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Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_90( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_146 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_145( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_188( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_332 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLWidthWidget32_4( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_62 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s5k3z4u_2 repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_74( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_54( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_74 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SharedFPFMA.scala:
package saturn.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
import saturn.insns._
trait HasSharedFPUIO {
implicit val p: Parameters
val io_fp_req = IO(Decoupled(new FPInput()))
val io_fp_active = IO(Output(Bool()))
val io_fp_resp = IO(Flipped(Valid(new FPResult())))
}
class SharedScalarElementwiseFPFMA(depth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit(depth)(p)
with HasFPUParameters
with HasSharedFPUIO {
val supported_insns = FPFMAFactory(depth, true).insns
val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq(
FPAdd, FPMul, FPSwapVdV2, FPFMACmd, ReadsVD, FPSpecRM, Wide2VD, Wide2VS2, Reduction))
val vs1_eew = io.pipe(0).bits.rvs1_eew
val vs2_eew = io.pipe(0).bits.rvs2_eew
val vd_eew = io.pipe(0).bits.vd_eew
val vd_eew64 = io.pipe(0).bits.vd_eew64
val vd_eew32 = io.pipe(0).bits.vd_eew32
val vd_eew16 = io.pipe(0).bits.vd_eew16
val eidx = Mux(io.pipe(0).bits.acc, 0.U, io.pipe(0).bits.eidx)
// Functional unit is ready if not currently running and the scalar FPU is available
io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched
io_fp_active := io.pipe.tail.map(_.valid).orR // head is pipe0, issuing the request
// Create FPInput
val req = Wire(new FPInput)
req.ldst := false.B
req.wen := false.B
req.ren1 := true.B
req.ren2 := true.B
req.ren3 := ctrl.bool(ReadsVD)
req.swap12 := false.B
req.swap23 := ctrl.bool(FPAdd) && !ctrl.bool(FPMul)
req.typeTagIn := Mux(vd_eew64, D, Mux(vd_eew32, S, H))
req.typeTagOut := Mux(vd_eew64, D, Mux(vd_eew32, S, H))
req.fromint := false.B
req.toint := false.B
req.fastpipe := false.B
req.fma := true.B
req.div := false.B
req.sqrt := false.B
req.wflags := true.B
req.vec := true.B
req.rm := io.pipe(0).bits.frm
req.fmaCmd := ctrl.uint(FPFMACmd)
req.typ := 0.U
req.fmt := 0.U
val rvs2_elem = io.pipe(0).bits.rvs2_elem
val rvs1_elem = io.pipe(0).bits.rvs1_elem
val rvd_elem = io.pipe(0).bits.rvd_elem
val h_rvs2 = FType.H.recode(rvs2_elem(15,0))
val h_rvs1 = FType.H.recode(rvs1_elem(15,0))
val h_rvd = FType.H.recode(rvd_elem(15,0))
// For widening operations, widen the narrow operands to compute with the scalar FPU
val h_widen_rvs1 = Module(new hardfloat.RecFNToRecFN(5, 11, 8, 24))
h_widen_rvs1.io.in := h_rvs1
h_widen_rvs1.io.roundingMode := io.pipe(0).bits.frm
h_widen_rvs1.io.detectTininess := hardfloat.consts.tininess_afterRounding
val h_widen_rvs2 = Module(new hardfloat.RecFNToRecFN(5, 11, 8, 24))
h_widen_rvs2.io.in := h_rvs2
h_widen_rvs2.io.roundingMode := io.pipe(0).bits.frm
h_widen_rvs2.io.detectTininess := hardfloat.consts.tininess_afterRounding
val s_rvs2 = FType.S.recode(rvs2_elem(31,0))
val s_rvs1 = FType.S.recode(rvs1_elem(31,0))
val s_rvd = FType.S.recode(rvd_elem(31,0))
// For widening operations, widen the narrow operands to compute with the scalar FPU
val s_widen_rvs1 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53))
s_widen_rvs1.io.in := s_rvs1
s_widen_rvs1.io.roundingMode := io.pipe(0).bits.frm
s_widen_rvs1.io.detectTininess := hardfloat.consts.tininess_afterRounding
val s_widen_rvs2 = Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53))
s_widen_rvs2.io.in := s_rvs2
s_widen_rvs2.io.roundingMode := io.pipe(0).bits.frm
s_widen_rvs2.io.detectTininess := hardfloat.consts.tininess_afterRounding
val d_rvs2 = FType.D.recode(rvs2_elem)
val d_rvs1 = FType.D.recode(rvs1_elem)
val d_rvd = FType.D.recode(rvd_elem)
val rvs2_recoded = Mux(vd_eew64, d_rvs2, Mux(vd_eew32, s_rvs2, h_rvs2))
val rvs1_recoded = Mux(vd_eew64, d_rvs1, Mux(vd_eew32, s_rvs1, h_rvs1))
val rvd_recoded = Mux(vd_eew64, d_rvd, Mux(vd_eew32, s_rvd, h_rvd))
// Set req.in1
when (ctrl.bool(FPSwapVdV2)) {
req.in1 := rvd_recoded
} .elsewhen (vs2_eew === 3.U) {
req.in1 := d_rvs2
} .elsewhen (ctrl.bool(Wide2VD) && vd_eew64) {
req.in1 := s_widen_rvs2.io.out
} .elsewhen (ctrl.bool(Wide2VD) && vd_eew32) {
req.in1 := h_widen_rvs2.io.out
} .elsewhen (vs2_eew === 2.U) {
req.in1 := s_rvs2
} .otherwise {
req.in1 := h_rvs2
}
// Set req.in2
when (vs1_eew === 3.U) {
req.in2 := d_rvs1
} .elsewhen (ctrl.bool(Wide2VD) && (vs1_eew === 2.U) && !io.pipe(0).bits.acc) {
req.in2 := s_widen_rvs1.io.out
} .elsewhen (ctrl.bool(Wide2VD) && (vs1_eew === 1.U) && !io.pipe(0).bits.acc) {
req.in2 := h_widen_rvs1.io.out
} .elsewhen (vs1_eew === 2.U) {
req.in2 := s_rvs1
} .otherwise {
req.in2 := h_rvs1
}
// Set req.in3
when (ctrl.bool(FPSwapVdV2)) {
req.in3 := rvs2_recoded
} .otherwise {
req.in3 := rvd_recoded
}
io_fp_req.bits := req
io_fp_req.valid := io.pipe(0).valid
io.pipe0_stall := !io_fp_req.ready
when (io.pipe(depth-1).valid) { assert(io_fp_resp.valid) }
io.write.valid := io.pipe(depth-1).valid
io.write.bits.eg := io.pipe(depth-1).bits.wvd_eg
io.write.bits.mask := FillInterleaved(8, io.pipe(depth-1).bits.wmask)
io.write.bits.data := Fill(dLenB >> 3, Mux(io.pipe(depth-1).bits.vd_eew === 3.U, FType.D.ieee(io_fp_resp.bits.data), Mux(io.pipe(depth-1).bits.vd_eew === 2.U,
Fill(2, FType.S.ieee(unbox(io_fp_resp.bits.data, S, Some(FType.S)))), Fill(4, FType.H.ieee(unbox(io_fp_resp.bits.data, H, Some(FType.H)))))))
io.set_fflags := DontCare
io.scalar_write.valid := false.B
io.scalar_write.bits := DontCare
io.set_vxsat := false.B
}
File FunctionalUnit.scala:
package saturn.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
import saturn.insns.{VectorInstruction}
abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val iss = new Bundle {
val valid = Input(Bool())
val op = Input(new ExecuteMicroOp)
val ready = Output(Bool())
}
val scalar_write = Decoupled(new ScalarWrite)
val set_vxsat = Output(Bool())
val set_fflags = Output(Valid(UInt(5.W)))
}
class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO {
val write = Valid(new VectorWrite(dLen))
val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp)))
val pipe0_stall = Output(Bool())
}
class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO {
val write = Decoupled(new VectorWrite(dLen))
val hazard = Output(Valid(new PipeHazard(10)))
val acc = Output(Bool())
val tail = Output(Bool())
val busy = Output(Bool())
}
trait FunctionalUnitFactory {
def insns: Seq[VectorInstruction]
def generate(implicit p: Parameters): FunctionalUnit
}
abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io: FunctionalUnitIO
}
abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) {
val io = IO(new PipelinedFunctionalUnitIO(depth))
require (depth > 0)
def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = {
val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) }
for (eew <- 0 until 3) {
val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq
for (i <- 0 until dLenB >> (eew + 1)) {
val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i))
val hi = Fill(16 << eew, lo((8 << eew)-1) && sext)
narrow_eew(eew)(i) := Cat(hi, lo)
}
}
VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W)))
}
}
abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) {
val io = IO(new IterativeFunctionalUnitIO)
val valid = RegInit(false.B)
val op = Reg(new ExecuteMicroOp)
val last = Wire(Bool())
io.busy := valid
io.hazard.bits.latency := DontCare
when (io.iss.valid && io.iss.ready) {
valid := true.B
op := io.iss.op
} .elsewhen (last) {
valid := false.B
}
}
File recFNFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object recFNFromFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val rawIn = rawFloatFromFN(expWidth, sigWidth, in)
rawIn.sign ##
(Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) |
Mux(rawIn.isNaN, 1.U, 0.U)) ##
rawIn.sExp(expWidth - 3, 0) ##
rawIn.sig(sigWidth - 2, 0)
}
}
File Bundles.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val debug_id = UInt(debugIdSz.W)
val base_offset = UInt(pgIdxBits.W)
val page = UInt((paddrBits - pgIdxBits).W)
val stride = UInt(pgIdxBits.W)
val segstart = UInt(3.W)
val segend = UInt(3.W)
val vstart = UInt(log2Ceil(maxVLMax).W)
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val mop = UInt(2.W)
val vm = Bool()
val nf = UInt(3.W)
val idx_size = UInt(2.W)
val elem_size = UInt(2.W)
val whole_reg = Bool()
val store = Bool()
val fast_sg = Bool()
def indexed = !mop.isOneOf(mopUnit, mopStrided)
def seg_nf = Mux(whole_reg, 0.U, nf)
def wr_nf = Mux(whole_reg, nf, 0.U)
}
class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val pc = UInt(vaddrBitsExtended.W)
val bits = UInt(32.W)
val vconfig = new VConfig
val vstart = UInt(log2Ceil(maxVLMax).W)
val segstart = UInt(3.W)
val segend = UInt(3.W)
val rs1_data = UInt(xLen.W)
val rs2_data = UInt(xLen.W)
val page = UInt((paddrBits - pgIdxBits).W)
val vat = UInt(vParams.vatSz.W)
val rm = UInt(3.W)
val emul = UInt(2.W)
val fast_sg = Bool()
val debug_id = UInt(debugIdSz.W)
val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this
def opcode = bits(6,0)
def store = opcode(5)
def mem_idx_size = bits(13,12)
def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12))
def vm = bits(25)
def orig_mop = bits(27,26)
def umop = bits(24,20)
def nf = bits(31,29)
def wr = orig_mop === mopUnit && umop === lumopWhole
def seg_nf = Mux(wr, 0.U, nf)
def wr_nf = Mux(wr, nf, 0.U)
def vmu = opcode.isOneOf(opcLoad, opcStore)
def rs1 = bits(19,15)
def rs2 = bits(24,20)
def rd = bits(11,7)
def may_write_v0 = rd === 0.U && opcode =/= opcStore
def funct3 = bits(14,12)
def imm5 = bits(19,15)
def imm5_sext = Cat(Fill(59, imm5(4)), imm5)
def funct6 = bits(31,26)
def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) || (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0))
def writes_frf = !vmu && (funct3 === OPFVV)
def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX)
def isOpm = funct3.isOneOf(OPMVV, OPMVX)
def isOpf = funct3.isOneOf(OPFVV, OPFVF)
def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal)
def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal)
def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal)
}
class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) {
val reduction = Bool() // accumulates into vd[0]
val scalar_to_vd0 = Bool() // mv scalar to vd[0]
val wide_vd = Bool() // vd reads/writes at 2xSEW
val wide_vs2 = Bool() // vs2 reads at 2xSEW
val writes_mask = Bool() // writes dest as a mask
val reads_vs1_mask = Bool() // vs1 read as mask
val reads_vs2_mask = Bool() // vs2 read as mask
val rs1_is_rs2 = Bool()
val nf_log2 = UInt(2.W)
val renv1 = Bool()
val renv2 = Bool()
val renvd = Bool()
val renvm = Bool()
val wvd = Bool()
}
class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) {
val seq = UInt(nSeqs.W)
}
class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eg = UInt(log2Ceil(32 * vLen / writeBits).W)
def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0)
val data = UInt(writeBits.W)
val mask = UInt(writeBits.W)
}
class ScalarWrite extends Bundle {
val data = UInt(64.W)
val fp = Bool()
val size = UInt(2.W)
val rd = UInt(5.W)
}
class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eg = UInt(log2Ceil(egsTotal).W)
val oldest = Bool()
}
class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val req = Decoupled(new VectorReadReq)
val resp = Input(UInt(dLen.W))
}
class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val ready = Output(Bool())
val valid = Input(Bool())
val vrs = Input(UInt(5.W))
val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W))
val eew = Input(UInt(2.W))
val idx = Output(UInt(64.W))
}
class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val ready = Output(Bool())
val valid = Input(Bool())
val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W))
val mask = Output(Bool())
}
class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val debug_id = UInt(debugIdSz.W)
val data = UInt(8.W)
val mask = Bool()
}
class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eidx = UInt(log2Ceil(maxVLMax).W)
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val rvs1_data = UInt(dLen.W)
val rvs2_data = UInt(dLen.W)
val rvd_data = UInt(dLen.W)
val rvm_data = UInt(dLen.W)
val rvs1_elem = UInt(64.W)
val rvs2_elem = UInt(64.W)
val rvd_elem = UInt(64.W)
val rvs1_eew = UInt(2.W)
val rvs2_eew = UInt(2.W)
val rvd_eew = UInt(2.W)
val vd_eew = UInt(2.W)
val rmask = UInt(dLenB.W)
val wmask = UInt(dLenB.W)
val full_tail_mask = UInt(dLen.W)
val wvd_eg = UInt(log2Ceil(egsTotal).W)
val funct3 = UInt(3.W)
def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX)
def isOpm = funct3.isOneOf(OPMVV, OPMVX)
def isOpf = funct3.isOneOf(OPFVV, OPFVF)
def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal)
def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal)
def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal)
def vd_eew8 = vd_eew === 0.U
def vd_eew16 = vd_eew === 1.U
def vd_eew32 = vd_eew === 2.U
def vd_eew64 = vd_eew === 3.U
val funct6 = UInt(6.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rd = UInt(5.W)
val vm = Bool()
val head = Bool()
val tail = Bool()
val vat = UInt(vParams.vatSz.W)
val acc = Bool()
val rm = UInt(3.W)
def vxrm = rm(1,0)
def frm = rm
}
class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val stdata = UInt(dLen.W)
val stmask = UInt(dLenB.W)
val debug_id = UInt(debugIdSz.W)
val tail = Bool()
val vat = UInt(vParams.vatSz.W)
def asMaskedBytes = {
val bytes = Wire(Vec(dLenB, new MaskedByte))
for (i <- 0 until dLenB) {
bytes(i).data := stdata(((i+1)*8)-1,i*8)
bytes(i).mask := stmask(i)
bytes(i).debug_id := debug_id
}
bytes
}
}
class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val wvd_eg = UInt(log2Ceil(egsTotal).W)
val wmask = UInt(dLenB.W)
val tail = Bool()
val debug_id = UInt(debugIdSz.W)
val vat = UInt(vParams.vatSz.W)
}
class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val renv2 = Bool()
val renvm = Bool()
val rvs2_data = UInt(dLen.W)
val eidx = UInt(log2Ceil(maxVLMax).W)
val rvs2_eew = UInt(2.W)
val rvm_data = UInt(dLen.W)
val vmu = Bool()
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val tail = Bool()
}
class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val latency = UInt(log2Ceil(pipe_depth).W)
val eg = UInt(log2Ceil(egsTotal).W)
def eg_oh = UIntToOH(eg)
}
class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val vat = UInt(vParams.vatSz.W)
val rintent = UInt(egsTotal.W)
val wintent = UInt(egsTotal.W)
}
class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val vat = UInt(vParams.vatSz.W)
val rintent = UInt(32.W)
val wintent = UInt(32.W)
}
| module SharedScalarElementwiseFPFMA( // @[SharedFPFMA.scala:19:7]
input clock, // @[SharedFPFMA.scala:19:7]
input reset, // @[SharedFPFMA.scala:19:7]
input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14]
input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14]
output io_iss_ready, // @[FunctionalUnit.scala:49:14]
output io_write_valid, // @[FunctionalUnit.scala:49:14]
output [4:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14]
output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14]
output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14]
input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14]
input [63:0] io_pipe_0_bits_rvs1_elem, // @[FunctionalUnit.scala:49:14]
input [63:0] io_pipe_0_bits_rvs2_elem, // @[FunctionalUnit.scala:49:14]
input [63:0] io_pipe_0_bits_rvd_elem, // @[FunctionalUnit.scala:49:14]
input [1:0] io_pipe_0_bits_rvs1_eew, // @[FunctionalUnit.scala:49:14]
input [1:0] io_pipe_0_bits_rvs2_eew, // @[FunctionalUnit.scala:49:14]
input [1:0] io_pipe_0_bits_vd_eew, // @[FunctionalUnit.scala:49:14]
input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14]
input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14]
input io_pipe_0_bits_acc, // @[FunctionalUnit.scala:49:14]
input [2:0] io_pipe_0_bits_rm, // @[FunctionalUnit.scala:49:14]
input io_pipe_1_valid, // @[FunctionalUnit.scala:49:14]
input io_pipe_2_valid, // @[FunctionalUnit.scala:49:14]
input io_pipe_3_valid, // @[FunctionalUnit.scala:49:14]
input [1:0] io_pipe_3_bits_vd_eew, // @[FunctionalUnit.scala:49:14]
input [7:0] io_pipe_3_bits_wmask, // @[FunctionalUnit.scala:49:14]
input [4:0] io_pipe_3_bits_wvd_eg, // @[FunctionalUnit.scala:49:14]
output io_pipe0_stall, // @[FunctionalUnit.scala:49:14]
input io_fp_req_ready, // @[SharedFPFMA.scala:14:21]
output io_fp_req_valid, // @[SharedFPFMA.scala:14:21]
output io_fp_req_bits_ren3, // @[SharedFPFMA.scala:14:21]
output io_fp_req_bits_swap23, // @[SharedFPFMA.scala:14:21]
output [1:0] io_fp_req_bits_typeTagIn, // @[SharedFPFMA.scala:14:21]
output [1:0] io_fp_req_bits_typeTagOut, // @[SharedFPFMA.scala:14:21]
output [2:0] io_fp_req_bits_rm, // @[SharedFPFMA.scala:14:21]
output [1:0] io_fp_req_bits_fmaCmd, // @[SharedFPFMA.scala:14:21]
output [64:0] io_fp_req_bits_in1, // @[SharedFPFMA.scala:14:21]
output [64:0] io_fp_req_bits_in2, // @[SharedFPFMA.scala:14:21]
output [64:0] io_fp_req_bits_in3, // @[SharedFPFMA.scala:14:21]
output io_fp_active, // @[SharedFPFMA.scala:15:24]
input io_fp_resp_valid, // @[SharedFPFMA.scala:16:22]
input [64:0] io_fp_resp_bits_data // @[SharedFPFMA.scala:16:22]
);
wire [64:0] _s_widen_rvs2_io_out; // @[SharedFPFMA.scala:94:28]
wire [64:0] _s_widen_rvs1_io_out; // @[SharedFPFMA.scala:89:28]
wire [32:0] _h_widen_rvs2_io_out; // @[SharedFPFMA.scala:79:28]
wire [32:0] _h_widen_rvs1_io_out; // @[SharedFPFMA.scala:74:28]
wire [4:0] _GEN = ~(io_pipe_0_bits_funct6[4:0]); // @[pla.scala:78:21]
wire [2:0] _decode_andMatrixOutputs_T_5 = {_GEN[2], io_pipe_0_bits_funct6[3], _GEN[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [1:0] _decode_andMatrixOutputs_T_7 = {io_pipe_0_bits_funct6[2], io_pipe_0_bits_funct6[3]}; // @[pla.scala:90:45, :98:53]
wire [1:0] _decode_andMatrixOutputs_T_8 = {_GEN[3], io_pipe_0_bits_funct6[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [1:0] _decode_andMatrixOutputs_T_10 = {io_pipe_0_bits_funct6[3], io_pipe_0_bits_funct6[4]}; // @[pla.scala:90:45, :98:53]
wire [2:0] _decode_andMatrixOutputs_T_11 = {io_pipe_0_bits_funct6[0], _GEN[4], io_pipe_0_bits_funct6[5]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [1:0] _decode_orMatrixOutputs_T_4 = {&_decode_andMatrixOutputs_T_8, &_decode_andMatrixOutputs_T_10}; // @[pla.scala:98:{53,70}, :114:19]
wire vd_eew32 = io_pipe_0_bits_vd_eew == 2'h2; // @[Bundles.scala:192:25]
wire [1:0] _GEN_0 = ~(io_iss_op_funct3[2:1]); // @[pla.scala:78:21]
wire [5:0] _GEN_1 = ~io_iss_op_funct6; // @[pla.scala:78:21]
wire [1:0] _GEN_2 = {1'h0, vd_eew32}; // @[SharedFPFMA.scala:50:23]
wire h_rvs2_rawIn_isZeroExpIn = io_pipe_0_bits_rvs2_elem[14:10] == 5'h0; // @[SharedFPFMA.scala:69:40]
wire [3:0] h_rvs2_rawIn_normDist = io_pipe_0_bits_rvs2_elem[9] ? 4'h0 : io_pipe_0_bits_rvs2_elem[8] ? 4'h1 : io_pipe_0_bits_rvs2_elem[7] ? 4'h2 : io_pipe_0_bits_rvs2_elem[6] ? 4'h3 : io_pipe_0_bits_rvs2_elem[5] ? 4'h4 : io_pipe_0_bits_rvs2_elem[4] ? 4'h5 : io_pipe_0_bits_rvs2_elem[3] ? 4'h6 : io_pipe_0_bits_rvs2_elem[2] ? 4'h7 : {3'h4, ~(io_pipe_0_bits_rvs2_elem[1])}; // @[Mux.scala:50:70]
wire [24:0] _h_rvs2_rawIn_subnormFract_T = {15'h0, io_pipe_0_bits_rvs2_elem[9:0]} << h_rvs2_rawIn_normDist; // @[Mux.scala:50:70]
wire [5:0] _h_rvs2_rawIn_adjustedExp_T_4 = (h_rvs2_rawIn_isZeroExpIn ? {2'h3, ~h_rvs2_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs2_elem[14:10]}) + {4'h4, h_rvs2_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [9:0] _h_rvs2_rawIn_out_sig_T_2 = h_rvs2_rawIn_isZeroExpIn ? {_h_rvs2_rawIn_subnormFract_T[8:0], 1'h0} : io_pipe_0_bits_rvs2_elem[9:0]; // @[SharedFPFMA.scala:69:40]
wire [2:0] _h_rvs2_T_2 = h_rvs2_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs2_elem[9:0])) ? 3'h0 : _h_rvs2_rawIn_adjustedExp_T_4[5:3]; // @[SharedFPFMA.scala:69:40]
wire _GEN_3 = _h_rvs2_T_2[0] | (&(_h_rvs2_rawIn_adjustedExp_T_4[5:4])) & (|(io_pipe_0_bits_rvs2_elem[9:0])); // @[SharedFPFMA.scala:69:40]
wire h_rvs1_rawIn_isZeroExpIn = io_pipe_0_bits_rvs1_elem[14:10] == 5'h0; // @[SharedFPFMA.scala:70:40]
wire [3:0] h_rvs1_rawIn_normDist = io_pipe_0_bits_rvs1_elem[9] ? 4'h0 : io_pipe_0_bits_rvs1_elem[8] ? 4'h1 : io_pipe_0_bits_rvs1_elem[7] ? 4'h2 : io_pipe_0_bits_rvs1_elem[6] ? 4'h3 : io_pipe_0_bits_rvs1_elem[5] ? 4'h4 : io_pipe_0_bits_rvs1_elem[4] ? 4'h5 : io_pipe_0_bits_rvs1_elem[3] ? 4'h6 : io_pipe_0_bits_rvs1_elem[2] ? 4'h7 : {3'h4, ~(io_pipe_0_bits_rvs1_elem[1])}; // @[Mux.scala:50:70]
wire [24:0] _h_rvs1_rawIn_subnormFract_T = {15'h0, io_pipe_0_bits_rvs1_elem[9:0]} << h_rvs1_rawIn_normDist; // @[Mux.scala:50:70]
wire [5:0] _h_rvs1_rawIn_adjustedExp_T_4 = (h_rvs1_rawIn_isZeroExpIn ? {2'h3, ~h_rvs1_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs1_elem[14:10]}) + {4'h4, h_rvs1_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [9:0] _h_rvs1_rawIn_out_sig_T_2 = h_rvs1_rawIn_isZeroExpIn ? {_h_rvs1_rawIn_subnormFract_T[8:0], 1'h0} : io_pipe_0_bits_rvs1_elem[9:0]; // @[SharedFPFMA.scala:70:40]
wire [2:0] _h_rvs1_T_2 = h_rvs1_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs1_elem[9:0])) ? 3'h0 : _h_rvs1_rawIn_adjustedExp_T_4[5:3]; // @[SharedFPFMA.scala:70:40]
wire _GEN_4 = _h_rvs1_T_2[0] | (&(_h_rvs1_rawIn_adjustedExp_T_4[5:4])) & (|(io_pipe_0_bits_rvs1_elem[9:0])); // @[SharedFPFMA.scala:70:40]
wire h_rvd_rawIn_isZeroExpIn = io_pipe_0_bits_rvd_elem[14:10] == 5'h0; // @[SharedFPFMA.scala:71:38]
wire [3:0] h_rvd_rawIn_normDist = io_pipe_0_bits_rvd_elem[9] ? 4'h0 : io_pipe_0_bits_rvd_elem[8] ? 4'h1 : io_pipe_0_bits_rvd_elem[7] ? 4'h2 : io_pipe_0_bits_rvd_elem[6] ? 4'h3 : io_pipe_0_bits_rvd_elem[5] ? 4'h4 : io_pipe_0_bits_rvd_elem[4] ? 4'h5 : io_pipe_0_bits_rvd_elem[3] ? 4'h6 : io_pipe_0_bits_rvd_elem[2] ? 4'h7 : {3'h4, ~(io_pipe_0_bits_rvd_elem[1])}; // @[Mux.scala:50:70]
wire [24:0] _h_rvd_rawIn_subnormFract_T = {15'h0, io_pipe_0_bits_rvd_elem[9:0]} << h_rvd_rawIn_normDist; // @[Mux.scala:50:70]
wire [5:0] _h_rvd_rawIn_adjustedExp_T_4 = (h_rvd_rawIn_isZeroExpIn ? {2'h3, ~h_rvd_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvd_elem[14:10]}) + {4'h4, h_rvd_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _h_rvd_T_2 = h_rvd_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvd_elem[9:0])) ? 3'h0 : _h_rvd_rawIn_adjustedExp_T_4[5:3]; // @[SharedFPFMA.scala:71:38]
wire s_rvs2_rawIn_isZeroExpIn = io_pipe_0_bits_rvs2_elem[30:23] == 8'h0; // @[SharedFPFMA.scala:84:40]
wire [4:0] s_rvs2_rawIn_normDist = io_pipe_0_bits_rvs2_elem[22] ? 5'h0 : io_pipe_0_bits_rvs2_elem[21] ? 5'h1 : io_pipe_0_bits_rvs2_elem[20] ? 5'h2 : io_pipe_0_bits_rvs2_elem[19] ? 5'h3 : io_pipe_0_bits_rvs2_elem[18] ? 5'h4 : io_pipe_0_bits_rvs2_elem[17] ? 5'h5 : io_pipe_0_bits_rvs2_elem[16] ? 5'h6 : io_pipe_0_bits_rvs2_elem[15] ? 5'h7 : io_pipe_0_bits_rvs2_elem[14] ? 5'h8 : io_pipe_0_bits_rvs2_elem[13] ? 5'h9 : io_pipe_0_bits_rvs2_elem[12] ? 5'hA : io_pipe_0_bits_rvs2_elem[11] ? 5'hB : io_pipe_0_bits_rvs2_elem[10] ? 5'hC : io_pipe_0_bits_rvs2_elem[9] ? 5'hD : io_pipe_0_bits_rvs2_elem[8] ? 5'hE : io_pipe_0_bits_rvs2_elem[7] ? 5'hF : io_pipe_0_bits_rvs2_elem[6] ? 5'h10 : io_pipe_0_bits_rvs2_elem[5] ? 5'h11 : io_pipe_0_bits_rvs2_elem[4] ? 5'h12 : io_pipe_0_bits_rvs2_elem[3] ? 5'h13 : io_pipe_0_bits_rvs2_elem[2] ? 5'h14 : io_pipe_0_bits_rvs2_elem[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [53:0] _s_rvs2_rawIn_subnormFract_T = {31'h0, io_pipe_0_bits_rvs2_elem[22:0]} << s_rvs2_rawIn_normDist; // @[Mux.scala:50:70]
wire [8:0] _s_rvs2_rawIn_adjustedExp_T_4 = (s_rvs2_rawIn_isZeroExpIn ? {4'hF, ~s_rvs2_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs2_elem[30:23]}) + {7'h20, s_rvs2_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [22:0] _s_rvs2_rawIn_out_sig_T_2 = s_rvs2_rawIn_isZeroExpIn ? {_s_rvs2_rawIn_subnormFract_T[21:0], 1'h0} : io_pipe_0_bits_rvs2_elem[22:0]; // @[SharedFPFMA.scala:84:40]
wire [2:0] _s_rvs2_T_2 = s_rvs2_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs2_elem[22:0])) ? 3'h0 : _s_rvs2_rawIn_adjustedExp_T_4[8:6]; // @[SharedFPFMA.scala:84:40]
wire _GEN_5 = _s_rvs2_T_2[0] | (&(_s_rvs2_rawIn_adjustedExp_T_4[8:7])) & (|(io_pipe_0_bits_rvs2_elem[22:0])); // @[SharedFPFMA.scala:84:40]
wire [32:0] s_rvs2 = {io_pipe_0_bits_rvs2_elem[31], _s_rvs2_T_2[2:1], _GEN_5, _s_rvs2_rawIn_adjustedExp_T_4[5:0], _s_rvs2_rawIn_out_sig_T_2}; // @[SharedFPFMA.scala:84:40]
wire s_rvs1_rawIn_isZeroExpIn = io_pipe_0_bits_rvs1_elem[30:23] == 8'h0; // @[SharedFPFMA.scala:85:40]
wire [4:0] s_rvs1_rawIn_normDist = io_pipe_0_bits_rvs1_elem[22] ? 5'h0 : io_pipe_0_bits_rvs1_elem[21] ? 5'h1 : io_pipe_0_bits_rvs1_elem[20] ? 5'h2 : io_pipe_0_bits_rvs1_elem[19] ? 5'h3 : io_pipe_0_bits_rvs1_elem[18] ? 5'h4 : io_pipe_0_bits_rvs1_elem[17] ? 5'h5 : io_pipe_0_bits_rvs1_elem[16] ? 5'h6 : io_pipe_0_bits_rvs1_elem[15] ? 5'h7 : io_pipe_0_bits_rvs1_elem[14] ? 5'h8 : io_pipe_0_bits_rvs1_elem[13] ? 5'h9 : io_pipe_0_bits_rvs1_elem[12] ? 5'hA : io_pipe_0_bits_rvs1_elem[11] ? 5'hB : io_pipe_0_bits_rvs1_elem[10] ? 5'hC : io_pipe_0_bits_rvs1_elem[9] ? 5'hD : io_pipe_0_bits_rvs1_elem[8] ? 5'hE : io_pipe_0_bits_rvs1_elem[7] ? 5'hF : io_pipe_0_bits_rvs1_elem[6] ? 5'h10 : io_pipe_0_bits_rvs1_elem[5] ? 5'h11 : io_pipe_0_bits_rvs1_elem[4] ? 5'h12 : io_pipe_0_bits_rvs1_elem[3] ? 5'h13 : io_pipe_0_bits_rvs1_elem[2] ? 5'h14 : io_pipe_0_bits_rvs1_elem[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [53:0] _s_rvs1_rawIn_subnormFract_T = {31'h0, io_pipe_0_bits_rvs1_elem[22:0]} << s_rvs1_rawIn_normDist; // @[Mux.scala:50:70]
wire [8:0] _s_rvs1_rawIn_adjustedExp_T_4 = (s_rvs1_rawIn_isZeroExpIn ? {4'hF, ~s_rvs1_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs1_elem[30:23]}) + {7'h20, s_rvs1_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [22:0] _s_rvs1_rawIn_out_sig_T_2 = s_rvs1_rawIn_isZeroExpIn ? {_s_rvs1_rawIn_subnormFract_T[21:0], 1'h0} : io_pipe_0_bits_rvs1_elem[22:0]; // @[SharedFPFMA.scala:85:40]
wire [2:0] _s_rvs1_T_2 = s_rvs1_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs1_elem[22:0])) ? 3'h0 : _s_rvs1_rawIn_adjustedExp_T_4[8:6]; // @[SharedFPFMA.scala:85:40]
wire _GEN_6 = _s_rvs1_T_2[0] | (&(_s_rvs1_rawIn_adjustedExp_T_4[8:7])) & (|(io_pipe_0_bits_rvs1_elem[22:0])); // @[SharedFPFMA.scala:85:40]
wire s_rvd_rawIn_isZeroExpIn = io_pipe_0_bits_rvd_elem[30:23] == 8'h0; // @[SharedFPFMA.scala:86:38]
wire [4:0] s_rvd_rawIn_normDist = io_pipe_0_bits_rvd_elem[22] ? 5'h0 : io_pipe_0_bits_rvd_elem[21] ? 5'h1 : io_pipe_0_bits_rvd_elem[20] ? 5'h2 : io_pipe_0_bits_rvd_elem[19] ? 5'h3 : io_pipe_0_bits_rvd_elem[18] ? 5'h4 : io_pipe_0_bits_rvd_elem[17] ? 5'h5 : io_pipe_0_bits_rvd_elem[16] ? 5'h6 : io_pipe_0_bits_rvd_elem[15] ? 5'h7 : io_pipe_0_bits_rvd_elem[14] ? 5'h8 : io_pipe_0_bits_rvd_elem[13] ? 5'h9 : io_pipe_0_bits_rvd_elem[12] ? 5'hA : io_pipe_0_bits_rvd_elem[11] ? 5'hB : io_pipe_0_bits_rvd_elem[10] ? 5'hC : io_pipe_0_bits_rvd_elem[9] ? 5'hD : io_pipe_0_bits_rvd_elem[8] ? 5'hE : io_pipe_0_bits_rvd_elem[7] ? 5'hF : io_pipe_0_bits_rvd_elem[6] ? 5'h10 : io_pipe_0_bits_rvd_elem[5] ? 5'h11 : io_pipe_0_bits_rvd_elem[4] ? 5'h12 : io_pipe_0_bits_rvd_elem[3] ? 5'h13 : io_pipe_0_bits_rvd_elem[2] ? 5'h14 : io_pipe_0_bits_rvd_elem[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [53:0] _s_rvd_rawIn_subnormFract_T = {31'h0, io_pipe_0_bits_rvd_elem[22:0]} << s_rvd_rawIn_normDist; // @[Mux.scala:50:70]
wire [8:0] _s_rvd_rawIn_adjustedExp_T_4 = (s_rvd_rawIn_isZeroExpIn ? {4'hF, ~s_rvd_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvd_elem[30:23]}) + {7'h20, s_rvd_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _s_rvd_T_2 = s_rvd_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvd_elem[22:0])) ? 3'h0 : _s_rvd_rawIn_adjustedExp_T_4[8:6]; // @[SharedFPFMA.scala:86:38]
wire d_rvs2_rawIn_isZeroExpIn = io_pipe_0_bits_rvs2_elem[62:52] == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire [5:0] d_rvs2_rawIn_normDist = io_pipe_0_bits_rvs2_elem[51] ? 6'h0 : io_pipe_0_bits_rvs2_elem[50] ? 6'h1 : io_pipe_0_bits_rvs2_elem[49] ? 6'h2 : io_pipe_0_bits_rvs2_elem[48] ? 6'h3 : io_pipe_0_bits_rvs2_elem[47] ? 6'h4 : io_pipe_0_bits_rvs2_elem[46] ? 6'h5 : io_pipe_0_bits_rvs2_elem[45] ? 6'h6 : io_pipe_0_bits_rvs2_elem[44] ? 6'h7 : io_pipe_0_bits_rvs2_elem[43] ? 6'h8 : io_pipe_0_bits_rvs2_elem[42] ? 6'h9 : io_pipe_0_bits_rvs2_elem[41] ? 6'hA : io_pipe_0_bits_rvs2_elem[40] ? 6'hB : io_pipe_0_bits_rvs2_elem[39] ? 6'hC : io_pipe_0_bits_rvs2_elem[38] ? 6'hD : io_pipe_0_bits_rvs2_elem[37] ? 6'hE : io_pipe_0_bits_rvs2_elem[36] ? 6'hF : io_pipe_0_bits_rvs2_elem[35] ? 6'h10 : io_pipe_0_bits_rvs2_elem[34] ? 6'h11 : io_pipe_0_bits_rvs2_elem[33] ? 6'h12 : io_pipe_0_bits_rvs2_elem[32] ? 6'h13 : io_pipe_0_bits_rvs2_elem[31] ? 6'h14 : io_pipe_0_bits_rvs2_elem[30] ? 6'h15 : io_pipe_0_bits_rvs2_elem[29] ? 6'h16 : io_pipe_0_bits_rvs2_elem[28] ? 6'h17 : io_pipe_0_bits_rvs2_elem[27] ? 6'h18 : io_pipe_0_bits_rvs2_elem[26] ? 6'h19 : io_pipe_0_bits_rvs2_elem[25] ? 6'h1A : io_pipe_0_bits_rvs2_elem[24] ? 6'h1B : io_pipe_0_bits_rvs2_elem[23] ? 6'h1C : io_pipe_0_bits_rvs2_elem[22] ? 6'h1D : io_pipe_0_bits_rvs2_elem[21] ? 6'h1E : io_pipe_0_bits_rvs2_elem[20] ? 6'h1F : io_pipe_0_bits_rvs2_elem[19] ? 6'h20 : io_pipe_0_bits_rvs2_elem[18] ? 6'h21 : io_pipe_0_bits_rvs2_elem[17] ? 6'h22 : io_pipe_0_bits_rvs2_elem[16] ? 6'h23 : io_pipe_0_bits_rvs2_elem[15] ? 6'h24 : io_pipe_0_bits_rvs2_elem[14] ? 6'h25 : io_pipe_0_bits_rvs2_elem[13] ? 6'h26 : io_pipe_0_bits_rvs2_elem[12] ? 6'h27 : io_pipe_0_bits_rvs2_elem[11] ? 6'h28 : io_pipe_0_bits_rvs2_elem[10] ? 6'h29 : io_pipe_0_bits_rvs2_elem[9] ? 6'h2A : io_pipe_0_bits_rvs2_elem[8] ? 6'h2B : io_pipe_0_bits_rvs2_elem[7] ? 6'h2C : io_pipe_0_bits_rvs2_elem[6] ? 6'h2D : io_pipe_0_bits_rvs2_elem[5] ? 6'h2E : io_pipe_0_bits_rvs2_elem[4] ? 6'h2F : io_pipe_0_bits_rvs2_elem[3] ? 6'h30 : io_pipe_0_bits_rvs2_elem[2] ? 6'h31 : {5'h19, ~(io_pipe_0_bits_rvs2_elem[1])}; // @[Mux.scala:50:70]
wire [114:0] _d_rvs2_rawIn_subnormFract_T = {63'h0, io_pipe_0_bits_rvs2_elem[51:0]} << d_rvs2_rawIn_normDist; // @[Mux.scala:50:70]
wire [11:0] _d_rvs2_rawIn_adjustedExp_T_4 = (d_rvs2_rawIn_isZeroExpIn ? {6'h3F, ~d_rvs2_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs2_elem[62:52]}) + {10'h100, d_rvs2_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _d_rvs2_T_1 = d_rvs2_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs2_elem[51:0])) ? 3'h0 : _d_rvs2_rawIn_adjustedExp_T_4[11:9]; // @[recFNFromFN.scala:48:{15,50}]
wire [64:0] d_rvs2 = {io_pipe_0_bits_rvs2_elem[63], _d_rvs2_T_1[2:1], _d_rvs2_T_1[0] | (&(_d_rvs2_rawIn_adjustedExp_T_4[11:10])) & (|(io_pipe_0_bits_rvs2_elem[51:0])), _d_rvs2_rawIn_adjustedExp_T_4[8:0], d_rvs2_rawIn_isZeroExpIn ? {_d_rvs2_rawIn_subnormFract_T[50:0], 1'h0} : io_pipe_0_bits_rvs2_elem[51:0]}; // @[recFNFromFN.scala:48:{15,76}, :50:{23,41}]
wire d_rvs1_rawIn_isZeroExpIn = io_pipe_0_bits_rvs1_elem[62:52] == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire [5:0] d_rvs1_rawIn_normDist = io_pipe_0_bits_rvs1_elem[51] ? 6'h0 : io_pipe_0_bits_rvs1_elem[50] ? 6'h1 : io_pipe_0_bits_rvs1_elem[49] ? 6'h2 : io_pipe_0_bits_rvs1_elem[48] ? 6'h3 : io_pipe_0_bits_rvs1_elem[47] ? 6'h4 : io_pipe_0_bits_rvs1_elem[46] ? 6'h5 : io_pipe_0_bits_rvs1_elem[45] ? 6'h6 : io_pipe_0_bits_rvs1_elem[44] ? 6'h7 : io_pipe_0_bits_rvs1_elem[43] ? 6'h8 : io_pipe_0_bits_rvs1_elem[42] ? 6'h9 : io_pipe_0_bits_rvs1_elem[41] ? 6'hA : io_pipe_0_bits_rvs1_elem[40] ? 6'hB : io_pipe_0_bits_rvs1_elem[39] ? 6'hC : io_pipe_0_bits_rvs1_elem[38] ? 6'hD : io_pipe_0_bits_rvs1_elem[37] ? 6'hE : io_pipe_0_bits_rvs1_elem[36] ? 6'hF : io_pipe_0_bits_rvs1_elem[35] ? 6'h10 : io_pipe_0_bits_rvs1_elem[34] ? 6'h11 : io_pipe_0_bits_rvs1_elem[33] ? 6'h12 : io_pipe_0_bits_rvs1_elem[32] ? 6'h13 : io_pipe_0_bits_rvs1_elem[31] ? 6'h14 : io_pipe_0_bits_rvs1_elem[30] ? 6'h15 : io_pipe_0_bits_rvs1_elem[29] ? 6'h16 : io_pipe_0_bits_rvs1_elem[28] ? 6'h17 : io_pipe_0_bits_rvs1_elem[27] ? 6'h18 : io_pipe_0_bits_rvs1_elem[26] ? 6'h19 : io_pipe_0_bits_rvs1_elem[25] ? 6'h1A : io_pipe_0_bits_rvs1_elem[24] ? 6'h1B : io_pipe_0_bits_rvs1_elem[23] ? 6'h1C : io_pipe_0_bits_rvs1_elem[22] ? 6'h1D : io_pipe_0_bits_rvs1_elem[21] ? 6'h1E : io_pipe_0_bits_rvs1_elem[20] ? 6'h1F : io_pipe_0_bits_rvs1_elem[19] ? 6'h20 : io_pipe_0_bits_rvs1_elem[18] ? 6'h21 : io_pipe_0_bits_rvs1_elem[17] ? 6'h22 : io_pipe_0_bits_rvs1_elem[16] ? 6'h23 : io_pipe_0_bits_rvs1_elem[15] ? 6'h24 : io_pipe_0_bits_rvs1_elem[14] ? 6'h25 : io_pipe_0_bits_rvs1_elem[13] ? 6'h26 : io_pipe_0_bits_rvs1_elem[12] ? 6'h27 : io_pipe_0_bits_rvs1_elem[11] ? 6'h28 : io_pipe_0_bits_rvs1_elem[10] ? 6'h29 : io_pipe_0_bits_rvs1_elem[9] ? 6'h2A : io_pipe_0_bits_rvs1_elem[8] ? 6'h2B : io_pipe_0_bits_rvs1_elem[7] ? 6'h2C : io_pipe_0_bits_rvs1_elem[6] ? 6'h2D : io_pipe_0_bits_rvs1_elem[5] ? 6'h2E : io_pipe_0_bits_rvs1_elem[4] ? 6'h2F : io_pipe_0_bits_rvs1_elem[3] ? 6'h30 : io_pipe_0_bits_rvs1_elem[2] ? 6'h31 : {5'h19, ~(io_pipe_0_bits_rvs1_elem[1])}; // @[Mux.scala:50:70]
wire [114:0] _d_rvs1_rawIn_subnormFract_T = {63'h0, io_pipe_0_bits_rvs1_elem[51:0]} << d_rvs1_rawIn_normDist; // @[Mux.scala:50:70]
wire [11:0] _d_rvs1_rawIn_adjustedExp_T_4 = (d_rvs1_rawIn_isZeroExpIn ? {6'h3F, ~d_rvs1_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvs1_elem[62:52]}) + {10'h100, d_rvs1_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _d_rvs1_T_1 = d_rvs1_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvs1_elem[51:0])) ? 3'h0 : _d_rvs1_rawIn_adjustedExp_T_4[11:9]; // @[recFNFromFN.scala:48:{15,50}]
wire d_rvd_rawIn_isZeroExpIn = io_pipe_0_bits_rvd_elem[62:52] == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire [5:0] d_rvd_rawIn_normDist = io_pipe_0_bits_rvd_elem[51] ? 6'h0 : io_pipe_0_bits_rvd_elem[50] ? 6'h1 : io_pipe_0_bits_rvd_elem[49] ? 6'h2 : io_pipe_0_bits_rvd_elem[48] ? 6'h3 : io_pipe_0_bits_rvd_elem[47] ? 6'h4 : io_pipe_0_bits_rvd_elem[46] ? 6'h5 : io_pipe_0_bits_rvd_elem[45] ? 6'h6 : io_pipe_0_bits_rvd_elem[44] ? 6'h7 : io_pipe_0_bits_rvd_elem[43] ? 6'h8 : io_pipe_0_bits_rvd_elem[42] ? 6'h9 : io_pipe_0_bits_rvd_elem[41] ? 6'hA : io_pipe_0_bits_rvd_elem[40] ? 6'hB : io_pipe_0_bits_rvd_elem[39] ? 6'hC : io_pipe_0_bits_rvd_elem[38] ? 6'hD : io_pipe_0_bits_rvd_elem[37] ? 6'hE : io_pipe_0_bits_rvd_elem[36] ? 6'hF : io_pipe_0_bits_rvd_elem[35] ? 6'h10 : io_pipe_0_bits_rvd_elem[34] ? 6'h11 : io_pipe_0_bits_rvd_elem[33] ? 6'h12 : io_pipe_0_bits_rvd_elem[32] ? 6'h13 : io_pipe_0_bits_rvd_elem[31] ? 6'h14 : io_pipe_0_bits_rvd_elem[30] ? 6'h15 : io_pipe_0_bits_rvd_elem[29] ? 6'h16 : io_pipe_0_bits_rvd_elem[28] ? 6'h17 : io_pipe_0_bits_rvd_elem[27] ? 6'h18 : io_pipe_0_bits_rvd_elem[26] ? 6'h19 : io_pipe_0_bits_rvd_elem[25] ? 6'h1A : io_pipe_0_bits_rvd_elem[24] ? 6'h1B : io_pipe_0_bits_rvd_elem[23] ? 6'h1C : io_pipe_0_bits_rvd_elem[22] ? 6'h1D : io_pipe_0_bits_rvd_elem[21] ? 6'h1E : io_pipe_0_bits_rvd_elem[20] ? 6'h1F : io_pipe_0_bits_rvd_elem[19] ? 6'h20 : io_pipe_0_bits_rvd_elem[18] ? 6'h21 : io_pipe_0_bits_rvd_elem[17] ? 6'h22 : io_pipe_0_bits_rvd_elem[16] ? 6'h23 : io_pipe_0_bits_rvd_elem[15] ? 6'h24 : io_pipe_0_bits_rvd_elem[14] ? 6'h25 : io_pipe_0_bits_rvd_elem[13] ? 6'h26 : io_pipe_0_bits_rvd_elem[12] ? 6'h27 : io_pipe_0_bits_rvd_elem[11] ? 6'h28 : io_pipe_0_bits_rvd_elem[10] ? 6'h29 : io_pipe_0_bits_rvd_elem[9] ? 6'h2A : io_pipe_0_bits_rvd_elem[8] ? 6'h2B : io_pipe_0_bits_rvd_elem[7] ? 6'h2C : io_pipe_0_bits_rvd_elem[6] ? 6'h2D : io_pipe_0_bits_rvd_elem[5] ? 6'h2E : io_pipe_0_bits_rvd_elem[4] ? 6'h2F : io_pipe_0_bits_rvd_elem[3] ? 6'h30 : io_pipe_0_bits_rvd_elem[2] ? 6'h31 : {5'h19, ~(io_pipe_0_bits_rvd_elem[1])}; // @[Mux.scala:50:70]
wire [114:0] _d_rvd_rawIn_subnormFract_T = {63'h0, io_pipe_0_bits_rvd_elem[51:0]} << d_rvd_rawIn_normDist; // @[Mux.scala:50:70]
wire [11:0] _d_rvd_rawIn_adjustedExp_T_4 = (d_rvd_rawIn_isZeroExpIn ? {6'h3F, ~d_rvd_rawIn_normDist} : {1'h0, io_pipe_0_bits_rvd_elem[62:52]}) + {10'h100, d_rvd_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _d_rvd_T_1 = d_rvd_rawIn_isZeroExpIn & ~(|(io_pipe_0_bits_rvd_elem[51:0])) ? 3'h0 : _d_rvd_rawIn_adjustedExp_T_4[11:9]; // @[recFNFromFN.scala:48:{15,50}]
wire [64:0] rvd_recoded = (&io_pipe_0_bits_vd_eew) ? {io_pipe_0_bits_rvd_elem[63], _d_rvd_T_1[2:1], _d_rvd_T_1[0] | (&(_d_rvd_rawIn_adjustedExp_T_4[11:10])) & (|(io_pipe_0_bits_rvd_elem[51:0])), _d_rvd_rawIn_adjustedExp_T_4[8:0], d_rvd_rawIn_isZeroExpIn ? {_d_rvd_rawIn_subnormFract_T[50:0], 1'h0} : io_pipe_0_bits_rvd_elem[51:0]} : {32'h0, vd_eew32 ? {io_pipe_0_bits_rvd_elem[31], _s_rvd_T_2[2:1], _s_rvd_T_2[0] | (&(_s_rvd_rawIn_adjustedExp_T_4[8:7])) & (|(io_pipe_0_bits_rvd_elem[22:0])), _s_rvd_rawIn_adjustedExp_T_4[5:0], s_rvd_rawIn_isZeroExpIn ? {_s_rvd_rawIn_subnormFract_T[21:0], 1'h0} : io_pipe_0_bits_rvd_elem[22:0]} : {16'h0, io_pipe_0_bits_rvd_elem[15], _h_rvd_T_2[2:1], _h_rvd_T_2[0] | (&(_h_rvd_rawIn_adjustedExp_T_4[5:4])) & (|(io_pipe_0_bits_rvd_elem[9:0])), _h_rvd_rawIn_adjustedExp_T_4[2:0], h_rvd_rawIn_isZeroExpIn ? {_h_rvd_rawIn_subnormFract_T[8:0], 1'h0} : io_pipe_0_bits_rvd_elem[9:0]}}; // @[SharedFPFMA.scala:71:38, :86:38, :105:{24,45}]
wire _GEN_7 = io_pipe_0_bits_rvs1_eew == 2'h2; // @[SharedFPFMA.scala:125:47] |
Generate the Verilog code corresponding to the following Chisel files.
File composer.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
class ComposedBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val (components, resp) = getBPDComponents(io.resp_in(0), p)
io.resp := resp
var metas = 0.U(1.W)
var meta_sz = 0
for (c <- components) {
c.io.f0_valid := io.f0_valid
c.io.f0_pc := io.f0_pc
c.io.f0_mask := io.f0_mask
c.io.f1_ghist := io.f1_ghist
c.io.f1_lhist := io.f1_lhist
c.io.f3_fire := io.f3_fire
if (c.metaSz > 0) {
metas = (metas << c.metaSz) | c.io.f3_meta(c.metaSz-1,0)
}
meta_sz = meta_sz + c.metaSz
}
require(meta_sz < bpdMaxMetaLength)
io.f3_meta := metas
var update_meta = io.update.bits.meta
for (c <- components.reverse) {
c.io.update := io.update
c.io.update.bits.meta := update_meta
update_meta = update_meta >> c.metaSz
}
val mems = components.map(_.mems).flatten
}
File predictor.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
// A branch prediction for a single instruction
class BranchPrediction(implicit p: Parameters) extends BoomBundle()(p)
{
// If this is a branch, do we take it?
val taken = Bool()
// Is this a branch?
val is_br = Bool()
// Is this a JAL?
val is_jal = Bool()
// What is the target of his branch/jump? Do we know the target?
val predicted_pc = Valid(UInt(vaddrBitsExtended.W))
}
// A branch prediction for a entire fetch-width worth of instructions
// This is typically merged from individual predictions from the banked
// predictor
class BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val pc = UInt(vaddrBitsExtended.W)
val preds = Vec(fetchWidth, new BranchPrediction)
val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W)))
}
// A branch update for a fetch-width worth of instructions
class BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
// Indicates that this update is due to a speculated misprediction
// Local predictors typically update themselves with speculative info
// Global predictors only care about non-speculative updates
val is_mispredict_update = Bool()
val is_repair_update = Bool()
val btb_mispredicts = UInt(fetchWidth.W)
def is_btb_mispredict_update = btb_mispredicts =/= 0.U
def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)
val pc = UInt(vaddrBitsExtended.W)
// Mask of instructions which are branches.
// If these are not cfi_idx, then they were predicted not taken
val br_mask = UInt(fetchWidth.W)
// Which CFI was taken/mispredicted (if any)
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the cfi taken?
val cfi_taken = Bool()
// Was the cfi mispredicted from the original prediction?
val cfi_mispredicted = Bool()
// Was the cfi a br?
val cfi_is_br = Bool()
// Was the cfi a jal/jalr?
val cfi_is_jal = Bool()
// Was the cfi a jalr
val cfi_is_jalr = Bool()
//val cfi_is_ret = Bool()
val ghist = new GlobalHistory
val lhist = Vec(nBanks, UInt(localHistoryLength.W))
// What did this CFI jump to?
val target = UInt(vaddrBitsExtended.W)
val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
// A branch update to a single bank
class BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val is_mispredict_update = Bool()
val is_repair_update = Bool()
val btb_mispredicts = UInt(bankWidth.W)
def is_btb_mispredict_update = btb_mispredicts =/= 0.U
def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)
val pc = UInt(vaddrBitsExtended.W)
val br_mask = UInt(bankWidth.W)
val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W))
val cfi_taken = Bool()
val cfi_mispredicted = Bool()
val cfi_is_br = Bool()
val cfi_is_jal = Bool()
val cfi_is_jalr = Bool()
val ghist = UInt(globalHistoryLength.W)
val lhist = UInt(localHistoryLength.W)
val target = UInt(vaddrBitsExtended.W)
val meta = UInt(bpdMaxMetaLength.W)
}
class BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p)
{
val pc = UInt(vaddrBitsExtended.W)
val ghist = new GlobalHistory
}
class BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val f1 = Vec(bankWidth, new BranchPrediction)
val f2 = Vec(bankWidth, new BranchPrediction)
val f3 = Vec(bankWidth, new BranchPrediction)
}
abstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
val metaSz = 0
def nInputs = 1
val mems: Seq[Tuple3[String, Int, Int]]
val io = IO(new Bundle {
val f0_valid = Input(Bool())
val f0_pc = Input(UInt(vaddrBitsExtended.W))
val f0_mask = Input(UInt(bankWidth.W))
// Local history not available until end of f1
val f1_ghist = Input(UInt(globalHistoryLength.W))
val f1_lhist = Input(UInt(localHistoryLength.W))
val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse))
val resp = Output(new BranchPredictionBankResponse)
// Store the meta as a UInt, use width inference to figure out the shape
val f3_meta = Output(UInt(bpdMaxMetaLength.W))
val f3_fire = Input(Bool())
val update = Input(Valid(new BranchPredictionBankUpdate))
})
io.resp := io.resp_in(0)
io.f3_meta := 0.U
val s0_idx = fetchIdx(io.f0_pc)
val s1_idx = RegNext(s0_idx)
val s2_idx = RegNext(s1_idx)
val s3_idx = RegNext(s2_idx)
val s0_valid = io.f0_valid
val s1_valid = RegNext(s0_valid)
val s2_valid = RegNext(s1_valid)
val s3_valid = RegNext(s2_valid)
val s0_mask = io.f0_mask
val s1_mask = RegNext(s0_mask)
val s2_mask = RegNext(s1_mask)
val s3_mask = RegNext(s2_mask)
val s0_pc = io.f0_pc
val s1_pc = RegNext(s0_pc)
val s0_update = io.update
val s0_update_idx = fetchIdx(io.update.bits.pc)
val s0_update_valid = io.update.valid
val s1_update = RegNext(s0_update)
val s1_update_idx = RegNext(s0_update_idx)
val s1_update_valid = RegNext(s0_update_valid)
}
class BranchPredictor(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
val io = IO(new Bundle {
// Requests and responses
val f0_req = Input(Valid(new BranchPredictionRequest))
val resp = Output(new Bundle {
val f1 = new BranchPredictionBundle
val f2 = new BranchPredictionBundle
val f3 = new BranchPredictionBundle
})
val f3_fire = Input(Bool())
// Update
val update = Input(Valid(new BranchPredictionUpdate))
})
var total_memsize = 0
val bpdStr = new StringBuilder
bpdStr.append(BoomCoreStringPrefix("==Branch Predictor Memory Sizes==\n"))
val banked_predictors = (0 until nBanks) map ( b => {
val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank)
for ((n, d, w) <- m.mems) {
bpdStr.append(BoomCoreStringPrefix(f"bank$b $n: $d x $w = ${d * w / 8}"))
total_memsize = total_memsize + d * w / 8
}
m
})
bpdStr.append(BoomCoreStringPrefix(f"Total bpd size: ${total_memsize / 1024} KB\n"))
override def toString: String = bpdStr.toString
val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) }
if (nBanks == 1) {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid
banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid
banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist
banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
} else {
require(nBanks == 2)
banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)
banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist
banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist
when (bank(io.f0_req.bits.pc) === 0.U) {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid
banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_lhist_providers(1).io.f0_valid := io.f0_req.valid
banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid
banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)
banked_predictors(1).io.f0_valid := io.f0_req.valid
banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W))
} .otherwise {
banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)
banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_lhist_providers(1).io.f0_valid := io.f0_req.valid
banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)
banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc)
banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W))
banked_predictors(1).io.f0_valid := io.f0_req.valid
banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)
banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc)
}
when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) {
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))
} .otherwise {
banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))
banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))
}
}
for (i <- 0 until nBanks) {
banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p =>
p.is_br && p.predicted_pc.valid && p.taken
).reduce(_||_)
}
if (nBanks == 1) {
io.resp.f1.preds := banked_predictors(0).io.resp.f1
io.resp.f2.preds := banked_predictors(0).io.resp.f2
io.resp.f3.preds := banked_predictors(0).io.resp.f3
io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta
io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist
banked_predictors(0).io.f3_fire := io.f3_fire
banked_lhist_providers(0).io.f3_fire := io.f3_fire
} else {
require(nBanks == 2)
val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid)))
val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid)))
banked_predictors(0).io.f3_fire := b0_fire
banked_predictors(1).io.f3_fire := b1_fire
banked_lhist_providers(0).io.f3_fire := b0_fire
banked_lhist_providers(1).io.f3_fire := b1_fire
// The branch prediction metadata is stored un-shuffled
io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta
io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta
io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist
io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist
when (bank(io.resp.f1.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i)
io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i)
io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i)
}
}
when (bank(io.resp.f2.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i)
io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i)
io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i)
}
}
when (bank(io.resp.f3.pc) === 0.U) {
for (i <- 0 until bankWidth) {
io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i)
io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i)
}
} .otherwise {
for (i <- 0 until bankWidth) {
io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i)
io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i)
}
}
}
io.resp.f1.pc := RegNext(io.f0_req.bits.pc)
io.resp.f2.pc := RegNext(io.resp.f1.pc)
io.resp.f3.pc := RegNext(io.resp.f2.pc)
// We don't care about meta from the f1 and f2 resps
// Use the meta from the latest resp
io.resp.f1.meta := DontCare
io.resp.f2.meta := DontCare
io.resp.f1.lhist := DontCare
io.resp.f2.lhist := DontCare
for (i <- 0 until nBanks) {
banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update
banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update
banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i)
banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i)
banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits
banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken
banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted
banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br
banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal
banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr
banked_predictors(i).io.update.bits.target := io.update.bits.target
banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update
banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update
banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i)
}
if (nBanks == 1) {
banked_predictors(0).io.update.valid := io.update.valid
banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U
banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)
} else {
require(nBanks == 2)
// Split the single update bundle for the fetchpacket into two updates
// 1 for each bank.
when (bank(io.update.bits.pc) === 0.U) {
val b1_update_valid = io.update.valid &&
(!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)
banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U
banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U
banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)
banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc)
banked_predictors(0).io.update.valid := io.update.valid
banked_predictors(1).io.update.valid := b1_update_valid
banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc)
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U
banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1)
} .otherwise {
val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) &&
(!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)
banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U
banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U
banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc)
banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc)
banked_predictors(1).io.update.valid := io.update.valid
banked_predictors(0).io.update.valid := b0_update_valid
banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc)
banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc)
banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask
banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth
banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts
banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth
banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U
banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U
banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0)
banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1)
}
}
when (io.update.valid) {
when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) {
assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))
}
}
}
class NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) {
val mems = Nil
}
File config-mixins.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util.{log2Up}
import org.chipsalliance.cde.config.{Parameters, Config, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMParams}
import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing}
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import boom.v3.ifu._
import boom.v3.exu._
import boom.v3.lsu._
// ---------------------
// BOOM Config Fragments
// ---------------------
class WithBoomCommitLogPrintf extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
enableCommitLogPrintf = true
)))
case other => other
}
})
class WithBoomBranchPrintf extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
enableBranchPrintf = true
)))
case other => other
}
})
class WithNBoomPerfCounters(n: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
nPerfCounters = n
)))
case other => other
}
})
class WithSynchronousBoomTiles extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
crossingType = SynchronousCrossing()
))
case other => other
}
})
class WithAsynchronousBoomTiles extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
crossingType = AsynchronousCrossing()
))
case other => other
}
})
class WithRationalBoomTiles extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
crossingType = RationalCrossing()
))
case other => other
}
})
/**
* 1-wide BOOM.
*/
class WithNSmallBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 4,
decodeWidth = 1,
numRobEntries = 32,
issueParams = Seq(
IssueParams(issueWidth=1, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=1),
IssueParams(issueWidth=1, numEntries=8, iqType=IQT_INT.litValue, dispatchWidth=1),
IssueParams(issueWidth=1, numEntries=8, iqType=IQT_FP.litValue , dispatchWidth=1)),
numIntPhysRegisters = 52,
numFpPhysRegisters = 48,
numLdqEntries = 8,
numStqEntries = 8,
maxBrCount = 8,
numFetchBufferEntries = 8,
ftq = FtqParameters(nEntries=16),
nPerfCounters = 2,
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
),
icache = Some(
ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4)
),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
/**
* 2-wide BOOM.
*/
class WithNMediumBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 4,
decodeWidth = 2,
numRobEntries = 64,
issueParams = Seq(
IssueParams(issueWidth=1, numEntries=12, iqType=IQT_MEM.litValue, dispatchWidth=2),
IssueParams(issueWidth=2, numEntries=20, iqType=IQT_INT.litValue, dispatchWidth=2),
IssueParams(issueWidth=1, numEntries=16, iqType=IQT_FP.litValue , dispatchWidth=2)),
numIntPhysRegisters = 80,
numFpPhysRegisters = 64,
numLdqEntries = 16,
numStqEntries = 16,
maxBrCount = 12,
numFetchBufferEntries = 16,
ftq = FtqParameters(nEntries=32),
nPerfCounters = 6,
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = 64, nSets=64, nWays=4, nMSHRs=2, nTLBWays=8)
),
icache = Some(
ICacheParams(rowBits = 64, nSets=64, nWays=4, fetchBytes=2*4)
),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
// DOC include start: LargeBoomConfig
/**
* 3-wide BOOM. Try to match the Cortex-A15.
*/
class WithNLargeBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 8,
decodeWidth = 3,
numRobEntries = 96,
issueParams = Seq(
IssueParams(issueWidth=1, numEntries=16, iqType=IQT_MEM.litValue, dispatchWidth=3),
IssueParams(issueWidth=3, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=3),
IssueParams(issueWidth=1, numEntries=24, iqType=IQT_FP.litValue , dispatchWidth=3)),
numIntPhysRegisters = 100,
numFpPhysRegisters = 96,
numLdqEntries = 24,
numStqEntries = 24,
maxBrCount = 16,
numFetchBufferEntries = 24,
ftq = FtqParameters(nEntries=32),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=4, nTLBWays=16)
),
icache = Some(
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
// DOC include end: LargeBoomConfig
/**
* 4-wide BOOM.
*/
class WithNMegaBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 8,
decodeWidth = 4,
numRobEntries = 128,
issueParams = Seq(
IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=4),
IssueParams(issueWidth=4, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=4),
IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=4)),
numIntPhysRegisters = 128,
numFpPhysRegisters = 128,
numLdqEntries = 32,
numStqEntries = 32,
maxBrCount = 20,
numFetchBufferEntries = 32,
enablePrefetching = true,
ftq = FtqParameters(nEntries=40),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
),
icache = Some(
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
/**
* 5-wide BOOM.
*/
class WithNGigaBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 8,
decodeWidth = 5,
numRobEntries = 130,
issueParams = Seq(
IssueParams(issueWidth=2, numEntries=24, iqType=IQT_MEM.litValue, dispatchWidth=5),
IssueParams(issueWidth=5, numEntries=40, iqType=IQT_INT.litValue, dispatchWidth=5),
IssueParams(issueWidth=2, numEntries=32, iqType=IQT_FP.litValue , dispatchWidth=5)),
numIntPhysRegisters = 128,
numFpPhysRegisters = 128,
numLdqEntries = 32,
numStqEntries = 32,
maxBrCount = 20,
numFetchBufferEntries = 35,
enablePrefetching = true,
numDCacheBanks = 1,
ftq = FtqParameters(nEntries=40),
fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))
),
dcache = Some(
DCacheParams(rowBits = 128, nSets=64, nWays=8, nMSHRs=8, nTLBWays=32)
),
icache = Some(
ICacheParams(rowBits = 128, nSets=64, nWays=8, fetchBytes=4*4)
),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
class WithCloneBoomTiles(
n: Int = 1,
cloneTileId: Int = 0,
location: HierarchicalLocation = InSubsystem,
cloneLocation: HierarchicalLocation = InSubsystem
) extends Config((site, here, up) => {
case TilesLocated(`location`) => {
val prev = up(TilesLocated(location), site)
val idOffset = up(NumTiles)
val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId)
.get.asInstanceOf[BoomTileAttachParams]
(0 until n).map { i =>
CloneTileAttachParams(cloneTileId, tileAttachParams.copy(
tileParams = tileAttachParams.tileParams.copy(tileId = i + idOffset)
))
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
/**
* BOOM Configs for CS152 lab
*/
class WithNCS152BaselineBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
val coreWidth = 1 // CS152: Change me (1 to 4)
val memWidth = 1 // CS152: Change me (1 or 2)
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 4, // CS152: Change me (4 or 8)
numRobEntries = 4, // CS152: Change me (2+)
numIntPhysRegisters = 33, // CS152: Change me (33+)
numLdqEntries = 8, // CS152: Change me (2+)
numStqEntries = 8, // CS152: Change me (2+)
maxBrCount = 8, // CS152: Change me (2+)
enableBranchPrediction = false, // CS152: Change me
numRasEntries = 0, // CS152: Change me
// DO NOT CHANGE BELOW
enableBranchPrintf = true,
decodeWidth = coreWidth,
numFetchBufferEntries = coreWidth * 8,
numDCacheBanks = memWidth,
issueParams = Seq(
IssueParams(issueWidth=memWidth, numEntries=8, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth),
IssueParams(issueWidth=coreWidth, numEntries=32, iqType=IQT_INT.litValue, dispatchWidth=coreWidth),
IssueParams(issueWidth=1, numEntries=4, iqType=IQT_FP.litValue , dispatchWidth=coreWidth))
// DO NOT CHANGE ABOVE
),
dcache = Some(DCacheParams(
rowBits=64,
nSets=64, // CS152: Change me (must be pow2, 2-64)
nWays=4, // CS152: Change me (1-8)
nMSHRs=2 // CS152: Change me (1+)
)),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
class WithNCS152DefaultBooms(n: Int = 1) extends Config(
new WithTAGELBPD ++ // Default to TAGE-L BPD
new Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
(0 until n).map { i =>
val coreWidth = 3 // CS152: Change me (1 to 4)
val memWidth = 1 // CS152: Change me (1 or 2)
val nIssueSlots = 32 // CS152: Change me (2+)
BoomTileAttachParams(
tileParams = BoomTileParams(
core = BoomCoreParams(
fetchWidth = 4, // CS152: Change me (4 or 8)
numRobEntries = 96, // CS152: Change me (2+)
numIntPhysRegisters = 96, // CS152: Change me (33+)
numLdqEntries = 16, // CS152: Change me (2+)
numStqEntries = 16, // CS152: Change me (2+)
maxBrCount = 12, // CS152: Change me (2+)
enableBranchPrediction = true, // CS152: Change me
numRasEntries = 16, // CS152: Change me
// DO NOT CHANGE BELOW
enableBranchPrintf = true,
decodeWidth = coreWidth,
numFetchBufferEntries = coreWidth * 8,
numDCacheBanks = memWidth,
issueParams = Seq(
IssueParams(issueWidth=memWidth, numEntries=nIssueSlots, iqType=IQT_MEM.litValue, dispatchWidth=coreWidth),
IssueParams(issueWidth=coreWidth, numEntries=nIssueSlots, iqType=IQT_INT.litValue, dispatchWidth=coreWidth),
IssueParams(issueWidth=1, numEntries=nIssueSlots, iqType=IQT_FP.litValue , dispatchWidth=coreWidth))
// DO NOT CHANGE ABOVE
),
dcache = Some(DCacheParams(
rowBits=64,
nSets=64, // CS152: Change me (must be pow2, 2-64)
nWays=4, // CS152: Change me (1-8)
nMSHRs=2 // CS152: Change me (1+)
)),
tileId = i + idOffset
),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
)
/**
* Branch prediction configs below
*/
class WithTAGELBPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 120,
globalHistoryLength = 64,
localHistoryLength = 1,
localHistoryNSets = 0,
branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => {
val loop = Module(new LoopBranchPredictorBank()(p))
val tage = Module(new TageBranchPredictorBank()(p))
val btb = Module(new BTBBranchPredictorBank()(p))
val bim = Module(new BIMBranchPredictorBank()(p))
val ubtb = Module(new FAMicroBTBBranchPredictorBank()(p))
val preds = Seq(loop, tage, btb, ubtb, bim)
preds.map(_.io := DontCare)
ubtb.io.resp_in(0) := resp_in
bim.io.resp_in(0) := ubtb.io.resp
btb.io.resp_in(0) := bim.io.resp
tage.io.resp_in(0) := btb.io.resp
loop.io.resp_in(0) := tage.io.resp
(preds, loop.io.resp)
})
)))
case other => other
}
})
class WithBoom2BPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 45,
globalHistoryLength = 16,
localHistoryLength = 1,
localHistoryNSets = 0,
branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => {
// gshare is just variant of TAGE with 1 table
val gshare = Module(new TageBranchPredictorBank(
BoomTageParams(tableInfo = Seq((256, 16, 7)))
)(p))
val btb = Module(new BTBBranchPredictorBank()(p))
val bim = Module(new BIMBranchPredictorBank()(p))
val preds = Seq(bim, btb, gshare)
preds.map(_.io := DontCare)
bim.io.resp_in(0) := resp_in
btb.io.resp_in(0) := bim.io.resp
gshare.io.resp_in(0) := btb.io.resp
(preds, gshare.io.resp)
})
)))
case other => other
}
})
class WithAlpha21264BPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 64,
globalHistoryLength = 32,
localHistoryLength = 32,
localHistoryNSets = 128,
branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => {
val btb = Module(new BTBBranchPredictorBank()(p))
val gbim = Module(new HBIMBranchPredictorBank()(p))
val lbim = Module(new HBIMBranchPredictorBank(BoomHBIMParams(useLocal=true))(p))
val tourney = Module(new TourneyBranchPredictorBank()(p))
val preds = Seq(lbim, btb, gbim, tourney)
preds.map(_.io := DontCare)
gbim.io.resp_in(0) := resp_in
lbim.io.resp_in(0) := resp_in
tourney.io.resp_in(0) := gbim.io.resp
tourney.io.resp_in(1) := lbim.io.resp
btb.io.resp_in(0) := tourney.io.resp
(preds, btb.io.resp)
})
)))
case other => other
}
})
class WithSWBPD extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(core = tp.tileParams.core.copy(
bpdMaxMetaLength = 1,
globalHistoryLength = 32,
localHistoryLength = 1,
localHistoryNSets = 0,
branchPredictor = ((resp_in: BranchPredictionBankResponse, p: Parameters) => {
val sw = Module(new SwBranchPredictorBank()(p))
sw.io.resp_in(0) := resp_in
(Seq(sw), sw.io.resp)
})
)))
case other => other
}
})
| module ComposedBranchPredictorBank_1( // @[composer.scala:14:7]
input clock, // @[composer.scala:14:7]
input reset, // @[composer.scala:14:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:449:26]
wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:449:26]
wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:449:26]
wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:449:26]
wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:448:25]
wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:448:25]
wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:448:25]
wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:448:25]
wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:447:25]
wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:447:25]
wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:447:25]
wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:447:25]
wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:446:26]
wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:446:26]
wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:446:26]
wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:446:26]
wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:445:26]
wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7]
wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7]
wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
wire [119:0] io_f3_meta_0; // @[composer.scala:14:7]
wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35]
reg [36:0] s1_idx; // @[predictor.scala:163:29]
reg [36:0] s2_idx; // @[predictor.scala:164:29]
reg [36:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [36:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
assign io_f3_meta_0 = {7'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[7:0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14]
always @(posedge clock) begin // @[composer.scala:14:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
always @(posedge)
LoopBranchPredictorBank_1 loop ( // @[config-mixins.scala:445:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:446:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:446:26]
.io_resp_f1_0_taken (io_resp_f1_0_taken_0),
.io_resp_f1_0_is_br (io_resp_f1_0_is_br_0),
.io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0),
.io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0),
.io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0),
.io_resp_f1_1_taken (io_resp_f1_1_taken_0),
.io_resp_f1_1_is_br (io_resp_f1_1_is_br_0),
.io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0),
.io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0),
.io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0),
.io_resp_f1_2_taken (io_resp_f1_2_taken_0),
.io_resp_f1_2_is_br (io_resp_f1_2_is_br_0),
.io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0),
.io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0),
.io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0),
.io_resp_f1_3_taken (io_resp_f1_3_taken_0),
.io_resp_f1_3_is_br (io_resp_f1_3_is_br_0),
.io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0),
.io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0),
.io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0),
.io_resp_f2_0_taken (io_resp_f2_0_taken_0),
.io_resp_f2_0_is_br (io_resp_f2_0_is_br_0),
.io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0),
.io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0),
.io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0),
.io_resp_f2_1_taken (io_resp_f2_1_taken_0),
.io_resp_f2_1_is_br (io_resp_f2_1_is_br_0),
.io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0),
.io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0),
.io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0),
.io_resp_f2_2_taken (io_resp_f2_2_taken_0),
.io_resp_f2_2_is_br (io_resp_f2_2_is_br_0),
.io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0),
.io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0),
.io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0),
.io_resp_f2_3_taken (io_resp_f2_3_taken_0),
.io_resp_f2_3_is_br (io_resp_f2_3_is_br_0),
.io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0),
.io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0),
.io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0),
.io_resp_f3_0_taken (io_resp_f3_0_taken_0),
.io_resp_f3_0_is_br (io_resp_f3_0_is_br_0),
.io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0),
.io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0),
.io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0),
.io_resp_f3_1_taken (io_resp_f3_1_taken_0),
.io_resp_f3_1_is_br (io_resp_f3_1_is_br_0),
.io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0),
.io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0),
.io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0),
.io_resp_f3_2_taken (io_resp_f3_2_taken_0),
.io_resp_f3_2_is_br (io_resp_f3_2_is_br_0),
.io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0),
.io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0),
.io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0),
.io_resp_f3_3_taken (io_resp_f3_3_taken_0),
.io_resp_f3_3_is_br (io_resp_f3_3_is_br_0),
.io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0),
.io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0),
.io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0),
.io_f3_meta (_loop_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({73'h0, io_update_bits_meta_0[119:73]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:445:26]
TageBranchPredictorBank_1 tage ( // @[config-mixins.scala:446:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:447:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:447:25]
.io_resp_f1_0_taken (_tage_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_tage_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_tage_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_tage_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_tage_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_tage_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_tage_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_tage_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_tage_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_tage_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_tage_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_tage_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_tage_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({17'h0, io_update_bits_meta_0[119:17]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:446:26]
BTBBranchPredictorBank_1 btb ( // @[config-mixins.scala:447:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:448:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:448:25]
.io_resp_f1_0_taken (_btb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_btb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_btb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_btb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_btb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_btb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_btb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_btb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_btb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_btb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_btb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_btb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_btb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({16'h0, io_update_bits_meta_0[119:16]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:447:25]
BIMBranchPredictorBank_1 bim ( // @[config-mixins.scala:448:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:449:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:449:26]
.io_resp_f1_0_taken (_bim_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_bim_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_bim_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_bim_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_bim_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_bim_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_bim_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_bim_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_bim_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_bim_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_bim_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_bim_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_bim_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7]
); // @[config-mixins.scala:448:25]
FAMicroBTBBranchPredictorBank_1 ubtb ( // @[config-mixins.scala:449:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_ubtb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31]
); // @[config-mixins.scala:449:26]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_323( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_4( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1366 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1366; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1366; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1439 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1439; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1439; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1439; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1292 = _T_1366 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1292 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1292 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1292 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1292 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1292 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1338 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1338 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1307 = _T_1439 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1307 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1307 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1307 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1410 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1410 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1392 = _T_1439 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1392 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1392 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1392 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_EntryData_39( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_66( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_66 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_66 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_94 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_222( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_123( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module MulAddRecFNToRaw_preMul_e8_s24_20( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module MulAddRecFNToRaw_preMul_e8_s24_6( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25]
wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30]
wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68]
wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9]
wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23]
wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30]
wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File arbiter.scala:
//**************************************************************************
// Arbiter for Princeton Architectures
//--------------------------------------------------------------------------
//
// Arbitrates instruction and data accesses to a single port memory.
package sodor.stage3
import chisel3._
import chisel3.util._
import sodor.common._
// arbitrates memory access
class SodorMemArbiter(implicit val conf: SodorCoreParams) extends Module
{
val io = IO(new Bundle
{
// TODO I need to come up with better names... this is too confusing
// from the point of view of the other modules
val imem = Flipped(new MemPortIo(conf.xprlen)) // instruction fetch
val dmem = Flipped(new MemPortIo(conf.xprlen)) // load/store
val mem = new MemPortIo(conf.xprlen) // the single-ported memory
})
val d_resp = RegInit(false.B)
// hook up requests
// d_resp ensures that data req gets access to bus only
// for one cycle
// alternate between data and instr to avoid starvation
when (d_resp)
{
// Last request is a data request - do not allow data request this cycle
io.dmem.req.ready := false.B
io.imem.req.ready := io.mem.req.ready
// We only clear the d_resp flag when the next request fired since it also indicates the allowed type of the next request
when (io.mem.req.fire)
{
d_resp := false.B
}
}
.otherwise
{
// Last request is not a data request - if this cycle has a new data request, dispatch it
io.dmem.req.ready := io.mem.req.ready
io.imem.req.ready := io.mem.req.ready && !io.dmem.req.valid
when (io.dmem.req.fire)
{
d_resp := true.B
}
}
// SWITCH BET DATA AND INST REQ FOR SINGLE PORT
when (io.dmem.req.fire)
{
io.mem.req.valid := io.dmem.req.valid
io.mem.req.bits.addr := io.dmem.req.bits.addr
io.mem.req.bits.fcn := io.dmem.req.bits.fcn
io.mem.req.bits.typ := io.dmem.req.bits.typ
}
.otherwise
{
io.mem.req.valid := io.imem.req.valid
io.mem.req.bits.addr := io.imem.req.bits.addr
io.mem.req.bits.fcn := io.imem.req.bits.fcn
io.mem.req.bits.typ := io.imem.req.bits.typ
}
// Control valid signal
when (d_resp)
{
io.imem.resp.valid := false.B
io.dmem.resp.valid := io.mem.resp.valid
}
.otherwise {
io.imem.resp.valid := io.mem.resp.valid
io.dmem.resp.valid := false.B
}
// No need to switch data since instruction port doesn't write
io.mem.req.bits.data := io.dmem.req.bits.data
// Simply connect response data to both ports since we only have one inflight request
// the validity of the data is controlled above
io.imem.resp.bits.data := io.mem.resp.bits.data
io.dmem.resp.bits.data := io.mem.resp.bits.data
}
| module SodorMemArbiter_1( // @[arbiter.scala:15:7]
input clock, // @[arbiter.scala:15:7]
input reset, // @[arbiter.scala:15:7]
output io_imem_req_ready, // @[arbiter.scala:17:14]
input io_imem_req_valid, // @[arbiter.scala:17:14]
input [31:0] io_imem_req_bits_addr, // @[arbiter.scala:17:14]
output io_imem_resp_valid, // @[arbiter.scala:17:14]
output [31:0] io_imem_resp_bits_data, // @[arbiter.scala:17:14]
output io_dmem_req_ready, // @[arbiter.scala:17:14]
input io_dmem_req_valid, // @[arbiter.scala:17:14]
input [31:0] io_dmem_req_bits_addr, // @[arbiter.scala:17:14]
input [31:0] io_dmem_req_bits_data, // @[arbiter.scala:17:14]
input io_dmem_req_bits_fcn, // @[arbiter.scala:17:14]
input [2:0] io_dmem_req_bits_typ, // @[arbiter.scala:17:14]
output io_dmem_resp_valid, // @[arbiter.scala:17:14]
output [31:0] io_dmem_resp_bits_data, // @[arbiter.scala:17:14]
input io_mem_req_ready, // @[arbiter.scala:17:14]
output io_mem_req_valid, // @[arbiter.scala:17:14]
output [31:0] io_mem_req_bits_addr, // @[arbiter.scala:17:14]
output [31:0] io_mem_req_bits_data, // @[arbiter.scala:17:14]
output io_mem_req_bits_fcn, // @[arbiter.scala:17:14]
output [2:0] io_mem_req_bits_typ, // @[arbiter.scala:17:14]
input io_mem_resp_valid, // @[arbiter.scala:17:14]
input [31:0] io_mem_resp_bits_data // @[arbiter.scala:17:14]
);
wire io_imem_req_valid_0 = io_imem_req_valid; // @[arbiter.scala:15:7]
wire [31:0] io_imem_req_bits_addr_0 = io_imem_req_bits_addr; // @[arbiter.scala:15:7]
wire io_dmem_req_valid_0 = io_dmem_req_valid; // @[arbiter.scala:15:7]
wire [31:0] io_dmem_req_bits_addr_0 = io_dmem_req_bits_addr; // @[arbiter.scala:15:7]
wire [31:0] io_dmem_req_bits_data_0 = io_dmem_req_bits_data; // @[arbiter.scala:15:7]
wire io_dmem_req_bits_fcn_0 = io_dmem_req_bits_fcn; // @[arbiter.scala:15:7]
wire [2:0] io_dmem_req_bits_typ_0 = io_dmem_req_bits_typ; // @[arbiter.scala:15:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[arbiter.scala:15:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[arbiter.scala:15:7]
wire [31:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[arbiter.scala:15:7]
wire [2:0] io_imem_req_bits_typ = 3'h7; // @[arbiter.scala:15:7, :17:14]
wire io_imem_req_bits_fcn = 1'h0; // @[arbiter.scala:15:7]
wire [31:0] io_imem_req_bits_data = 32'h0; // @[arbiter.scala:15:7, :17:14]
wire [31:0] io_mem_req_bits_data_0 = io_dmem_req_bits_data_0; // @[arbiter.scala:15:7]
wire [31:0] io_imem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7]
wire [31:0] io_dmem_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[arbiter.scala:15:7]
wire io_imem_req_ready_0; // @[arbiter.scala:15:7]
wire io_imem_resp_valid_0; // @[arbiter.scala:15:7]
wire io_dmem_req_ready_0; // @[arbiter.scala:15:7]
wire io_dmem_resp_valid_0; // @[arbiter.scala:15:7]
wire [31:0] io_mem_req_bits_addr_0; // @[arbiter.scala:15:7]
wire io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7]
wire [2:0] io_mem_req_bits_typ_0; // @[arbiter.scala:15:7]
wire io_mem_req_valid_0; // @[arbiter.scala:15:7]
reg d_resp; // @[arbiter.scala:26:23]
assign io_dmem_req_ready_0 = ~d_resp & io_mem_req_ready_0; // @[arbiter.scala:15:7, :26:23, :33:3, :35:23, :47:23]
wire _io_imem_req_ready_T = ~io_dmem_req_valid_0; // @[arbiter.scala:15:7, :48:46]
wire _io_imem_req_ready_T_1 = io_mem_req_ready_0 & _io_imem_req_ready_T; // @[arbiter.scala:15:7, :48:{43,46}]
assign io_imem_req_ready_0 = d_resp ? io_mem_req_ready_0 : _io_imem_req_ready_T_1; // @[arbiter.scala:15:7, :26:23, :33:3, :36:23, :48:{23,43}]
wire _T_2 = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35]
assign io_mem_req_valid_0 = _T_2 ? io_dmem_req_valid_0 : io_imem_req_valid_0; // @[Decoupled.scala:51:35]
assign io_mem_req_bits_addr_0 = _T_2 ? io_dmem_req_bits_addr_0 : io_imem_req_bits_addr_0; // @[Decoupled.scala:51:35]
assign io_mem_req_bits_fcn_0 = _T_2 & io_dmem_req_bits_fcn_0; // @[Decoupled.scala:51:35]
assign io_mem_req_bits_typ_0 = _T_2 ? io_dmem_req_bits_typ_0 : 3'h7; // @[Decoupled.scala:51:35]
assign io_imem_resp_valid_0 = ~d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :33:3, :35:23, :47:23, :72:3, :73:24, :77:24]
assign io_dmem_resp_valid_0 = d_resp & io_mem_resp_valid_0; // @[arbiter.scala:15:7, :26:23, :72:3, :74:24, :78:24]
always @(posedge clock) begin // @[arbiter.scala:15:7]
if (reset) // @[arbiter.scala:15:7]
d_resp <= 1'h0; // @[arbiter.scala:26:23]
else if (d_resp) // @[arbiter.scala:26:23]
d_resp <= ~(io_mem_req_ready_0 & io_mem_req_valid_0) & d_resp; // @[Decoupled.scala:51:35]
else // @[arbiter.scala:26:23]
d_resp <= io_dmem_req_ready_0 & io_dmem_req_valid_0 | d_resp; // @[Decoupled.scala:51:35]
always @(posedge)
assign io_imem_req_ready = io_imem_req_ready_0; // @[arbiter.scala:15:7]
assign io_imem_resp_valid = io_imem_resp_valid_0; // @[arbiter.scala:15:7]
assign io_imem_resp_bits_data = io_imem_resp_bits_data_0; // @[arbiter.scala:15:7]
assign io_dmem_req_ready = io_dmem_req_ready_0; // @[arbiter.scala:15:7]
assign io_dmem_resp_valid = io_dmem_resp_valid_0; // @[arbiter.scala:15:7]
assign io_dmem_resp_bits_data = io_dmem_resp_bits_data_0; // @[arbiter.scala:15:7]
assign io_mem_req_valid = io_mem_req_valid_0; // @[arbiter.scala:15:7]
assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[arbiter.scala:15:7]
assign io_mem_req_bits_data = io_mem_req_bits_data_0; // @[arbiter.scala:15:7]
assign io_mem_req_bits_fcn = io_mem_req_bits_fcn_0; // @[arbiter.scala:15:7]
assign io_mem_req_bits_typ = io_mem_req_bits_typ_0; // @[arbiter.scala:15:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File AtomicAutomata.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.util.leftOR
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operations.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
val node = TLAdapterNode(
managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
m.v1copy(
supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical),
mayDenyGet = m.mayDenyGet || m.mayDenyPut)
})})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes
// To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, beatBytes)
val managersNeedingHelp = managers.filter { m =>
m.supportsPutFull.contains(ourSupport) &&
m.supportsGet.contains(ourSupport) &&
((logical && !m.supportsLogical .contains(ourSupport)) ||
(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
!passthrough) // we will do atomics for everyone we can
}
// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n"))
// We cannot add atomics to a non-FIFO manager
managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
// We need to preserve FIFO semantics across FIFO domains, not managers
// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
// Don't overprovision the CAM
val camSize = min(domainsNeedingHelp.size, concurrency)
// Compact the fifoIds to only those we care about
def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)
// CAM entry state machine
val FREE = 0.U // unused waiting on Atomic from A
val GET = 3.U // Get sent down A waiting on AccessDataAck from D
val AMO = 2.U // AccessDataAck sent up D waiting for A availability
val ACK = 1.U // Put sent down A waiting for PutAck from D
val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size)
// Do we need to do anything at all?
if (camSize > 0) {
val initval = Wire(new TLAtomicAutomata.CAM_S(params))
initval.state := FREE
val cam_s = RegInit(VecInit.fill(camSize)(initval))
val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params)))
val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params)))
val cam_free = cam_s.map(_.state === FREE)
val cam_amo = cam_s.map(_.state === AMO)
val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries
// Can the manager already handle this message?
val a_address = edgeIn.address(in.a.bits)
val a_size = edgeIn.size(in.a.bits)
val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size)
val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size)
val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B))
// Must we do a Put?
val a_cam_any_put = cam_amo.reduce(_ || _)
val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init
val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
val a_cam_a = PriorityMux(cam_amo, cam_a)
val a_cam_d = PriorityMux(cam_amo, cam_d)
val a_a = a_cam_a.bits.data
val a_d = a_cam_d.data
// Does the A request conflict with an inflight AMO?
val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U)
val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
// (Where) are we are allocating in the CAM?
val a_cam_any_free = cam_free.reduce(_ || _)
val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init
val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
// Logical AMO
val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
// Arithmetic AMO
val unsigned = a_cam_a.bits.param(1)
val take_max = a_cam_a.bits.param(0)
val adder = a_cam_a.bits.param(2)
val mask = a_cam_a.bits.mask
val signSel = ~(~mask | (mask >> 1))
val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a
val a_d_ext = (a_d & wide_mask) | signext_d
val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
val adder_out = a_a_ext + a_d_inv
val h = 8*beatBytes-1 // now sign-extended; use biggest bit
val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
val pick_a = take_max === a_bigger
val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d))
// AMO result data
val amo_data =
if (!logical) arith_out else
if (!arithmetic) logic_out else
Mux(a_cam_a.bits.opcode(0), logic_out, arith_out)
// Potentially mutate the message from inner
val source_i = Wire(chiselTypeOf(in.a))
val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
in.a.ready := source_i.ready && a_allow
source_i.valid := in.a.valid && a_allow
source_i.bits := in.a.bits
when (!a_isSupported) { // minimal mux difference
source_i.bits.opcode := TLMessages.Get
source_i.bits.param := 0.U
}
// Potentially take the message from the CAM
val source_c = Wire(chiselTypeOf(in.a))
source_c.valid := a_cam_any_put
source_c.bits := edgeOut.Put(
fromSource = a_cam_a.bits.source,
toAddress = edgeIn.address(a_cam_a.bits),
lgSize = a_cam_a.bits.size,
data = amo_data,
corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2
source_c.bits.user :<= a_cam_a.bits.user
source_c.bits.echo :<= a_cam_a.bits.echo
// Finishing an AMO from the CAM has highest priority
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i))
// Capture the A state into the CAM
when (source_i.fire && !a_isSupported) {
(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
when (en) {
r.fifoId := a_fifoId
r.bits := in.a.bits
r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
TLAtomics.AND -> 0x8.U,
TLAtomics.OR -> 0xe.U,
TLAtomics.XOR -> 0x6.U,
TLAtomics.SWAP -> 0xc.U))
}
}
(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := GET
}
}
}
// Advance the put state
when (source_c.fire) {
(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := ACK
}
}
}
// We need to deal with a potential D response in the same cycle as the A request
val d_first = edgeOut.first(out.d)
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied))
val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
val d_ack = out.d.bits.opcode === TLMessages.AccessAck
when (out.d.fire && d_first) {
(d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) {
r.data := out.d.bits.data
r.denied := out.d.bits.denied
r.corrupt := out.d.bits.corrupt
}
}
(d_cam_sel zip cam_s) foreach { case (en, r) =>
when (en) {
// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
r.state := Mux(d_ackd, AMO, FREE)
}
}
}
val d_drop = d_first && d_ackd && d_cam_sel_any
val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _)
in.d.valid := out.d.valid && !d_drop
out.d.ready := in.d.ready || d_drop
in.d.bits := out.d.bits
when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data
in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied
in.d.bits.denied := d_cam_denied || out.d.bits.denied
}
} else {
out.a.valid := in.a.valid
in.a.ready := out.a.ready
out.a.bits := in.a.bits
in.d.valid := out.d.valid
out.d.ready := in.d.ready
in.d.bits := out.d.bits
}
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAtomicAutomata
{
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
})
atomics.node
}
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
class CAM_S(val params: CAMParams) extends Bundle {
val state = UInt(2.W)
}
class CAM_A(val params: CAMParams) extends Bundle {
val bits = new TLBundleA(params.a)
val fifoId = UInt(log2Up(params.domainsNeedingHelp).W)
val lut = UInt(4.W)
}
class CAM_D(val params: CAMParams) extends Bundle {
val data = UInt(params.a.dataBits.W)
val denied = Bool()
val corrupt = Bool()
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
| module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83]
wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60]
wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85]
wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canLogical_T_52 = 1'h0; // @[Parameters.scala:684:54]
wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canArithmetic_T_52 = 1'h0; // @[Parameters.scala:684:54]
wire _source_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _source_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [32:0] _a_fifoId_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_fifoId_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27]
wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [31:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9]
wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28]
wire [6:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28]
wire [31:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28]
wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28]
wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28]
wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [31:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17]
wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34]
reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
wire [6:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17]
reg [31:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [31:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [31:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44]
wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58]
wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82]
wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire cam_amo_0; // @[AtomicAutomata.scala:87:44]
assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44]
wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68]
assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68]
wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56]
wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80]
wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28]
wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49]
wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}]
wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96]
wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49]
wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire _a_canLogical_T_1; // @[Parameters.scala:92:38]
assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38]
assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29]
wire [31:0] _GEN_1 = {nodeIn_a_bits_address[31:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_4; // @[Parameters.scala:137:31]
assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46]
wire _a_canLogical_T_8 = _a_canLogical_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_2 = {nodeIn_a_bits_address[31:29], nodeIn_a_bits_address[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_9; // @[Parameters.scala:137:31]
assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46]
wire _a_canLogical_T_13 = _a_canLogical_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13; // @[Parameters.scala:685:42]
wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canLogical_T_53 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26]
wire [32:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46]
wire _a_canLogical_T_21 = _a_canLogical_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_3 = {nodeIn_a_bits_address[31:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_22; // @[Parameters.scala:137:31]
assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46]
wire _a_canLogical_T_26 = _a_canLogical_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_4 = {nodeIn_a_bits_address[31:21], nodeIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_27; // @[Parameters.scala:137:31]
assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 33'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46]
wire _a_canLogical_T_31 = _a_canLogical_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_5 = {nodeIn_a_bits_address[31:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_32; // @[Parameters.scala:137:31]
assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46]
wire _a_canLogical_T_36 = _a_canLogical_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_6 = {nodeIn_a_bits_address[31:28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_37; // @[Parameters.scala:137:31]
assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46]
wire _a_canLogical_T_41 = _a_canLogical_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_7 = nodeIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [31:0] _a_canLogical_T_42; // @[Parameters.scala:137:31]
assign _a_canLogical_T_42 = _GEN_7; // @[Parameters.scala:137:31]
wire [31:0] _a_canArithmetic_T_42; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_42 = _GEN_7; // @[Parameters.scala:137:31]
wire [32:0] _a_canLogical_T_43 = {1'h0, _a_canLogical_T_42}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canLogical_T_44 = _a_canLogical_T_43 & 33'h9A100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canLogical_T_45 = _a_canLogical_T_44; // @[Parameters.scala:137:46]
wire _a_canLogical_T_46 = _a_canLogical_T_45 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_47 = _a_canLogical_T_21 | _a_canLogical_T_26; // @[Parameters.scala:685:42]
wire _a_canLogical_T_48 = _a_canLogical_T_47 | _a_canLogical_T_31; // @[Parameters.scala:685:42]
wire _a_canLogical_T_49 = _a_canLogical_T_48 | _a_canLogical_T_36; // @[Parameters.scala:685:42]
wire _a_canLogical_T_50 = _a_canLogical_T_49 | _a_canLogical_T_41; // @[Parameters.scala:685:42]
wire _a_canLogical_T_51 = _a_canLogical_T_50 | _a_canLogical_T_46; // @[Parameters.scala:685:42]
wire _a_canLogical_T_54 = _a_canLogical_T_53; // @[Parameters.scala:686:26]
wire a_canLogical = _a_canLogical_T_54; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29]
wire [32:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canArithmetic_T_53 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26]
wire [32:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 33'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 33'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _a_canArithmetic_T_43 = {1'h0, _a_canArithmetic_T_42}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_canArithmetic_T_44 = _a_canArithmetic_T_43 & 33'h9A100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_canArithmetic_T_45 = _a_canArithmetic_T_44; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_46 = _a_canArithmetic_T_45 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_47 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47 | _a_canArithmetic_T_31; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_49 = _a_canArithmetic_T_48 | _a_canArithmetic_T_36; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_50 = _a_canArithmetic_T_49 | _a_canArithmetic_T_41; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_51 = _a_canArithmetic_T_50 | _a_canArithmetic_T_46; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_54 = _a_canArithmetic_T_53; // @[Parameters.scala:686:26]
wire a_canArithmetic = _a_canArithmetic_T_54; // @[Parameters.scala:686:26]
wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47]
wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47]
wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63]
wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]
wire [32:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}]
wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57]
wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28]
wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42]
wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42]
wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39]
wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25]
wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39]
wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}]
wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}]
wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29]
wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29]
wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38]
wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}]
wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}]
wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38]
wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}]
wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}]
wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17]
wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17]
wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17]
wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17]
wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17]
wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17]
wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17]
wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17]
wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40]
wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40]
wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17]
wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17]
wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17]
wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17]
wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17]
wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17]
wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17]
wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17]
wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40]
wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40]
wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40]
wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28]
wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}]
wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28]
wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}]
wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43]
wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]
wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33]
wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33]
wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49]
wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35]
wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}]
wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50]
wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}]
wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65]
wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}]
wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}]
wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31]
wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]
wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]
wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34]
wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]
wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17]
wire _source_i_ready_T; // @[Arbiter.scala:94:31]
wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38]
wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28]
wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28]
wire source_i_ready; // @[AtomicAutomata.scala:154:28]
wire source_i_valid; // @[AtomicAutomata.scala:154:28]
wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23]
wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53]
wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}]
assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38]
assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]
assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]
wire _source_c_ready_T; // @[Arbiter.scala:94:31]
wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17]
wire source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28]
wire [6:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28]
wire [31:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28]
wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28]
wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28]
wire source_c_ready; // @[AtomicAutomata.scala:165:28]
wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45]
assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17]
wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [31:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[31:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 33'h8A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _source_c_bits_legal_T_51 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [32:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 33'h8A112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[31:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 33'h8A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[31:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 33'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[31:28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 33'h88000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _source_c_bits_legal_T_34 = cam_a_0_bits_address ^ 32'h80000000; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 33'h8A100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_39 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_40 = _source_c_bits_legal_T_39 | _source_c_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 | _source_c_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41 | _source_c_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_42; // @[Parameters.scala:684:{29,54}, :685:42]
wire [31:0] _source_c_bits_legal_T_45 = {cam_a_0_bits_address[31:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24]
wire [32:0] _source_c_bits_legal_T_46 = {1'h0, _source_c_bits_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 & 33'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_52 = _source_c_bits_legal_T_51 | _source_c_bits_legal_T_43; // @[Parameters.scala:684:54, :686:26]
wire source_c_bits_legal = _source_c_bits_legal_T_52; // @[Parameters.scala:686:26]
assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17]
assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17]
assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17]
assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17]
assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46]
wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28] |
Generate the Verilog code corresponding to the following Chisel files.
File SyncMem.scala:
package gemmini
import chisel3._
import chisel3.util._
class SinglePortedSyncMemIO[T <: Data](n: Int, t: T) extends Bundle {
val addr = Input(UInt((log2Ceil(n) max 1).W))
val wdata = Input(t)
val rdata = Output(t)
val wen = Input(Bool())
val ren = Input(Bool())
}
class SinglePortSyncMem[T <: Data](n: Int, t: T) extends Module {
val io = IO(new SinglePortedSyncMemIO(n, t))
assert(!(io.ren && io.wen), "undefined behavior in single-ported SRAM")
val mem = SyncReadMem(n, t)
when (io.wen) {
mem.write(io.addr, io.wdata)
io.rdata := DontCare
}.otherwise {
io.rdata := mem.read(io.addr, io.ren)
}
}
class TwoPortSyncMem[T <: Data](n: Int, t: T, mask_len: Int) extends Module {
val io = IO(new Bundle {
val waddr = Input(UInt((log2Ceil(n) max 1).W))
val raddr = Input(UInt((log2Ceil(n) max 1).W))
val wdata = Input(t)
val rdata = Output(t)
val wen = Input(Bool())
val ren = Input(Bool())
val mask = Input(Vec(mask_len, Bool()))
})
assert(!(io.wen && io.ren && io.raddr === io.waddr), "undefined behavior in dual-ported SRAM")
// val mem = SyncReadMem(n, t)
val mask_elem = UInt((t.getWidth / mask_len).W)
val mem = SyncReadMem(n, Vec(mask_len, mask_elem))
io.rdata := mem.read(io.raddr, io.ren).asTypeOf(t)
when (io.wen) {
mem.write(io.waddr, io.wdata.asTypeOf(Vec(mask_len, mask_elem)), io.mask)
}
}
class SplitSinglePortSyncMem[T <: Data](n: Int, t: T, splits: Int) extends Module {
val io = IO(new Bundle {
val waddr = Input(UInt((log2Ceil(n) max 1).W))
val raddr = Input(UInt((log2Ceil(n) max 1).W))
val wdata = Input(t)
val rdata = Output(t)
val wen = Input(Bool())
val ren = Input(Bool())
})
val lens = n / splits
val last_len = n - (splits-1)*lens
def is_in_range(addr: UInt, i: Int) = {
if (i == splits-1)
addr >= (i*lens).U
else
addr >= (i*lens).U && addr < ((i+1)*lens).U
}
def split_addr(addr: UInt, i: Int) = {
addr - (i*lens).U
}
val srams = Seq.fill(splits-1)(SinglePortSyncMem(lens, t).io) :+ SinglePortSyncMem(last_len, t).io
val output_split = Reg(UInt((log2Ceil(splits) max 1).W))
io.rdata := DontCare
srams.zipWithIndex.foreach { case (sr, i) =>
sr.addr := Mux(sr.ren, split_addr(io.raddr, i), split_addr(io.waddr, i))
sr.wdata := io.wdata
sr.ren := io.ren && is_in_range(io.raddr, i)
sr.wen := io.wen && is_in_range(io.waddr, i)
when (sr.ren) {
output_split := i.U
}
// This is an awkward Chisel Vec error workaround
when (output_split === i.U) {
io.rdata := sr.rdata
}
}
}
object SinglePortSyncMem {
def apply[T <: Data](n: Int, t: T): SinglePortSyncMem[T] = Module(new SinglePortSyncMem(n, t))
}
object TwoPortSyncMem {
def apply[T <: Data](n: Int, t: T, mask_len: Int): TwoPortSyncMem[T] = Module(new TwoPortSyncMem(n, t, mask_len))
}
object SplitSinglePortSyncMem {
def apply[T <: Data](n: Int, t: T, splits: Int): SplitSinglePortSyncMem[T] = Module(new SplitSinglePortSyncMem(n, t, splits))
}
| module TwoPortSyncMem( // @[SyncMem.scala:30:7]
input clock, // @[SyncMem.scala:30:7]
input reset, // @[SyncMem.scala:30:7]
input [11:0] io_waddr, // @[SyncMem.scala:31:14]
input [11:0] io_raddr, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_0_0_bits, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_1_0_bits, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_2_0_bits, // @[SyncMem.scala:31:14]
input [31:0] io_wdata_3_0_bits, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_0_0_bits, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_1_0_bits, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_2_0_bits, // @[SyncMem.scala:31:14]
output [31:0] io_rdata_3_0_bits, // @[SyncMem.scala:31:14]
input io_wen, // @[SyncMem.scala:31:14]
input io_ren, // @[SyncMem.scala:31:14]
input io_mask_0, // @[SyncMem.scala:31:14]
input io_mask_1, // @[SyncMem.scala:31:14]
input io_mask_2, // @[SyncMem.scala:31:14]
input io_mask_3, // @[SyncMem.scala:31:14]
input io_mask_4, // @[SyncMem.scala:31:14]
input io_mask_5, // @[SyncMem.scala:31:14]
input io_mask_6, // @[SyncMem.scala:31:14]
input io_mask_7, // @[SyncMem.scala:31:14]
input io_mask_8, // @[SyncMem.scala:31:14]
input io_mask_9, // @[SyncMem.scala:31:14]
input io_mask_10, // @[SyncMem.scala:31:14]
input io_mask_11, // @[SyncMem.scala:31:14]
input io_mask_12, // @[SyncMem.scala:31:14]
input io_mask_13, // @[SyncMem.scala:31:14]
input io_mask_14, // @[SyncMem.scala:31:14]
input io_mask_15 // @[SyncMem.scala:31:14]
);
wire [127:0] _mem_R0_data; // @[SyncMem.scala:45:24]
wire [11:0] io_waddr_0 = io_waddr; // @[SyncMem.scala:30:7]
wire [11:0] io_raddr_0 = io_raddr; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_0_0_bits_0 = io_wdata_0_0_bits; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_1_0_bits_0 = io_wdata_1_0_bits; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_2_0_bits_0 = io_wdata_2_0_bits; // @[SyncMem.scala:30:7]
wire [31:0] io_wdata_3_0_bits_0 = io_wdata_3_0_bits; // @[SyncMem.scala:30:7]
wire io_wen_0 = io_wen; // @[SyncMem.scala:30:7]
wire io_ren_0 = io_ren; // @[SyncMem.scala:30:7]
wire io_mask_0_0 = io_mask_0; // @[SyncMem.scala:30:7]
wire io_mask_1_0 = io_mask_1; // @[SyncMem.scala:30:7]
wire io_mask_2_0 = io_mask_2; // @[SyncMem.scala:30:7]
wire io_mask_3_0 = io_mask_3; // @[SyncMem.scala:30:7]
wire io_mask_4_0 = io_mask_4; // @[SyncMem.scala:30:7]
wire io_mask_5_0 = io_mask_5; // @[SyncMem.scala:30:7]
wire io_mask_6_0 = io_mask_6; // @[SyncMem.scala:30:7]
wire io_mask_7_0 = io_mask_7; // @[SyncMem.scala:30:7]
wire io_mask_8_0 = io_mask_8; // @[SyncMem.scala:30:7]
wire io_mask_9_0 = io_mask_9; // @[SyncMem.scala:30:7]
wire io_mask_10_0 = io_mask_10; // @[SyncMem.scala:30:7]
wire io_mask_11_0 = io_mask_11; // @[SyncMem.scala:30:7]
wire io_mask_12_0 = io_mask_12; // @[SyncMem.scala:30:7]
wire io_mask_13_0 = io_mask_13; // @[SyncMem.scala:30:7]
wire io_mask_14_0 = io_mask_14; // @[SyncMem.scala:30:7]
wire io_mask_15_0 = io_mask_15; // @[SyncMem.scala:30:7]
wire [11:0] _io_rdata_WIRE = io_raddr_0; // @[SyncMem.scala:30:7, :47:23]
wire [31:0] _io_rdata_WIRE_1_0_0_bits; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_1_0_bits; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_2_0_bits; // @[SyncMem.scala:47:50]
wire [31:0] _io_rdata_WIRE_1_3_0_bits; // @[SyncMem.scala:47:50]
wire [31:0] io_rdata_0_0_bits_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_1_0_bits_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_2_0_bits_0; // @[SyncMem.scala:30:7]
wire [31:0] io_rdata_3_0_bits_0; // @[SyncMem.scala:30:7] |
Generate the Verilog code corresponding to the following Chisel files.
File rob.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Re-order Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Bank the ROB, such that each "dispatch" group gets its own row of the ROB,
// and each instruction in the dispatch group goes to a different bank.
// We can compress out the PC by only saving the high-order bits!
//
// ASSUMPTIONS:
// - dispatch groups are aligned to the PC.
//
// NOTES:
// - Currently we do not compress out bubbles in the ROB.
// - Exceptions are only taken when at the head of the commit bundle --
// this helps deal with loads, stores, and refetch instructions.
package boom.v3.exu
import scala.math.ceil
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import boom.v3.common._
import boom.v3.util._
/**
* IO bundle to interact with the ROB
*
* @param numWakeupPorts number of wakeup ports to the rob
* @param numFpuPorts number of fpu ports that will write back fflags
*/
class RobIo(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomBundle
{
// Decode Stage
// (Allocate, write instruction to ROB).
val enq_valids = Input(Vec(coreWidth, Bool()))
val enq_uops = Input(Vec(coreWidth, new MicroOp()))
val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,
// and stalling on the rest of it (don't
// advance the tail ptr)
val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))
val rob_tail_idx = Output(UInt(robAddrSz.W))
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
// Handle Branch Misspeculations
val brupdate = Input(new BrUpdateInfo())
// Write-back Stage
// (Update of ROB)
// Instruction is no longer busy and can be committed
val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))
// Unbusying ports for stores.
// +1 for fpstdata
val lsu_clr_bsy = Input(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))
// Port for unmarking loads/stores as speculation hazards..
val lsu_clr_unsafe = Input(Vec(memWidth, Valid(UInt(robAddrSz.W))))
// Track side-effects for debug purposes.
// Also need to know when loads write back, whereas we don't need loads to unbusy.
val debug_wb_valids = Input(Vec(numWakeupPorts, Bool()))
val debug_wb_wdata = Input(Vec(numWakeupPorts, Bits(xLen.W)))
val fflags = Flipped(Vec(numFpuPorts, new ValidIO(new FFlagsResp())))
val lxcpt = Input(Valid(new Exception())) // LSU
val csr_replay = Input(Valid(new Exception()))
// Commit stage (free resources; also used for rollback).
val commit = Output(new CommitSignals())
// tell the LSU that the head of the ROB is a load
// (some loads can only execute once they are at the head of the ROB).
val com_load_is_at_rob_head = Output(Bool())
// Communicate exceptions to the CSRFile
val com_xcpt = Valid(new CommitExceptionSignals())
// Let the CSRFile stall us (e.g., wfi).
val csr_stall = Input(Bool())
// Flush signals (including exceptions, pipeline replays, and memory ordering failures)
// to send to the frontend for redirection.
val flush = Valid(new CommitExceptionSignals)
// Stall Decode as appropriate
val empty = Output(Bool())
val ready = Output(Bool()) // ROB is busy unrolling rename state...
// Stall the frontend if we know we will redirect the PC
val flush_frontend = Output(Bool())
val debug_tsc = Input(UInt(xLen.W))
}
/**
* Bundle to send commit signals across processor
*/
class CommitSignals(implicit p: Parameters) extends BoomBundle
{
val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn
val arch_valids = Vec(retireWidth, Bool())
val uops = Vec(retireWidth, new MicroOp())
val fflags = Valid(UInt(5.W))
// These come a cycle later
val debug_insts = Vec(retireWidth, UInt(32.W))
// Perform rollback of rename state (in conjuction with commit.uops).
val rbk_valids = Vec(retireWidth, Bool())
val rollback = Bool()
val debug_wdata = Vec(retireWidth, UInt(xLen.W))
}
/**
* Bundle to communicate exceptions to CSRFile
*
* TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).
*/
class CommitExceptionSignals(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val edge_inst = Bool()
val is_rvc = Bool()
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
val cause = UInt(xLen.W)
val badvaddr = UInt(xLen.W)
// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)
// so the FTQ can drive the frontend with the correct redirected PC.
val flush_typ = FlushTypes()
}
/**
* Tell the frontend the type of flush so it can set up the next PC properly.
*/
object FlushTypes
{
def SZ = 3
def apply() = UInt(SZ.W)
def none = 0.U
def xcpt = 1.U // An exception occurred.
def eret = (2+1).U // Execute an environment return instruction.
def refetch = 2.U // Flush and refetch the head instruction.
def next = 4.U // Flush and fetch the next instruction.
def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U
def useSamePC(typ: UInt): Bool = typ === refetch
def usePCplus4(typ: UInt): Bool = typ === next
def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {
val ret =
Mux(!valid, none,
Mux(i_eret, eret,
Mux(i_xcpt, xcpt,
Mux(i_refetch, refetch,
next))))
ret
}
}
/**
* Bundle of signals indicating that an exception occurred
*/
class Exception(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)
val badvaddr = UInt(coreMaxAddrBits.W)
}
/**
* Bundle for debug ROB signals
* These should not be synthesized!
*/
class DebugRobSignals(implicit p: Parameters) extends BoomBundle
{
val state = UInt()
val rob_head = UInt(robAddrSz.W)
val rob_pnr = UInt(robAddrSz.W)
val xcpt_val = Bool()
val xcpt_uop = new MicroOp()
val xcpt_badvaddr = UInt(xLen.W)
}
/**
* Reorder Buffer to keep track of dependencies and inflight instructions
*
* @param numWakeupPorts number of wakeup ports to the ROB
* @param numFpuPorts number of FPU units that will write back fflags
*/
class Rob(
val numWakeupPorts: Int,
val numFpuPorts: Int
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new RobIo(numWakeupPorts, numFpuPorts))
// ROB Finite State Machine
val s_reset :: s_normal :: s_rollback :: s_wait_till_empty :: Nil = Enum(4)
val rob_state = RegInit(s_reset)
//commit entries at the head, and unwind exceptions from the tail
val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)
val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)
val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)
val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)
val com_idx = Mux(rob_state === s_rollback, rob_tail, rob_head)
val maybe_full = RegInit(false.B)
val full = Wire(Bool())
val empty = Wire(Bool())
val will_commit = Wire(Vec(coreWidth, Bool()))
val can_commit = Wire(Vec(coreWidth, Bool()))
val can_throw_exception = Wire(Vec(coreWidth, Bool()))
val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?
val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?
val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)
val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))
val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))
val rob_head_fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
val exception_thrown = Wire(Bool())
// exception info
// TODO compress xcpt cause size. Most bits in the middle are zero.
val r_xcpt_val = RegInit(false.B)
val r_xcpt_uop = Reg(new MicroOp())
val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))
io.flush_frontend := r_xcpt_val
//--------------------------------------------------
// Utility
def GetRowIdx(rob_idx: UInt): UInt = {
if (coreWidth == 1) return rob_idx
else return rob_idx >> log2Ceil(coreWidth).U
}
def GetBankIdx(rob_idx: UInt): UInt = {
if(coreWidth == 1) { return 0.U }
else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }
}
// **************************************************************************
// Debug
class DebugRobBundle extends BoomBundle
{
val valid = Bool()
val busy = Bool()
val unsafe = Bool()
val uop = new MicroOp()
val exception = Bool()
}
val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))
debug_entry := DontCare // override in statements below
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.
val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))
// Used for trace port, for debug purposes only
val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))
val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))
val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))
rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)
val rob_debug_inst_rdata = rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))
val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
for (w <- 0 until coreWidth) {
def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)
// one bank
val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))
val rob_bsy = Reg(Vec(numRobRows, Bool()))
val rob_unsafe = Reg(Vec(numRobRows, Bool()))
val rob_uop = Reg(Vec(numRobRows, new MicroOp()))
val rob_exception = Reg(Vec(numRobRows, Bool()))
val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?
val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))
//-----------------------------------------------
// Dispatch: Add Entry to ROB
rob_debug_inst_wmask(w) := io.enq_valids(w)
rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst
when (io.enq_valids(w)) {
rob_val(rob_tail) := true.B
rob_bsy(rob_tail) := !(io.enq_uops(w).is_fence ||
io.enq_uops(w).is_fencei)
rob_unsafe(rob_tail) := io.enq_uops(w).unsafe
rob_uop(rob_tail) := io.enq_uops(w)
rob_exception(rob_tail) := io.enq_uops(w).exception
rob_predicated(rob_tail) := false.B
rob_fflags(w)(rob_tail) := 0.U
assert (rob_val(rob_tail) === false.B, "[rob] overwriting a valid entry.")
assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)
} .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {
rob_uop(rob_tail).debug_inst := BUBBLE // just for debug purposes
}
//-----------------------------------------------
// Writeback
for (i <- 0 until numWakeupPorts) {
val wb_resp = io.wb_resps(i)
val wb_uop = wb_resp.bits.uop
val row_idx = GetRowIdx(wb_uop.rob_idx)
when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {
rob_bsy(row_idx) := false.B
rob_unsafe(row_idx) := false.B
rob_predicated(row_idx) := wb_resp.bits.predicated
}
// TODO check that fflags aren't overwritten
// TODO check that the wb is to a valid ROB entry, give it a time stamp
// assert (!(wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx)) &&
// wb_uop.fp_val && !(wb_uop.is_load || wb_uop.is_store) &&
// rob_exc_cause(row_idx) =/= 0.U),
// "FP instruction writing back exc bits is overriding an existing exception.")
}
// Stores have a separate method to clear busy bits
for (clr_rob_idx <- io.lsu_clr_bsy) {
when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {
val cidx = GetRowIdx(clr_rob_idx.bits)
rob_bsy(cidx) := false.B
rob_unsafe(cidx) := false.B
assert (rob_val(cidx) === true.B, "[rob] store writing back to invalid entry.")
assert (rob_bsy(cidx) === true.B, "[rob] store writing back to a not-busy entry.")
}
}
for (clr <- io.lsu_clr_unsafe) {
when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {
val cidx = GetRowIdx(clr.bits)
rob_unsafe(cidx) := false.B
}
}
//-----------------------------------------------
// Accruing fflags
for (i <- 0 until numFpuPorts) {
val fflag_uop = io.fflags(i).bits.uop
when (io.fflags(i).valid && MatchBank(GetBankIdx(fflag_uop.rob_idx))) {
rob_fflags(w)(GetRowIdx(fflag_uop.rob_idx)) := io.fflags(i).bits.flags
}
}
//-----------------------------------------------------
// Exceptions
// (the cause bits are compressed and stored elsewhere)
when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B
when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {
// In the case of a mem-ordering failure, the failing load will have been marked safe already.
assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),
"An instruction marked as safe is causing an exception")
}
}
when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B
}
can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)
//-----------------------------------------------
// Commit or Rollback
// Can this instruction commit? (the check for exceptions/rob_state happens later).
can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall
// use the same "com_uop" for both rollback AND commit
// Perform Commit
io.commit.valids(w) := will_commit(w)
io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(com_idx)
io.commit.uops(w) := rob_uop(com_idx)
io.commit.debug_insts(w) := rob_debug_inst_rdata(w)
// We unbusy branches in b1, but its easier to mark the taken/provider src in b2,
// when the branch might be committing
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&
GetRowIdx(io.brupdate.b2.uop.rob_idx) === com_idx) {
io.commit.uops(w).debug_fsrc := BSRC_C
io.commit.uops(w).taken := io.brupdate.b2.taken
}
// Don't attempt to rollback the tail's row when the rob is full.
val rbk_row = rob_state === s_rollback && !full
io.commit.rbk_valids(w) := rbk_row && rob_val(com_idx) && !(enableCommitMapTable.B)
io.commit.rollback := (rob_state === s_rollback)
assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),
"com_valids and rbk_valids are mutually exclusive")
when (rbk_row) {
rob_val(com_idx) := false.B
rob_exception(com_idx) := false.B
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
for (i <- 0 until numRobRows) {
rob_val(i) := false.B
rob_bsy(i) := false.B
rob_uop(i).debug_inst := BUBBLE
}
}
}
// -----------------------------------------------
// Kill speculated entries on branch mispredict
for (i <- 0 until numRobRows) {
val br_mask = rob_uop(i).br_mask
//kill instruction if mispredict & br mask match
when (IsKilledByBranch(io.brupdate, br_mask))
{
rob_val(i) := false.B
rob_uop(i.U).debug_inst := BUBBLE
} .elsewhen (rob_val(i)) {
// clear speculation bit even on correct speculation
rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)
}
}
// Debug signal to figure out which prediction structure
// or core resolved a branch correctly
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken
}
// -----------------------------------------------
// Commit
when (will_commit(w)) {
rob_val(rob_head) := false.B
}
// -----------------------------------------------
// Outputs
rob_head_vals(w) := rob_val(rob_head)
rob_tail_vals(w) := rob_val(rob_tail)
rob_head_fflags(w) := rob_fflags(w)(rob_head)
rob_head_uses_stq(w) := rob_uop(rob_head).uses_stq
rob_head_uses_ldq(w) := rob_uop(rob_head).uses_ldq
//------------------------------------------------
// Invalid entries are safe; thrown exceptions are unsafe.
for (i <- 0 until numRobRows) {
rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))
}
// Read unsafe status of PNR row.
rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))
// -----------------------------------------------
// debugging write ports that should not be synthesized
when (will_commit(w)) {
rob_uop(rob_head).debug_inst := BUBBLE
} .elsewhen (rbk_row)
{
rob_uop(rob_tail).debug_inst := BUBBLE
}
//--------------------------------------------------
// Debug: for debug purposes, track side-effects to all register destinations
for (i <- 0 until numWakeupPorts) {
val rob_idx = io.wb_resps(i).bits.uop.rob_idx
when (io.debug_wb_valids(i) && MatchBank(GetBankIdx(rob_idx))) {
rob_debug_wdata(GetRowIdx(rob_idx)) := io.debug_wb_wdata(i)
}
val temp_uop = rob_uop(GetRowIdx(rob_idx))
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_val(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to an invalid ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_bsy(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to a not-busy ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
temp_uop.ldst_val && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),
"[rob] writeback (" + i + ") occurred to the wrong pdst.")
}
io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)
} //for (w <- 0 until coreWidth)
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// -----------------------------------------------
// Commit Logic
// need to take a "can_commit" array, and let the first can_commits commit
// previous instructions may block the commit of younger instructions in the commit bundle
// e.g., exception, or (valid && busy).
// Finally, don't throw an exception if there are instructions in front of
// it that want to commit (only throw exception when head of the bundle).
var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))
var will_throw_exception = false.B
var block_xcpt = false.B
for (w <- 0 until coreWidth) {
will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception
will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit
block_commit = (rob_head_vals(w) &&
(!can_commit(w) || can_throw_exception(w))) || block_commit
block_xcpt = will_commit(w)
}
// Note: exception must be in the commit bundle.
// Note: exception must be the first valid instruction in the commit bundle.
exception_thrown := will_throw_exception
val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)
io.com_xcpt.valid := exception_thrown && !is_mini_exception
io.com_xcpt.bits := DontCare
io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause
io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)
val insn_sys_pc2epc =
rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})
val refetch_inst = exception_thrown || insn_sys_pc2epc
val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)
io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx
io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst
io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc
io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob
val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}
val flush_commit = flush_commit_mask.reduce(_|_)
val flush_val = exception_thrown || flush_commit
assert(!(PopCount(flush_commit_mask) > 1.U),
"[rob] Can't commit multiple flush_on_commit instructions on one cycle")
val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))
// delay a cycle for critical path considerations
io.flush.valid := flush_val
io.flush.bits := DontCare
io.flush.bits.ftq_idx := flush_uop.ftq_idx
io.flush.bits.pc_lob := flush_uop.pc_lob
io.flush.bits.edge_inst := flush_uop.edge_inst
io.flush.bits.is_rvc := flush_uop.is_rvc
io.flush.bits.flush_typ := FlushTypes.getType(flush_val,
exception_thrown && !is_mini_exception,
flush_commit && flush_uop.uopc === uopERET,
refetch_inst)
// -----------------------------------------------
// FP Exceptions
// send fflags bits to the CSRFile to accrue
val fflags_val = Wire(Vec(coreWidth, Bool()))
val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
for (w <- 0 until coreWidth) {
fflags_val(w) :=
io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
!io.commit.uops(w).uses_stq
fflags(w) := Mux(fflags_val(w), rob_head_fflags(w), 0.U)
assert (!(io.commit.valids(w) &&
!io.commit.uops(w).fp_val &&
rob_head_fflags(w) =/= 0.U),
"Committed non-FP instruction has non-zero fflag bits.")
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
(io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&
rob_head_fflags(w) =/= 0.U),
"Committed FP load or store has non-zero fflag bits.")
}
io.commit.fflags.valid := fflags_val.reduce(_|_)
io.commit.fflags.bits := fflags.reduce(_|_)
// -----------------------------------------------
// Exception Tracking Logic
// only store the oldest exception, since only one can happen!
val next_xcpt_uop = Wire(new MicroOp())
next_xcpt_uop := r_xcpt_uop
val enq_xcpts = Wire(Vec(coreWidth, Bool()))
for (i <- 0 until coreWidth) {
enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception
}
when (!(io.flush.valid || exception_thrown) && rob_state =/= s_rollback) {
val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid
val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)
val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when (new_xcpt_valid) {
when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {
r_xcpt_val := true.B
next_xcpt_uop := new_xcpt.uop
next_xcpt_uop.exc_cause := new_xcpt.cause
r_xcpt_badvaddr := new_xcpt.badvaddr
}
} .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {
val idx = enq_xcpts.indexWhere{i: Bool => i}
// if no exception yet, dispatch exception wins
r_xcpt_val := true.B
next_xcpt_uop := io.enq_uops(idx)
r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob
}
}
r_xcpt_uop := next_xcpt_uop
r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)
when (io.flush.valid || IsKilledByBranch(io.brupdate, next_xcpt_uop)) {
r_xcpt_val := false.B
}
assert (!(exception_thrown && !r_xcpt_val),
"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause")
assert (!(empty && r_xcpt_val),
"ROB is empty, but believes it has an outstanding exception.")
assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),
"ROB is throwing an exception, but the stored exception information's " +
"rob_idx does not match the rob_head")
// -----------------------------------------------
// ROB Head Logic
// remember if we're still waiting on the rest of the dispatch packet, and prevent
// the rob_head from advancing if it commits a partial parket before we
// dispatch the rest of it.
// update when committed ALL valid instructions in commit_bundle
val rob_deq = WireInit(false.B)
val r_partial_row = RegInit(false.B)
when (io.enq_valids.reduce(_|_)) {
r_partial_row := io.enq_partial_stall
}
val finished_committing_row =
(io.commit.valids.asUInt =/= 0.U) &&
((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&
!(r_partial_row && rob_head === rob_tail && !maybe_full)
when (finished_committing_row) {
rob_head := WrapInc(rob_head, numRobRows)
rob_head_lsb := 0.U
rob_deq := true.B
} .otherwise {
rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))
}
// -----------------------------------------------
// ROB Point-of-No-Return (PNR) Logic
// Acts as a second head, but only waits on busy instructions which might cause misspeculation.
// TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?
// Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.
// Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.
if (enableFastPNR) {
val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)
val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,
AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),
rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))
rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)
if (coreWidth > 1)
rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)
} else {
// Distinguish between PNR being at head/tail when ROB is full.
// Works the same as maybe_full tracking for the ROB tail.
val pnr_maybe_at_tail = RegInit(false.B)
val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty
val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))
when (empty && io.enq_valids.asUInt =/= 0.U) {
// Unforunately for us, the ROB does not use its entries in monotonically
// increasing order, even in the case of no exceptions. The edge case
// arises when partial rows are enqueued and committed, leaving an empty
// ROB.
rob_pnr := rob_head
rob_pnr_lsb := PriorityEncoder(io.enq_valids)
} .elsewhen (safe_to_inc && do_inc_row) {
rob_pnr := WrapInc(rob_pnr, numRobRows)
rob_pnr_lsb := 0.U
} .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)
} .elsewhen (safe_to_inc && !full && !empty) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))
} .elsewhen (full && pnr_maybe_at_tail) {
rob_pnr_lsb := 0.U
}
pnr_maybe_at_tail := !rob_deq && (do_inc_row || pnr_maybe_at_tail)
}
// Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.
assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)
// PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.
assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)
// -----------------------------------------------
// ROB Tail Logic
val rob_enq = WireInit(false.B)
when (rob_state === s_rollback && (rob_tail =/= rob_head || maybe_full)) {
// Rollback a row
rob_tail := WrapDec(rob_tail, numRobRows)
rob_tail_lsb := (coreWidth-1).U
rob_deq := true.B
} .elsewhen (rob_state === s_rollback && (rob_tail === rob_head) && !maybe_full) {
// Rollback an entry
rob_tail_lsb := rob_head_lsb
} .elsewhen (io.brupdate.b2.mispredict) {
rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)
rob_tail_lsb := 0.U
} .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {
rob_tail := WrapInc(rob_tail, numRobRows)
rob_tail_lsb := 0.U
rob_enq := true.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {
rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))
}
if (enableCommitMapTable) {
when (RegNext(exception_thrown)) {
rob_tail := 0.U
rob_tail_lsb := 0.U
rob_head := 0.U
rob_pnr := 0.U
rob_pnr_lsb := 0.U
}
}
// -----------------------------------------------
// Full/Empty Logic
// The ROB can be completely full, but only if it did not dispatch a row in the prior cycle.
// I.E. at least one entry will be empty when in a steady state of dispatching and committing a row each cycle.
// TODO should we add an extra 'parity bit' onto the ROB pointers to simplify this logic?
maybe_full := !rob_deq && (rob_enq || maybe_full) || io.brupdate.b1.mispredict_mask =/= 0.U
full := rob_tail === rob_head && maybe_full
empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)
io.rob_head_idx := rob_head_idx
io.rob_tail_idx := rob_tail_idx
io.rob_pnr_idx := rob_pnr_idx
io.empty := empty
io.ready := (rob_state === s_normal) && !full && !r_xcpt_val
//-----------------------------------------------
//-----------------------------------------------
//-----------------------------------------------
// ROB FSM
if (!enableCommitMapTable) {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
// Delay rollback 2 cycles so branch mispredictions can drain
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (empty) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (RegNext(exception_thrown)) {
rob_state := s_rollback
} .elsewhen (empty) {
rob_state := s_normal
}
}
}
} else {
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
when (exception_thrown) {
; //rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
when (rob_tail_idx === rob_head_idx) {
rob_state := s_normal
}
}
is (s_wait_till_empty) {
when (exception_thrown) {
; //rob_state := s_rollback
} .elsewhen (rob_tail === rob_head) {
rob_state := s_normal
}
}
}
}
// -----------------------------------------------
// Outputs
io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&
!will_commit.reduce(_||_))
override def toString: String = BoomCoreStringPrefix(
"==ROB==",
"Machine Width : " + coreWidth,
"Rob Entries : " + numRobEntries,
"Rob Rows : " + numRobRows,
"Rob Row size : " + log2Ceil(numRobRows),
"log2Ceil(coreWidth): " + log2Ceil(coreWidth),
"FPU FFlag Ports : " + numFpuPorts)
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
| module Rob_1( // @[rob.scala:211:7]
input clock, // @[rob.scala:211:7]
input reset, // @[rob.scala:211:7]
input io_enq_valids_0, // @[rob.scala:216:14]
input io_enq_valids_1, // @[rob.scala:216:14]
input io_enq_valids_2, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_uopc, // @[rob.scala:216:14]
input [31:0] io_enq_uops_0_inst, // @[rob.scala:216:14]
input [31:0] io_enq_uops_0_debug_inst, // @[rob.scala:216:14]
input io_enq_uops_0_is_rvc, // @[rob.scala:216:14]
input [39:0] io_enq_uops_0_debug_pc, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_iq_type, // @[rob.scala:216:14]
input [9:0] io_enq_uops_0_fu_code, // @[rob.scala:216:14]
input [3:0] io_enq_uops_0_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_ctrl_op_fcn, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_enq_uops_0_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_load, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_sta, // @[rob.scala:216:14]
input io_enq_uops_0_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_iw_state, // @[rob.scala:216:14]
input io_enq_uops_0_iw_p1_poisoned, // @[rob.scala:216:14]
input io_enq_uops_0_iw_p2_poisoned, // @[rob.scala:216:14]
input io_enq_uops_0_is_br, // @[rob.scala:216:14]
input io_enq_uops_0_is_jalr, // @[rob.scala:216:14]
input io_enq_uops_0_is_jal, // @[rob.scala:216:14]
input io_enq_uops_0_is_sfb, // @[rob.scala:216:14]
input [15:0] io_enq_uops_0_br_mask, // @[rob.scala:216:14]
input [3:0] io_enq_uops_0_br_tag, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_ftq_idx, // @[rob.scala:216:14]
input io_enq_uops_0_edge_inst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_pc_lob, // @[rob.scala:216:14]
input io_enq_uops_0_taken, // @[rob.scala:216:14]
input [19:0] io_enq_uops_0_imm_packed, // @[rob.scala:216:14]
input [11:0] io_enq_uops_0_csr_addr, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_rob_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_stq_idx, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_pdst, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_prs1, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_prs2, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_prs3, // @[rob.scala:216:14]
input io_enq_uops_0_prs1_busy, // @[rob.scala:216:14]
input io_enq_uops_0_prs2_busy, // @[rob.scala:216:14]
input io_enq_uops_0_prs3_busy, // @[rob.scala:216:14]
input [6:0] io_enq_uops_0_stale_pdst, // @[rob.scala:216:14]
input io_enq_uops_0_exception, // @[rob.scala:216:14]
input [63:0] io_enq_uops_0_exc_cause, // @[rob.scala:216:14]
input io_enq_uops_0_bypassable, // @[rob.scala:216:14]
input [4:0] io_enq_uops_0_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_mem_size, // @[rob.scala:216:14]
input io_enq_uops_0_mem_signed, // @[rob.scala:216:14]
input io_enq_uops_0_is_fence, // @[rob.scala:216:14]
input io_enq_uops_0_is_fencei, // @[rob.scala:216:14]
input io_enq_uops_0_is_amo, // @[rob.scala:216:14]
input io_enq_uops_0_uses_ldq, // @[rob.scala:216:14]
input io_enq_uops_0_uses_stq, // @[rob.scala:216:14]
input io_enq_uops_0_is_sys_pc2epc, // @[rob.scala:216:14]
input io_enq_uops_0_is_unique, // @[rob.scala:216:14]
input io_enq_uops_0_flush_on_commit, // @[rob.scala:216:14]
input io_enq_uops_0_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_ldst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs2, // @[rob.scala:216:14]
input [5:0] io_enq_uops_0_lrs3, // @[rob.scala:216:14]
input io_enq_uops_0_ldst_val, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_lrs2_rtype, // @[rob.scala:216:14]
input io_enq_uops_0_frs3_en, // @[rob.scala:216:14]
input io_enq_uops_0_fp_val, // @[rob.scala:216:14]
input io_enq_uops_0_fp_single, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_pf_if, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_ae_if, // @[rob.scala:216:14]
input io_enq_uops_0_xcpt_ma_if, // @[rob.scala:216:14]
input io_enq_uops_0_bp_debug_if, // @[rob.scala:216:14]
input io_enq_uops_0_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_enq_uops_0_debug_tsrc, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_uopc, // @[rob.scala:216:14]
input [31:0] io_enq_uops_1_inst, // @[rob.scala:216:14]
input [31:0] io_enq_uops_1_debug_inst, // @[rob.scala:216:14]
input io_enq_uops_1_is_rvc, // @[rob.scala:216:14]
input [39:0] io_enq_uops_1_debug_pc, // @[rob.scala:216:14]
input [2:0] io_enq_uops_1_iq_type, // @[rob.scala:216:14]
input [9:0] io_enq_uops_1_fu_code, // @[rob.scala:216:14]
input [3:0] io_enq_uops_1_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_1_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_1_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_enq_uops_1_ctrl_op_fcn, // @[rob.scala:216:14]
input io_enq_uops_1_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_enq_uops_1_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_enq_uops_1_ctrl_is_load, // @[rob.scala:216:14]
input io_enq_uops_1_ctrl_is_sta, // @[rob.scala:216:14]
input io_enq_uops_1_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_iw_state, // @[rob.scala:216:14]
input io_enq_uops_1_iw_p1_poisoned, // @[rob.scala:216:14]
input io_enq_uops_1_iw_p2_poisoned, // @[rob.scala:216:14]
input io_enq_uops_1_is_br, // @[rob.scala:216:14]
input io_enq_uops_1_is_jalr, // @[rob.scala:216:14]
input io_enq_uops_1_is_jal, // @[rob.scala:216:14]
input io_enq_uops_1_is_sfb, // @[rob.scala:216:14]
input [15:0] io_enq_uops_1_br_mask, // @[rob.scala:216:14]
input [3:0] io_enq_uops_1_br_tag, // @[rob.scala:216:14]
input [4:0] io_enq_uops_1_ftq_idx, // @[rob.scala:216:14]
input io_enq_uops_1_edge_inst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_1_pc_lob, // @[rob.scala:216:14]
input io_enq_uops_1_taken, // @[rob.scala:216:14]
input [19:0] io_enq_uops_1_imm_packed, // @[rob.scala:216:14]
input [11:0] io_enq_uops_1_csr_addr, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_rob_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_1_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_1_stq_idx, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_pdst, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_prs1, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_prs2, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_prs3, // @[rob.scala:216:14]
input io_enq_uops_1_prs1_busy, // @[rob.scala:216:14]
input io_enq_uops_1_prs2_busy, // @[rob.scala:216:14]
input io_enq_uops_1_prs3_busy, // @[rob.scala:216:14]
input [6:0] io_enq_uops_1_stale_pdst, // @[rob.scala:216:14]
input io_enq_uops_1_exception, // @[rob.scala:216:14]
input [63:0] io_enq_uops_1_exc_cause, // @[rob.scala:216:14]
input io_enq_uops_1_bypassable, // @[rob.scala:216:14]
input [4:0] io_enq_uops_1_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_mem_size, // @[rob.scala:216:14]
input io_enq_uops_1_mem_signed, // @[rob.scala:216:14]
input io_enq_uops_1_is_fence, // @[rob.scala:216:14]
input io_enq_uops_1_is_fencei, // @[rob.scala:216:14]
input io_enq_uops_1_is_amo, // @[rob.scala:216:14]
input io_enq_uops_1_uses_ldq, // @[rob.scala:216:14]
input io_enq_uops_1_uses_stq, // @[rob.scala:216:14]
input io_enq_uops_1_is_sys_pc2epc, // @[rob.scala:216:14]
input io_enq_uops_1_is_unique, // @[rob.scala:216:14]
input io_enq_uops_1_flush_on_commit, // @[rob.scala:216:14]
input io_enq_uops_1_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_1_ldst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_1_lrs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_1_lrs2, // @[rob.scala:216:14]
input [5:0] io_enq_uops_1_lrs3, // @[rob.scala:216:14]
input io_enq_uops_1_ldst_val, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_lrs2_rtype, // @[rob.scala:216:14]
input io_enq_uops_1_frs3_en, // @[rob.scala:216:14]
input io_enq_uops_1_fp_val, // @[rob.scala:216:14]
input io_enq_uops_1_fp_single, // @[rob.scala:216:14]
input io_enq_uops_1_xcpt_pf_if, // @[rob.scala:216:14]
input io_enq_uops_1_xcpt_ae_if, // @[rob.scala:216:14]
input io_enq_uops_1_xcpt_ma_if, // @[rob.scala:216:14]
input io_enq_uops_1_bp_debug_if, // @[rob.scala:216:14]
input io_enq_uops_1_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_enq_uops_1_debug_tsrc, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_uopc, // @[rob.scala:216:14]
input [31:0] io_enq_uops_2_inst, // @[rob.scala:216:14]
input [31:0] io_enq_uops_2_debug_inst, // @[rob.scala:216:14]
input io_enq_uops_2_is_rvc, // @[rob.scala:216:14]
input [39:0] io_enq_uops_2_debug_pc, // @[rob.scala:216:14]
input [2:0] io_enq_uops_2_iq_type, // @[rob.scala:216:14]
input [9:0] io_enq_uops_2_fu_code, // @[rob.scala:216:14]
input [3:0] io_enq_uops_2_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_2_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_enq_uops_2_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_enq_uops_2_ctrl_op_fcn, // @[rob.scala:216:14]
input io_enq_uops_2_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_enq_uops_2_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_enq_uops_2_ctrl_is_load, // @[rob.scala:216:14]
input io_enq_uops_2_ctrl_is_sta, // @[rob.scala:216:14]
input io_enq_uops_2_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_iw_state, // @[rob.scala:216:14]
input io_enq_uops_2_iw_p1_poisoned, // @[rob.scala:216:14]
input io_enq_uops_2_iw_p2_poisoned, // @[rob.scala:216:14]
input io_enq_uops_2_is_br, // @[rob.scala:216:14]
input io_enq_uops_2_is_jalr, // @[rob.scala:216:14]
input io_enq_uops_2_is_jal, // @[rob.scala:216:14]
input io_enq_uops_2_is_sfb, // @[rob.scala:216:14]
input [15:0] io_enq_uops_2_br_mask, // @[rob.scala:216:14]
input [3:0] io_enq_uops_2_br_tag, // @[rob.scala:216:14]
input [4:0] io_enq_uops_2_ftq_idx, // @[rob.scala:216:14]
input io_enq_uops_2_edge_inst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_2_pc_lob, // @[rob.scala:216:14]
input io_enq_uops_2_taken, // @[rob.scala:216:14]
input [19:0] io_enq_uops_2_imm_packed, // @[rob.scala:216:14]
input [11:0] io_enq_uops_2_csr_addr, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_rob_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_2_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_enq_uops_2_stq_idx, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_pdst, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_prs1, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_prs2, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_prs3, // @[rob.scala:216:14]
input io_enq_uops_2_prs1_busy, // @[rob.scala:216:14]
input io_enq_uops_2_prs2_busy, // @[rob.scala:216:14]
input io_enq_uops_2_prs3_busy, // @[rob.scala:216:14]
input [6:0] io_enq_uops_2_stale_pdst, // @[rob.scala:216:14]
input io_enq_uops_2_exception, // @[rob.scala:216:14]
input [63:0] io_enq_uops_2_exc_cause, // @[rob.scala:216:14]
input io_enq_uops_2_bypassable, // @[rob.scala:216:14]
input [4:0] io_enq_uops_2_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_mem_size, // @[rob.scala:216:14]
input io_enq_uops_2_mem_signed, // @[rob.scala:216:14]
input io_enq_uops_2_is_fence, // @[rob.scala:216:14]
input io_enq_uops_2_is_fencei, // @[rob.scala:216:14]
input io_enq_uops_2_is_amo, // @[rob.scala:216:14]
input io_enq_uops_2_uses_ldq, // @[rob.scala:216:14]
input io_enq_uops_2_uses_stq, // @[rob.scala:216:14]
input io_enq_uops_2_is_sys_pc2epc, // @[rob.scala:216:14]
input io_enq_uops_2_is_unique, // @[rob.scala:216:14]
input io_enq_uops_2_flush_on_commit, // @[rob.scala:216:14]
input io_enq_uops_2_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_2_ldst, // @[rob.scala:216:14]
input [5:0] io_enq_uops_2_lrs1, // @[rob.scala:216:14]
input [5:0] io_enq_uops_2_lrs2, // @[rob.scala:216:14]
input [5:0] io_enq_uops_2_lrs3, // @[rob.scala:216:14]
input io_enq_uops_2_ldst_val, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_lrs2_rtype, // @[rob.scala:216:14]
input io_enq_uops_2_frs3_en, // @[rob.scala:216:14]
input io_enq_uops_2_fp_val, // @[rob.scala:216:14]
input io_enq_uops_2_fp_single, // @[rob.scala:216:14]
input io_enq_uops_2_xcpt_pf_if, // @[rob.scala:216:14]
input io_enq_uops_2_xcpt_ae_if, // @[rob.scala:216:14]
input io_enq_uops_2_xcpt_ma_if, // @[rob.scala:216:14]
input io_enq_uops_2_bp_debug_if, // @[rob.scala:216:14]
input io_enq_uops_2_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_enq_uops_2_debug_tsrc, // @[rob.scala:216:14]
input io_enq_partial_stall, // @[rob.scala:216:14]
input [39:0] io_xcpt_fetch_pc, // @[rob.scala:216:14]
output [6:0] io_rob_tail_idx, // @[rob.scala:216:14]
output [6:0] io_rob_pnr_idx, // @[rob.scala:216:14]
output [6:0] io_rob_head_idx, // @[rob.scala:216:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[rob.scala:216:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rob.scala:216:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[rob.scala:216:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_br, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_jalr, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_jal, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rob.scala:216:14]
input io_brupdate_b2_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rob.scala:216:14]
input io_brupdate_b2_uop_taken, // @[rob.scala:216:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs1_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs2_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_prs3_busy, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rob.scala:216:14]
input io_brupdate_b2_uop_exception, // @[rob.scala:216:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rob.scala:216:14]
input io_brupdate_b2_uop_mem_signed, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_fence, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_fencei, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_amo, // @[rob.scala:216:14]
input io_brupdate_b2_uop_uses_ldq, // @[rob.scala:216:14]
input io_brupdate_b2_uop_uses_stq, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_brupdate_b2_uop_is_unique, // @[rob.scala:216:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rob.scala:216:14]
input io_brupdate_b2_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_brupdate_b2_uop_frs3_en, // @[rob.scala:216:14]
input io_brupdate_b2_uop_fp_val, // @[rob.scala:216:14]
input io_brupdate_b2_uop_fp_single, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rob.scala:216:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rob.scala:216:14]
input io_brupdate_b2_valid, // @[rob.scala:216:14]
input io_brupdate_b2_mispredict, // @[rob.scala:216:14]
input io_brupdate_b2_taken, // @[rob.scala:216:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rob.scala:216:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rob.scala:216:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rob.scala:216:14]
input [20:0] io_brupdate_b2_target_offset, // @[rob.scala:216:14]
input io_wb_resps_0_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_0_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_0_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_0_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_0_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_0_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_0_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_0_bits_data, // @[rob.scala:216:14]
input io_wb_resps_0_bits_predicated, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_0_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_wb_resps_1_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_1_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_1_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_1_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_1_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_1_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_1_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_1_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_1_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_1_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_1_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_1_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_1_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_1_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_1_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_1_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_1_bits_data, // @[rob.scala:216:14]
input io_wb_resps_2_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_2_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_2_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_2_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_2_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_2_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_2_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_2_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_2_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_2_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_2_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_2_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_2_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_2_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_2_bits_data, // @[rob.scala:216:14]
input io_wb_resps_3_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_3_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_3_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_3_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_3_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_3_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_3_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_3_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_3_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_3_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_3_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_3_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_3_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_3_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_3_bits_data, // @[rob.scala:216:14]
input io_wb_resps_4_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_4_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_4_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_4_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_4_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_4_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_4_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_4_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_4_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_4_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_4_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_4_bits_data, // @[rob.scala:216:14]
input io_wb_resps_4_bits_predicated, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_4_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_4_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_4_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_4_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_4_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_4_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_4_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_4_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_4_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_4_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_4_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_4_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_4_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_wb_resps_5_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_5_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_5_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_5_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_5_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_5_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_5_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_5_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_5_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_5_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_5_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [64:0] io_wb_resps_5_bits_data, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_valid, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_wb_resps_5_bits_fflags_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_wb_resps_5_bits_fflags_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_wb_resps_5_bits_fflags_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_fflags_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_wb_resps_5_bits_fflags_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_iw_state, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_br, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_jal, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_wb_resps_5_bits_fflags_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_wb_resps_5_bits_fflags_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_fflags_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_wb_resps_5_bits_fflags_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_wb_resps_5_bits_fflags_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_ppred, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_wb_resps_5_bits_fflags_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_wb_resps_5_bits_fflags_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_mem_size, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_fence, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_amo, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_is_unique, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_fflags_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs3, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_fp_val, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_fp_single, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_wb_resps_5_bits_fflags_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_wb_resps_5_bits_fflags_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_wb_resps_5_bits_fflags_bits_flags, // @[rob.scala:216:14]
input io_lsu_clr_bsy_0_valid, // @[rob.scala:216:14]
input [6:0] io_lsu_clr_bsy_0_bits, // @[rob.scala:216:14]
input io_lsu_clr_bsy_1_valid, // @[rob.scala:216:14]
input [6:0] io_lsu_clr_bsy_1_bits, // @[rob.scala:216:14]
input [6:0] io_lsu_clr_unsafe_0_bits, // @[rob.scala:216:14]
input io_debug_wb_valids_0, // @[rob.scala:216:14]
input io_debug_wb_valids_1, // @[rob.scala:216:14]
input io_debug_wb_valids_2, // @[rob.scala:216:14]
input io_debug_wb_valids_3, // @[rob.scala:216:14]
input io_debug_wb_valids_4, // @[rob.scala:216:14]
input io_debug_wb_valids_5, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_0, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_1, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_2, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_3, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_4, // @[rob.scala:216:14]
input [63:0] io_debug_wb_wdata_5, // @[rob.scala:216:14]
input io_fflags_0_valid, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_fflags_0_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_fflags_0_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_fflags_0_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_fflags_0_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_fflags_0_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_iw_state, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_br, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_jal, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_fflags_0_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_fflags_0_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_fflags_0_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_fflags_0_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_ppred, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_fflags_0_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_fflags_0_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_mem_size, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_fence, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_amo, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_is_unique, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_fflags_0_bits_uop_lrs3, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_fp_val, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_fp_single, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_fflags_0_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_fflags_0_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_fflags_0_bits_flags, // @[rob.scala:216:14]
input io_fflags_1_valid, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_fflags_1_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_fflags_1_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_fflags_1_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_fflags_1_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_fflags_1_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_iw_state, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_br, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_jal, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_fflags_1_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_fflags_1_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_fflags_1_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_fflags_1_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_ppred, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_fflags_1_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_fflags_1_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_mem_size, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_fence, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_amo, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_is_unique, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_fflags_1_bits_uop_lrs3, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_fp_val, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_fp_single, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_fflags_1_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_fflags_1_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_fflags_1_bits_flags, // @[rob.scala:216:14]
input io_lxcpt_valid, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_lxcpt_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_lxcpt_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_lxcpt_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_lxcpt_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_lxcpt_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_iw_state, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_br, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_jal, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_lxcpt_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_lxcpt_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_lxcpt_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_lxcpt_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_ppred, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_lxcpt_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_lxcpt_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_mem_size, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_fence, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_amo, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_is_unique, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_lxcpt_bits_uop_lrs3, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_fp_val, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_fp_single, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_lxcpt_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_lxcpt_bits_uop_debug_tsrc, // @[rob.scala:216:14]
input [4:0] io_lxcpt_bits_cause, // @[rob.scala:216:14]
input [39:0] io_lxcpt_bits_badvaddr, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_uopc, // @[rob.scala:216:14]
input [31:0] io_csr_replay_bits_uop_inst, // @[rob.scala:216:14]
input [31:0] io_csr_replay_bits_uop_debug_inst, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_rvc, // @[rob.scala:216:14]
input [39:0] io_csr_replay_bits_uop_debug_pc, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_iq_type, // @[rob.scala:216:14]
input [9:0] io_csr_replay_bits_uop_fu_code, // @[rob.scala:216:14]
input [3:0] io_csr_replay_bits_uop_ctrl_br_type, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_ctrl_op1_sel, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_op2_sel, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_imm_sel, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_ctrl_op_fcn, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_fcn_dw, // @[rob.scala:216:14]
input [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_load, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_sta, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ctrl_is_std, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_iw_state, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_iw_p1_poisoned, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_iw_p2_poisoned, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_br, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_jalr, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_jal, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_sfb, // @[rob.scala:216:14]
input [15:0] io_csr_replay_bits_uop_br_mask, // @[rob.scala:216:14]
input [3:0] io_csr_replay_bits_uop_br_tag, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_ftq_idx, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_edge_inst, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_pc_lob, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_taken, // @[rob.scala:216:14]
input [19:0] io_csr_replay_bits_uop_imm_packed, // @[rob.scala:216:14]
input [11:0] io_csr_replay_bits_uop_csr_addr, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_rob_idx, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_ldq_idx, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_stq_idx, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_rxq_idx, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_pdst, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_prs1, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_prs2, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_prs3, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_ppred, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs1_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs2_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_prs3_busy, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ppred_busy, // @[rob.scala:216:14]
input [6:0] io_csr_replay_bits_uop_stale_pdst, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_exception, // @[rob.scala:216:14]
input [63:0] io_csr_replay_bits_uop_exc_cause, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bypassable, // @[rob.scala:216:14]
input [4:0] io_csr_replay_bits_uop_mem_cmd, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_mem_size, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_mem_signed, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_fence, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_fencei, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_amo, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_uses_ldq, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_uses_stq, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_sys_pc2epc, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_is_unique, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_flush_on_commit, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ldst_is_rs1, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_ldst, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs1, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs2, // @[rob.scala:216:14]
input [5:0] io_csr_replay_bits_uop_lrs3, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_ldst_val, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_dst_rtype, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_lrs1_rtype, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_lrs2_rtype, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_frs3_en, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_fp_val, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_fp_single, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_pf_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_ae_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_xcpt_ma_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bp_debug_if, // @[rob.scala:216:14]
input io_csr_replay_bits_uop_bp_xcpt_if, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_debug_fsrc, // @[rob.scala:216:14]
input [1:0] io_csr_replay_bits_uop_debug_tsrc, // @[rob.scala:216:14]
output io_commit_valids_0, // @[rob.scala:216:14]
output io_commit_valids_1, // @[rob.scala:216:14]
output io_commit_valids_2, // @[rob.scala:216:14]
output io_commit_arch_valids_0, // @[rob.scala:216:14]
output io_commit_arch_valids_1, // @[rob.scala:216:14]
output io_commit_arch_valids_2, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_uopc, // @[rob.scala:216:14]
output [31:0] io_commit_uops_0_inst, // @[rob.scala:216:14]
output [31:0] io_commit_uops_0_debug_inst, // @[rob.scala:216:14]
output io_commit_uops_0_is_rvc, // @[rob.scala:216:14]
output [39:0] io_commit_uops_0_debug_pc, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_iq_type, // @[rob.scala:216:14]
output [9:0] io_commit_uops_0_fu_code, // @[rob.scala:216:14]
output [3:0] io_commit_uops_0_ctrl_br_type, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_ctrl_op1_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_op2_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_imm_sel, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_ctrl_op_fcn, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_fcn_dw, // @[rob.scala:216:14]
output [2:0] io_commit_uops_0_ctrl_csr_cmd, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_load, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_sta, // @[rob.scala:216:14]
output io_commit_uops_0_ctrl_is_std, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_iw_state, // @[rob.scala:216:14]
output io_commit_uops_0_iw_p1_poisoned, // @[rob.scala:216:14]
output io_commit_uops_0_iw_p2_poisoned, // @[rob.scala:216:14]
output io_commit_uops_0_is_br, // @[rob.scala:216:14]
output io_commit_uops_0_is_jalr, // @[rob.scala:216:14]
output io_commit_uops_0_is_jal, // @[rob.scala:216:14]
output io_commit_uops_0_is_sfb, // @[rob.scala:216:14]
output [15:0] io_commit_uops_0_br_mask, // @[rob.scala:216:14]
output [3:0] io_commit_uops_0_br_tag, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_ftq_idx, // @[rob.scala:216:14]
output io_commit_uops_0_edge_inst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_pc_lob, // @[rob.scala:216:14]
output io_commit_uops_0_taken, // @[rob.scala:216:14]
output [19:0] io_commit_uops_0_imm_packed, // @[rob.scala:216:14]
output [11:0] io_commit_uops_0_csr_addr, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_rob_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_ldq_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_stq_idx, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_rxq_idx, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_pdst, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_prs1, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_prs2, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_prs3, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_ppred, // @[rob.scala:216:14]
output io_commit_uops_0_prs1_busy, // @[rob.scala:216:14]
output io_commit_uops_0_prs2_busy, // @[rob.scala:216:14]
output io_commit_uops_0_prs3_busy, // @[rob.scala:216:14]
output io_commit_uops_0_ppred_busy, // @[rob.scala:216:14]
output [6:0] io_commit_uops_0_stale_pdst, // @[rob.scala:216:14]
output io_commit_uops_0_exception, // @[rob.scala:216:14]
output [63:0] io_commit_uops_0_exc_cause, // @[rob.scala:216:14]
output io_commit_uops_0_bypassable, // @[rob.scala:216:14]
output [4:0] io_commit_uops_0_mem_cmd, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_mem_size, // @[rob.scala:216:14]
output io_commit_uops_0_mem_signed, // @[rob.scala:216:14]
output io_commit_uops_0_is_fence, // @[rob.scala:216:14]
output io_commit_uops_0_is_fencei, // @[rob.scala:216:14]
output io_commit_uops_0_is_amo, // @[rob.scala:216:14]
output io_commit_uops_0_uses_ldq, // @[rob.scala:216:14]
output io_commit_uops_0_uses_stq, // @[rob.scala:216:14]
output io_commit_uops_0_is_sys_pc2epc, // @[rob.scala:216:14]
output io_commit_uops_0_is_unique, // @[rob.scala:216:14]
output io_commit_uops_0_flush_on_commit, // @[rob.scala:216:14]
output io_commit_uops_0_ldst_is_rs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_ldst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs2, // @[rob.scala:216:14]
output [5:0] io_commit_uops_0_lrs3, // @[rob.scala:216:14]
output io_commit_uops_0_ldst_val, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_dst_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_lrs1_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_lrs2_rtype, // @[rob.scala:216:14]
output io_commit_uops_0_frs3_en, // @[rob.scala:216:14]
output io_commit_uops_0_fp_val, // @[rob.scala:216:14]
output io_commit_uops_0_fp_single, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_pf_if, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_ae_if, // @[rob.scala:216:14]
output io_commit_uops_0_xcpt_ma_if, // @[rob.scala:216:14]
output io_commit_uops_0_bp_debug_if, // @[rob.scala:216:14]
output io_commit_uops_0_bp_xcpt_if, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_debug_fsrc, // @[rob.scala:216:14]
output [1:0] io_commit_uops_0_debug_tsrc, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_uopc, // @[rob.scala:216:14]
output [31:0] io_commit_uops_1_inst, // @[rob.scala:216:14]
output [31:0] io_commit_uops_1_debug_inst, // @[rob.scala:216:14]
output io_commit_uops_1_is_rvc, // @[rob.scala:216:14]
output [39:0] io_commit_uops_1_debug_pc, // @[rob.scala:216:14]
output [2:0] io_commit_uops_1_iq_type, // @[rob.scala:216:14]
output [9:0] io_commit_uops_1_fu_code, // @[rob.scala:216:14]
output [3:0] io_commit_uops_1_ctrl_br_type, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_ctrl_op1_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_1_ctrl_op2_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_1_ctrl_imm_sel, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_ctrl_op_fcn, // @[rob.scala:216:14]
output io_commit_uops_1_ctrl_fcn_dw, // @[rob.scala:216:14]
output [2:0] io_commit_uops_1_ctrl_csr_cmd, // @[rob.scala:216:14]
output io_commit_uops_1_ctrl_is_load, // @[rob.scala:216:14]
output io_commit_uops_1_ctrl_is_sta, // @[rob.scala:216:14]
output io_commit_uops_1_ctrl_is_std, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_iw_state, // @[rob.scala:216:14]
output io_commit_uops_1_iw_p1_poisoned, // @[rob.scala:216:14]
output io_commit_uops_1_iw_p2_poisoned, // @[rob.scala:216:14]
output io_commit_uops_1_is_br, // @[rob.scala:216:14]
output io_commit_uops_1_is_jalr, // @[rob.scala:216:14]
output io_commit_uops_1_is_jal, // @[rob.scala:216:14]
output io_commit_uops_1_is_sfb, // @[rob.scala:216:14]
output [15:0] io_commit_uops_1_br_mask, // @[rob.scala:216:14]
output [3:0] io_commit_uops_1_br_tag, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_ftq_idx, // @[rob.scala:216:14]
output io_commit_uops_1_edge_inst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_1_pc_lob, // @[rob.scala:216:14]
output io_commit_uops_1_taken, // @[rob.scala:216:14]
output [19:0] io_commit_uops_1_imm_packed, // @[rob.scala:216:14]
output [11:0] io_commit_uops_1_csr_addr, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_rob_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_ldq_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_stq_idx, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_rxq_idx, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_pdst, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_prs1, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_prs2, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_prs3, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_ppred, // @[rob.scala:216:14]
output io_commit_uops_1_prs1_busy, // @[rob.scala:216:14]
output io_commit_uops_1_prs2_busy, // @[rob.scala:216:14]
output io_commit_uops_1_prs3_busy, // @[rob.scala:216:14]
output io_commit_uops_1_ppred_busy, // @[rob.scala:216:14]
output [6:0] io_commit_uops_1_stale_pdst, // @[rob.scala:216:14]
output io_commit_uops_1_exception, // @[rob.scala:216:14]
output [63:0] io_commit_uops_1_exc_cause, // @[rob.scala:216:14]
output io_commit_uops_1_bypassable, // @[rob.scala:216:14]
output [4:0] io_commit_uops_1_mem_cmd, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_mem_size, // @[rob.scala:216:14]
output io_commit_uops_1_mem_signed, // @[rob.scala:216:14]
output io_commit_uops_1_is_fence, // @[rob.scala:216:14]
output io_commit_uops_1_is_fencei, // @[rob.scala:216:14]
output io_commit_uops_1_is_amo, // @[rob.scala:216:14]
output io_commit_uops_1_uses_ldq, // @[rob.scala:216:14]
output io_commit_uops_1_uses_stq, // @[rob.scala:216:14]
output io_commit_uops_1_is_sys_pc2epc, // @[rob.scala:216:14]
output io_commit_uops_1_is_unique, // @[rob.scala:216:14]
output io_commit_uops_1_flush_on_commit, // @[rob.scala:216:14]
output io_commit_uops_1_ldst_is_rs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_1_ldst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_1_lrs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_1_lrs2, // @[rob.scala:216:14]
output [5:0] io_commit_uops_1_lrs3, // @[rob.scala:216:14]
output io_commit_uops_1_ldst_val, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_dst_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_lrs1_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_lrs2_rtype, // @[rob.scala:216:14]
output io_commit_uops_1_frs3_en, // @[rob.scala:216:14]
output io_commit_uops_1_fp_val, // @[rob.scala:216:14]
output io_commit_uops_1_fp_single, // @[rob.scala:216:14]
output io_commit_uops_1_xcpt_pf_if, // @[rob.scala:216:14]
output io_commit_uops_1_xcpt_ae_if, // @[rob.scala:216:14]
output io_commit_uops_1_xcpt_ma_if, // @[rob.scala:216:14]
output io_commit_uops_1_bp_debug_if, // @[rob.scala:216:14]
output io_commit_uops_1_bp_xcpt_if, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_debug_fsrc, // @[rob.scala:216:14]
output [1:0] io_commit_uops_1_debug_tsrc, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_uopc, // @[rob.scala:216:14]
output [31:0] io_commit_uops_2_inst, // @[rob.scala:216:14]
output [31:0] io_commit_uops_2_debug_inst, // @[rob.scala:216:14]
output io_commit_uops_2_is_rvc, // @[rob.scala:216:14]
output [39:0] io_commit_uops_2_debug_pc, // @[rob.scala:216:14]
output [2:0] io_commit_uops_2_iq_type, // @[rob.scala:216:14]
output [9:0] io_commit_uops_2_fu_code, // @[rob.scala:216:14]
output [3:0] io_commit_uops_2_ctrl_br_type, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_ctrl_op1_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_2_ctrl_op2_sel, // @[rob.scala:216:14]
output [2:0] io_commit_uops_2_ctrl_imm_sel, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_ctrl_op_fcn, // @[rob.scala:216:14]
output io_commit_uops_2_ctrl_fcn_dw, // @[rob.scala:216:14]
output [2:0] io_commit_uops_2_ctrl_csr_cmd, // @[rob.scala:216:14]
output io_commit_uops_2_ctrl_is_load, // @[rob.scala:216:14]
output io_commit_uops_2_ctrl_is_sta, // @[rob.scala:216:14]
output io_commit_uops_2_ctrl_is_std, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_iw_state, // @[rob.scala:216:14]
output io_commit_uops_2_iw_p1_poisoned, // @[rob.scala:216:14]
output io_commit_uops_2_iw_p2_poisoned, // @[rob.scala:216:14]
output io_commit_uops_2_is_br, // @[rob.scala:216:14]
output io_commit_uops_2_is_jalr, // @[rob.scala:216:14]
output io_commit_uops_2_is_jal, // @[rob.scala:216:14]
output io_commit_uops_2_is_sfb, // @[rob.scala:216:14]
output [15:0] io_commit_uops_2_br_mask, // @[rob.scala:216:14]
output [3:0] io_commit_uops_2_br_tag, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_ftq_idx, // @[rob.scala:216:14]
output io_commit_uops_2_edge_inst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_2_pc_lob, // @[rob.scala:216:14]
output io_commit_uops_2_taken, // @[rob.scala:216:14]
output [19:0] io_commit_uops_2_imm_packed, // @[rob.scala:216:14]
output [11:0] io_commit_uops_2_csr_addr, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_rob_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_ldq_idx, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_stq_idx, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_rxq_idx, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_pdst, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_prs1, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_prs2, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_prs3, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_ppred, // @[rob.scala:216:14]
output io_commit_uops_2_prs1_busy, // @[rob.scala:216:14]
output io_commit_uops_2_prs2_busy, // @[rob.scala:216:14]
output io_commit_uops_2_prs3_busy, // @[rob.scala:216:14]
output io_commit_uops_2_ppred_busy, // @[rob.scala:216:14]
output [6:0] io_commit_uops_2_stale_pdst, // @[rob.scala:216:14]
output io_commit_uops_2_exception, // @[rob.scala:216:14]
output [63:0] io_commit_uops_2_exc_cause, // @[rob.scala:216:14]
output io_commit_uops_2_bypassable, // @[rob.scala:216:14]
output [4:0] io_commit_uops_2_mem_cmd, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_mem_size, // @[rob.scala:216:14]
output io_commit_uops_2_mem_signed, // @[rob.scala:216:14]
output io_commit_uops_2_is_fence, // @[rob.scala:216:14]
output io_commit_uops_2_is_fencei, // @[rob.scala:216:14]
output io_commit_uops_2_is_amo, // @[rob.scala:216:14]
output io_commit_uops_2_uses_ldq, // @[rob.scala:216:14]
output io_commit_uops_2_uses_stq, // @[rob.scala:216:14]
output io_commit_uops_2_is_sys_pc2epc, // @[rob.scala:216:14]
output io_commit_uops_2_is_unique, // @[rob.scala:216:14]
output io_commit_uops_2_flush_on_commit, // @[rob.scala:216:14]
output io_commit_uops_2_ldst_is_rs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_2_ldst, // @[rob.scala:216:14]
output [5:0] io_commit_uops_2_lrs1, // @[rob.scala:216:14]
output [5:0] io_commit_uops_2_lrs2, // @[rob.scala:216:14]
output [5:0] io_commit_uops_2_lrs3, // @[rob.scala:216:14]
output io_commit_uops_2_ldst_val, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_dst_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_lrs1_rtype, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_lrs2_rtype, // @[rob.scala:216:14]
output io_commit_uops_2_frs3_en, // @[rob.scala:216:14]
output io_commit_uops_2_fp_val, // @[rob.scala:216:14]
output io_commit_uops_2_fp_single, // @[rob.scala:216:14]
output io_commit_uops_2_xcpt_pf_if, // @[rob.scala:216:14]
output io_commit_uops_2_xcpt_ae_if, // @[rob.scala:216:14]
output io_commit_uops_2_xcpt_ma_if, // @[rob.scala:216:14]
output io_commit_uops_2_bp_debug_if, // @[rob.scala:216:14]
output io_commit_uops_2_bp_xcpt_if, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_debug_fsrc, // @[rob.scala:216:14]
output [1:0] io_commit_uops_2_debug_tsrc, // @[rob.scala:216:14]
output io_commit_fflags_valid, // @[rob.scala:216:14]
output [4:0] io_commit_fflags_bits, // @[rob.scala:216:14]
output [31:0] io_commit_debug_insts_0, // @[rob.scala:216:14]
output [31:0] io_commit_debug_insts_1, // @[rob.scala:216:14]
output [31:0] io_commit_debug_insts_2, // @[rob.scala:216:14]
output io_commit_rbk_valids_0, // @[rob.scala:216:14]
output io_commit_rbk_valids_1, // @[rob.scala:216:14]
output io_commit_rbk_valids_2, // @[rob.scala:216:14]
output io_commit_rollback, // @[rob.scala:216:14]
output [63:0] io_commit_debug_wdata_0, // @[rob.scala:216:14]
output [63:0] io_commit_debug_wdata_1, // @[rob.scala:216:14]
output [63:0] io_commit_debug_wdata_2, // @[rob.scala:216:14]
output io_com_load_is_at_rob_head, // @[rob.scala:216:14]
output io_com_xcpt_valid, // @[rob.scala:216:14]
output [4:0] io_com_xcpt_bits_ftq_idx, // @[rob.scala:216:14]
output io_com_xcpt_bits_edge_inst, // @[rob.scala:216:14]
output [5:0] io_com_xcpt_bits_pc_lob, // @[rob.scala:216:14]
output [63:0] io_com_xcpt_bits_cause, // @[rob.scala:216:14]
output [63:0] io_com_xcpt_bits_badvaddr, // @[rob.scala:216:14]
input io_csr_stall, // @[rob.scala:216:14]
output io_flush_valid, // @[rob.scala:216:14]
output [4:0] io_flush_bits_ftq_idx, // @[rob.scala:216:14]
output io_flush_bits_edge_inst, // @[rob.scala:216:14]
output io_flush_bits_is_rvc, // @[rob.scala:216:14]
output [5:0] io_flush_bits_pc_lob, // @[rob.scala:216:14]
output [2:0] io_flush_bits_flush_typ, // @[rob.scala:216:14]
output io_empty, // @[rob.scala:216:14]
output io_ready, // @[rob.scala:216:14]
output io_flush_frontend, // @[rob.scala:216:14]
input [63:0] io_debug_tsc // @[rob.scala:216:14]
);
wire [95:0] _rob_debug_inst_mem_R0_data; // @[rob.scala:296:41]
wire io_enq_valids_0_0 = io_enq_valids_0; // @[rob.scala:211:7]
wire io_enq_valids_1_0 = io_enq_valids_1; // @[rob.scala:211:7]
wire io_enq_valids_2_0 = io_enq_valids_2; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_uopc_0 = io_enq_uops_0_uopc; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_0_inst_0 = io_enq_uops_0_inst; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_0_debug_inst_0 = io_enq_uops_0_debug_inst; // @[rob.scala:211:7]
wire io_enq_uops_0_is_rvc_0 = io_enq_uops_0_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_enq_uops_0_debug_pc_0 = io_enq_uops_0_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_iq_type_0 = io_enq_uops_0_iq_type; // @[rob.scala:211:7]
wire [9:0] io_enq_uops_0_fu_code_0 = io_enq_uops_0_fu_code; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_0_ctrl_br_type_0 = io_enq_uops_0_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_ctrl_op1_sel_0 = io_enq_uops_0_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_op2_sel_0 = io_enq_uops_0_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_imm_sel_0 = io_enq_uops_0_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_ctrl_op_fcn_0 = io_enq_uops_0_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_fcn_dw_0 = io_enq_uops_0_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_0_ctrl_csr_cmd_0 = io_enq_uops_0_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_load_0 = io_enq_uops_0_ctrl_is_load; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_sta_0 = io_enq_uops_0_ctrl_is_sta; // @[rob.scala:211:7]
wire io_enq_uops_0_ctrl_is_std_0 = io_enq_uops_0_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_iw_state_0 = io_enq_uops_0_iw_state; // @[rob.scala:211:7]
wire io_enq_uops_0_iw_p1_poisoned_0 = io_enq_uops_0_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_0_iw_p2_poisoned_0 = io_enq_uops_0_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_0_is_br_0 = io_enq_uops_0_is_br; // @[rob.scala:211:7]
wire io_enq_uops_0_is_jalr_0 = io_enq_uops_0_is_jalr; // @[rob.scala:211:7]
wire io_enq_uops_0_is_jal_0 = io_enq_uops_0_is_jal; // @[rob.scala:211:7]
wire io_enq_uops_0_is_sfb_0 = io_enq_uops_0_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_enq_uops_0_br_mask_0 = io_enq_uops_0_br_mask; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_0_br_tag_0 = io_enq_uops_0_br_tag; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_ftq_idx_0 = io_enq_uops_0_ftq_idx; // @[rob.scala:211:7]
wire io_enq_uops_0_edge_inst_0 = io_enq_uops_0_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_pc_lob_0 = io_enq_uops_0_pc_lob; // @[rob.scala:211:7]
wire io_enq_uops_0_taken_0 = io_enq_uops_0_taken; // @[rob.scala:211:7]
wire [19:0] io_enq_uops_0_imm_packed_0 = io_enq_uops_0_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_enq_uops_0_csr_addr_0 = io_enq_uops_0_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_rob_idx_0 = io_enq_uops_0_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_ldq_idx_0 = io_enq_uops_0_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_stq_idx_0 = io_enq_uops_0_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_rxq_idx_0 = io_enq_uops_0_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_pdst_0 = io_enq_uops_0_pdst; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_prs1_0 = io_enq_uops_0_prs1; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_prs2_0 = io_enq_uops_0_prs2; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_prs3_0 = io_enq_uops_0_prs3; // @[rob.scala:211:7]
wire io_enq_uops_0_prs1_busy_0 = io_enq_uops_0_prs1_busy; // @[rob.scala:211:7]
wire io_enq_uops_0_prs2_busy_0 = io_enq_uops_0_prs2_busy; // @[rob.scala:211:7]
wire io_enq_uops_0_prs3_busy_0 = io_enq_uops_0_prs3_busy; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_0_stale_pdst_0 = io_enq_uops_0_stale_pdst; // @[rob.scala:211:7]
wire io_enq_uops_0_exception_0 = io_enq_uops_0_exception; // @[rob.scala:211:7]
wire [63:0] io_enq_uops_0_exc_cause_0 = io_enq_uops_0_exc_cause; // @[rob.scala:211:7]
wire io_enq_uops_0_bypassable_0 = io_enq_uops_0_bypassable; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_0_mem_cmd_0 = io_enq_uops_0_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_mem_size_0 = io_enq_uops_0_mem_size; // @[rob.scala:211:7]
wire io_enq_uops_0_mem_signed_0 = io_enq_uops_0_mem_signed; // @[rob.scala:211:7]
wire io_enq_uops_0_is_fence_0 = io_enq_uops_0_is_fence; // @[rob.scala:211:7]
wire io_enq_uops_0_is_fencei_0 = io_enq_uops_0_is_fencei; // @[rob.scala:211:7]
wire io_enq_uops_0_is_amo_0 = io_enq_uops_0_is_amo; // @[rob.scala:211:7]
wire io_enq_uops_0_uses_ldq_0 = io_enq_uops_0_uses_ldq; // @[rob.scala:211:7]
wire io_enq_uops_0_uses_stq_0 = io_enq_uops_0_uses_stq; // @[rob.scala:211:7]
wire io_enq_uops_0_is_sys_pc2epc_0 = io_enq_uops_0_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_enq_uops_0_is_unique_0 = io_enq_uops_0_is_unique; // @[rob.scala:211:7]
wire io_enq_uops_0_flush_on_commit_0 = io_enq_uops_0_flush_on_commit; // @[rob.scala:211:7]
wire io_enq_uops_0_ldst_is_rs1_0 = io_enq_uops_0_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_ldst_0 = io_enq_uops_0_ldst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs1_0 = io_enq_uops_0_lrs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs2_0 = io_enq_uops_0_lrs2; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_0_lrs3_0 = io_enq_uops_0_lrs3; // @[rob.scala:211:7]
wire io_enq_uops_0_ldst_val_0 = io_enq_uops_0_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_dst_rtype_0 = io_enq_uops_0_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_lrs1_rtype_0 = io_enq_uops_0_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_lrs2_rtype_0 = io_enq_uops_0_lrs2_rtype; // @[rob.scala:211:7]
wire io_enq_uops_0_frs3_en_0 = io_enq_uops_0_frs3_en; // @[rob.scala:211:7]
wire io_enq_uops_0_fp_val_0 = io_enq_uops_0_fp_val; // @[rob.scala:211:7]
wire io_enq_uops_0_fp_single_0 = io_enq_uops_0_fp_single; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_pf_if_0 = io_enq_uops_0_xcpt_pf_if; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_ae_if_0 = io_enq_uops_0_xcpt_ae_if; // @[rob.scala:211:7]
wire io_enq_uops_0_xcpt_ma_if_0 = io_enq_uops_0_xcpt_ma_if; // @[rob.scala:211:7]
wire io_enq_uops_0_bp_debug_if_0 = io_enq_uops_0_bp_debug_if; // @[rob.scala:211:7]
wire io_enq_uops_0_bp_xcpt_if_0 = io_enq_uops_0_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_debug_fsrc_0 = io_enq_uops_0_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_0_debug_tsrc_0 = io_enq_uops_0_debug_tsrc; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_uopc_0 = io_enq_uops_1_uopc; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_1_inst_0 = io_enq_uops_1_inst; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_1_debug_inst_0 = io_enq_uops_1_debug_inst; // @[rob.scala:211:7]
wire io_enq_uops_1_is_rvc_0 = io_enq_uops_1_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_enq_uops_1_debug_pc_0 = io_enq_uops_1_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_1_iq_type_0 = io_enq_uops_1_iq_type; // @[rob.scala:211:7]
wire [9:0] io_enq_uops_1_fu_code_0 = io_enq_uops_1_fu_code; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_1_ctrl_br_type_0 = io_enq_uops_1_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_ctrl_op1_sel_0 = io_enq_uops_1_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_1_ctrl_op2_sel_0 = io_enq_uops_1_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_1_ctrl_imm_sel_0 = io_enq_uops_1_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_ctrl_op_fcn_0 = io_enq_uops_1_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_enq_uops_1_ctrl_fcn_dw_0 = io_enq_uops_1_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_1_ctrl_csr_cmd_0 = io_enq_uops_1_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_enq_uops_1_ctrl_is_load_0 = io_enq_uops_1_ctrl_is_load; // @[rob.scala:211:7]
wire io_enq_uops_1_ctrl_is_sta_0 = io_enq_uops_1_ctrl_is_sta; // @[rob.scala:211:7]
wire io_enq_uops_1_ctrl_is_std_0 = io_enq_uops_1_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_iw_state_0 = io_enq_uops_1_iw_state; // @[rob.scala:211:7]
wire io_enq_uops_1_iw_p1_poisoned_0 = io_enq_uops_1_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_1_iw_p2_poisoned_0 = io_enq_uops_1_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_1_is_br_0 = io_enq_uops_1_is_br; // @[rob.scala:211:7]
wire io_enq_uops_1_is_jalr_0 = io_enq_uops_1_is_jalr; // @[rob.scala:211:7]
wire io_enq_uops_1_is_jal_0 = io_enq_uops_1_is_jal; // @[rob.scala:211:7]
wire io_enq_uops_1_is_sfb_0 = io_enq_uops_1_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_enq_uops_1_br_mask_0 = io_enq_uops_1_br_mask; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_1_br_tag_0 = io_enq_uops_1_br_tag; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_ftq_idx_0 = io_enq_uops_1_ftq_idx; // @[rob.scala:211:7]
wire io_enq_uops_1_edge_inst_0 = io_enq_uops_1_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_1_pc_lob_0 = io_enq_uops_1_pc_lob; // @[rob.scala:211:7]
wire io_enq_uops_1_taken_0 = io_enq_uops_1_taken; // @[rob.scala:211:7]
wire [19:0] io_enq_uops_1_imm_packed_0 = io_enq_uops_1_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_enq_uops_1_csr_addr_0 = io_enq_uops_1_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_rob_idx_0 = io_enq_uops_1_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_ldq_idx_0 = io_enq_uops_1_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_stq_idx_0 = io_enq_uops_1_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_rxq_idx_0 = io_enq_uops_1_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_pdst_0 = io_enq_uops_1_pdst; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_prs1_0 = io_enq_uops_1_prs1; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_prs2_0 = io_enq_uops_1_prs2; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_prs3_0 = io_enq_uops_1_prs3; // @[rob.scala:211:7]
wire io_enq_uops_1_prs1_busy_0 = io_enq_uops_1_prs1_busy; // @[rob.scala:211:7]
wire io_enq_uops_1_prs2_busy_0 = io_enq_uops_1_prs2_busy; // @[rob.scala:211:7]
wire io_enq_uops_1_prs3_busy_0 = io_enq_uops_1_prs3_busy; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_1_stale_pdst_0 = io_enq_uops_1_stale_pdst; // @[rob.scala:211:7]
wire io_enq_uops_1_exception_0 = io_enq_uops_1_exception; // @[rob.scala:211:7]
wire [63:0] io_enq_uops_1_exc_cause_0 = io_enq_uops_1_exc_cause; // @[rob.scala:211:7]
wire io_enq_uops_1_bypassable_0 = io_enq_uops_1_bypassable; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_mem_cmd_0 = io_enq_uops_1_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_mem_size_0 = io_enq_uops_1_mem_size; // @[rob.scala:211:7]
wire io_enq_uops_1_mem_signed_0 = io_enq_uops_1_mem_signed; // @[rob.scala:211:7]
wire io_enq_uops_1_is_fence_0 = io_enq_uops_1_is_fence; // @[rob.scala:211:7]
wire io_enq_uops_1_is_fencei_0 = io_enq_uops_1_is_fencei; // @[rob.scala:211:7]
wire io_enq_uops_1_is_amo_0 = io_enq_uops_1_is_amo; // @[rob.scala:211:7]
wire io_enq_uops_1_uses_ldq_0 = io_enq_uops_1_uses_ldq; // @[rob.scala:211:7]
wire io_enq_uops_1_uses_stq_0 = io_enq_uops_1_uses_stq; // @[rob.scala:211:7]
wire io_enq_uops_1_is_sys_pc2epc_0 = io_enq_uops_1_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_enq_uops_1_is_unique_0 = io_enq_uops_1_is_unique; // @[rob.scala:211:7]
wire io_enq_uops_1_flush_on_commit_0 = io_enq_uops_1_flush_on_commit; // @[rob.scala:211:7]
wire io_enq_uops_1_ldst_is_rs1_0 = io_enq_uops_1_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_1_ldst_0 = io_enq_uops_1_ldst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_1_lrs1_0 = io_enq_uops_1_lrs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_1_lrs2_0 = io_enq_uops_1_lrs2; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_1_lrs3_0 = io_enq_uops_1_lrs3; // @[rob.scala:211:7]
wire io_enq_uops_1_ldst_val_0 = io_enq_uops_1_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_dst_rtype_0 = io_enq_uops_1_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_lrs1_rtype_0 = io_enq_uops_1_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_lrs2_rtype_0 = io_enq_uops_1_lrs2_rtype; // @[rob.scala:211:7]
wire io_enq_uops_1_frs3_en_0 = io_enq_uops_1_frs3_en; // @[rob.scala:211:7]
wire io_enq_uops_1_fp_val_0 = io_enq_uops_1_fp_val; // @[rob.scala:211:7]
wire io_enq_uops_1_fp_single_0 = io_enq_uops_1_fp_single; // @[rob.scala:211:7]
wire io_enq_uops_1_xcpt_pf_if_0 = io_enq_uops_1_xcpt_pf_if; // @[rob.scala:211:7]
wire io_enq_uops_1_xcpt_ae_if_0 = io_enq_uops_1_xcpt_ae_if; // @[rob.scala:211:7]
wire io_enq_uops_1_xcpt_ma_if_0 = io_enq_uops_1_xcpt_ma_if; // @[rob.scala:211:7]
wire io_enq_uops_1_bp_debug_if_0 = io_enq_uops_1_bp_debug_if; // @[rob.scala:211:7]
wire io_enq_uops_1_bp_xcpt_if_0 = io_enq_uops_1_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_debug_fsrc_0 = io_enq_uops_1_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_1_debug_tsrc_0 = io_enq_uops_1_debug_tsrc; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_uopc_0 = io_enq_uops_2_uopc; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_2_inst_0 = io_enq_uops_2_inst; // @[rob.scala:211:7]
wire [31:0] io_enq_uops_2_debug_inst_0 = io_enq_uops_2_debug_inst; // @[rob.scala:211:7]
wire io_enq_uops_2_is_rvc_0 = io_enq_uops_2_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_enq_uops_2_debug_pc_0 = io_enq_uops_2_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_2_iq_type_0 = io_enq_uops_2_iq_type; // @[rob.scala:211:7]
wire [9:0] io_enq_uops_2_fu_code_0 = io_enq_uops_2_fu_code; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_2_ctrl_br_type_0 = io_enq_uops_2_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_ctrl_op1_sel_0 = io_enq_uops_2_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_2_ctrl_op2_sel_0 = io_enq_uops_2_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_2_ctrl_imm_sel_0 = io_enq_uops_2_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_ctrl_op_fcn_0 = io_enq_uops_2_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_enq_uops_2_ctrl_fcn_dw_0 = io_enq_uops_2_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_enq_uops_2_ctrl_csr_cmd_0 = io_enq_uops_2_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_enq_uops_2_ctrl_is_load_0 = io_enq_uops_2_ctrl_is_load; // @[rob.scala:211:7]
wire io_enq_uops_2_ctrl_is_sta_0 = io_enq_uops_2_ctrl_is_sta; // @[rob.scala:211:7]
wire io_enq_uops_2_ctrl_is_std_0 = io_enq_uops_2_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_iw_state_0 = io_enq_uops_2_iw_state; // @[rob.scala:211:7]
wire io_enq_uops_2_iw_p1_poisoned_0 = io_enq_uops_2_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_2_iw_p2_poisoned_0 = io_enq_uops_2_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_enq_uops_2_is_br_0 = io_enq_uops_2_is_br; // @[rob.scala:211:7]
wire io_enq_uops_2_is_jalr_0 = io_enq_uops_2_is_jalr; // @[rob.scala:211:7]
wire io_enq_uops_2_is_jal_0 = io_enq_uops_2_is_jal; // @[rob.scala:211:7]
wire io_enq_uops_2_is_sfb_0 = io_enq_uops_2_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_enq_uops_2_br_mask_0 = io_enq_uops_2_br_mask; // @[rob.scala:211:7]
wire [3:0] io_enq_uops_2_br_tag_0 = io_enq_uops_2_br_tag; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_ftq_idx_0 = io_enq_uops_2_ftq_idx; // @[rob.scala:211:7]
wire io_enq_uops_2_edge_inst_0 = io_enq_uops_2_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_2_pc_lob_0 = io_enq_uops_2_pc_lob; // @[rob.scala:211:7]
wire io_enq_uops_2_taken_0 = io_enq_uops_2_taken; // @[rob.scala:211:7]
wire [19:0] io_enq_uops_2_imm_packed_0 = io_enq_uops_2_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_enq_uops_2_csr_addr_0 = io_enq_uops_2_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_rob_idx_0 = io_enq_uops_2_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_ldq_idx_0 = io_enq_uops_2_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_stq_idx_0 = io_enq_uops_2_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_rxq_idx_0 = io_enq_uops_2_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_pdst_0 = io_enq_uops_2_pdst; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_prs1_0 = io_enq_uops_2_prs1; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_prs2_0 = io_enq_uops_2_prs2; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_prs3_0 = io_enq_uops_2_prs3; // @[rob.scala:211:7]
wire io_enq_uops_2_prs1_busy_0 = io_enq_uops_2_prs1_busy; // @[rob.scala:211:7]
wire io_enq_uops_2_prs2_busy_0 = io_enq_uops_2_prs2_busy; // @[rob.scala:211:7]
wire io_enq_uops_2_prs3_busy_0 = io_enq_uops_2_prs3_busy; // @[rob.scala:211:7]
wire [6:0] io_enq_uops_2_stale_pdst_0 = io_enq_uops_2_stale_pdst; // @[rob.scala:211:7]
wire io_enq_uops_2_exception_0 = io_enq_uops_2_exception; // @[rob.scala:211:7]
wire [63:0] io_enq_uops_2_exc_cause_0 = io_enq_uops_2_exc_cause; // @[rob.scala:211:7]
wire io_enq_uops_2_bypassable_0 = io_enq_uops_2_bypassable; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_mem_cmd_0 = io_enq_uops_2_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_mem_size_0 = io_enq_uops_2_mem_size; // @[rob.scala:211:7]
wire io_enq_uops_2_mem_signed_0 = io_enq_uops_2_mem_signed; // @[rob.scala:211:7]
wire io_enq_uops_2_is_fence_0 = io_enq_uops_2_is_fence; // @[rob.scala:211:7]
wire io_enq_uops_2_is_fencei_0 = io_enq_uops_2_is_fencei; // @[rob.scala:211:7]
wire io_enq_uops_2_is_amo_0 = io_enq_uops_2_is_amo; // @[rob.scala:211:7]
wire io_enq_uops_2_uses_ldq_0 = io_enq_uops_2_uses_ldq; // @[rob.scala:211:7]
wire io_enq_uops_2_uses_stq_0 = io_enq_uops_2_uses_stq; // @[rob.scala:211:7]
wire io_enq_uops_2_is_sys_pc2epc_0 = io_enq_uops_2_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_enq_uops_2_is_unique_0 = io_enq_uops_2_is_unique; // @[rob.scala:211:7]
wire io_enq_uops_2_flush_on_commit_0 = io_enq_uops_2_flush_on_commit; // @[rob.scala:211:7]
wire io_enq_uops_2_ldst_is_rs1_0 = io_enq_uops_2_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_2_ldst_0 = io_enq_uops_2_ldst; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_2_lrs1_0 = io_enq_uops_2_lrs1; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_2_lrs2_0 = io_enq_uops_2_lrs2; // @[rob.scala:211:7]
wire [5:0] io_enq_uops_2_lrs3_0 = io_enq_uops_2_lrs3; // @[rob.scala:211:7]
wire io_enq_uops_2_ldst_val_0 = io_enq_uops_2_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_dst_rtype_0 = io_enq_uops_2_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_lrs1_rtype_0 = io_enq_uops_2_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_lrs2_rtype_0 = io_enq_uops_2_lrs2_rtype; // @[rob.scala:211:7]
wire io_enq_uops_2_frs3_en_0 = io_enq_uops_2_frs3_en; // @[rob.scala:211:7]
wire io_enq_uops_2_fp_val_0 = io_enq_uops_2_fp_val; // @[rob.scala:211:7]
wire io_enq_uops_2_fp_single_0 = io_enq_uops_2_fp_single; // @[rob.scala:211:7]
wire io_enq_uops_2_xcpt_pf_if_0 = io_enq_uops_2_xcpt_pf_if; // @[rob.scala:211:7]
wire io_enq_uops_2_xcpt_ae_if_0 = io_enq_uops_2_xcpt_ae_if; // @[rob.scala:211:7]
wire io_enq_uops_2_xcpt_ma_if_0 = io_enq_uops_2_xcpt_ma_if; // @[rob.scala:211:7]
wire io_enq_uops_2_bp_debug_if_0 = io_enq_uops_2_bp_debug_if; // @[rob.scala:211:7]
wire io_enq_uops_2_bp_xcpt_if_0 = io_enq_uops_2_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_debug_fsrc_0 = io_enq_uops_2_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_enq_uops_2_debug_tsrc_0 = io_enq_uops_2_debug_tsrc; // @[rob.scala:211:7]
wire io_enq_partial_stall_0 = io_enq_partial_stall; // @[rob.scala:211:7]
wire [39:0] io_xcpt_fetch_pc_0 = io_xcpt_fetch_pc; // @[rob.scala:211:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rob.scala:211:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rob.scala:211:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rob.scala:211:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rob.scala:211:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rob.scala:211:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rob.scala:211:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rob.scala:211:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rob.scala:211:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rob.scala:211:7]
wire io_wb_resps_0_valid_0 = io_wb_resps_0_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_uopc_0 = io_wb_resps_0_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_uop_inst_0 = io_wb_resps_0_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_uop_debug_inst_0 = io_wb_resps_0_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_rvc_0 = io_wb_resps_0_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_0_bits_uop_debug_pc_0 = io_wb_resps_0_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_iq_type_0 = io_wb_resps_0_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_0_bits_uop_fu_code_0 = io_wb_resps_0_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_iw_state_0 = io_wb_resps_0_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_br_0 = io_wb_resps_0_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_jalr_0 = io_wb_resps_0_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_jal_0 = io_wb_resps_0_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_sfb_0 = io_wb_resps_0_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_0_bits_uop_br_mask_0 = io_wb_resps_0_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_uop_br_tag_0 = io_wb_resps_0_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_edge_inst_0 = io_wb_resps_0_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_pc_lob_0 = io_wb_resps_0_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_taken_0 = io_wb_resps_0_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_0_bits_uop_imm_packed_0 = io_wb_resps_0_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_0_bits_uop_csr_addr_0 = io_wb_resps_0_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_rob_idx_0 = io_wb_resps_0_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_stq_idx_0 = io_wb_resps_0_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_pdst_0 = io_wb_resps_0_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_prs1_0 = io_wb_resps_0_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_prs2_0 = io_wb_resps_0_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_prs3_0 = io_wb_resps_0_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_ppred_0 = io_wb_resps_0_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_exception_0 = io_wb_resps_0_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_0_bits_uop_exc_cause_0 = io_wb_resps_0_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bypassable_0 = io_wb_resps_0_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_mem_size_0 = io_wb_resps_0_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_mem_signed_0 = io_wb_resps_0_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_fence_0 = io_wb_resps_0_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_fencei_0 = io_wb_resps_0_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_amo_0 = io_wb_resps_0_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_uses_stq_0 = io_wb_resps_0_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_is_unique_0 = io_wb_resps_0_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_ldst_0 = io_wb_resps_0_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs1_0 = io_wb_resps_0_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs2_0 = io_wb_resps_0_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs3_0 = io_wb_resps_0_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_ldst_val_0 = io_wb_resps_0_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_frs3_en_0 = io_wb_resps_0_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_fp_val_0 = io_wb_resps_0_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_fp_single_0 = io_wb_resps_0_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_0_bits_data_0 = io_wb_resps_0_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_predicated_0 = io_wb_resps_0_bits_predicated; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_valid_0 = io_wb_resps_0_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_uopc_0 = io_wb_resps_0_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_0_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_0_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_0_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_0_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_0_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_0_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_br_0 = io_wb_resps_0_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_0_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_0_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_0_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_0_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_0_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_0_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_0_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_taken_0 = io_wb_resps_0_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_0_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_0_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_0_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_0_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs1_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs2_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_prs3_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_ppred_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_0_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_exception_0 = io_wb_resps_0_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_0_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_0_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_0_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_0_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_0_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_0_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_0_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_0_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_ldst_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_0_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_0_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_0_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_0_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_flags_0 = io_wb_resps_0_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_wb_resps_1_valid_0 = io_wb_resps_1_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_uopc_0 = io_wb_resps_1_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_uop_inst_0 = io_wb_resps_1_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_uop_debug_inst_0 = io_wb_resps_1_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_rvc_0 = io_wb_resps_1_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_1_bits_uop_debug_pc_0 = io_wb_resps_1_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_iq_type_0 = io_wb_resps_1_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_1_bits_uop_fu_code_0 = io_wb_resps_1_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_uop_ctrl_br_type_0 = io_wb_resps_1_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_ctrl_op1_sel_0 = io_wb_resps_1_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_op2_sel_0 = io_wb_resps_1_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_imm_sel_0 = io_wb_resps_1_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_ctrl_op_fcn_0 = io_wb_resps_1_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_1_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_1_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_load_0 = io_wb_resps_1_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_sta_0 = io_wb_resps_1_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ctrl_is_std_0 = io_wb_resps_1_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_iw_state_0 = io_wb_resps_1_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_iw_p1_poisoned_0 = io_wb_resps_1_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_iw_p2_poisoned_0 = io_wb_resps_1_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_br_0 = io_wb_resps_1_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_jalr_0 = io_wb_resps_1_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_jal_0 = io_wb_resps_1_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_sfb_0 = io_wb_resps_1_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_1_bits_uop_br_mask_0 = io_wb_resps_1_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_uop_br_tag_0 = io_wb_resps_1_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_ftq_idx_0 = io_wb_resps_1_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_edge_inst_0 = io_wb_resps_1_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_pc_lob_0 = io_wb_resps_1_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_taken_0 = io_wb_resps_1_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_1_bits_uop_imm_packed_0 = io_wb_resps_1_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_1_bits_uop_csr_addr_0 = io_wb_resps_1_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_rob_idx_0 = io_wb_resps_1_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_ldq_idx_0 = io_wb_resps_1_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_stq_idx_0 = io_wb_resps_1_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_rxq_idx_0 = io_wb_resps_1_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_pdst_0 = io_wb_resps_1_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_prs1_0 = io_wb_resps_1_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_prs2_0 = io_wb_resps_1_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_prs3_0 = io_wb_resps_1_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_ppred_0 = io_wb_resps_1_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs1_busy_0 = io_wb_resps_1_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs2_busy_0 = io_wb_resps_1_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_prs3_busy_0 = io_wb_resps_1_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ppred_busy_0 = io_wb_resps_1_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_uop_stale_pdst_0 = io_wb_resps_1_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_exception_0 = io_wb_resps_1_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_1_bits_uop_exc_cause_0 = io_wb_resps_1_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bypassable_0 = io_wb_resps_1_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_uop_mem_cmd_0 = io_wb_resps_1_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_mem_size_0 = io_wb_resps_1_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_mem_signed_0 = io_wb_resps_1_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_fence_0 = io_wb_resps_1_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_fencei_0 = io_wb_resps_1_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_amo_0 = io_wb_resps_1_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_uses_ldq_0 = io_wb_resps_1_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_uses_stq_0 = io_wb_resps_1_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_sys_pc2epc_0 = io_wb_resps_1_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_is_unique_0 = io_wb_resps_1_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_flush_on_commit_0 = io_wb_resps_1_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ldst_is_rs1_0 = io_wb_resps_1_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_ldst_0 = io_wb_resps_1_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs1_0 = io_wb_resps_1_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs2_0 = io_wb_resps_1_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs3_0 = io_wb_resps_1_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_ldst_val_0 = io_wb_resps_1_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_dst_rtype_0 = io_wb_resps_1_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs1_rtype_0 = io_wb_resps_1_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs2_rtype_0 = io_wb_resps_1_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_frs3_en_0 = io_wb_resps_1_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_fp_val_0 = io_wb_resps_1_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_fp_single_0 = io_wb_resps_1_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_pf_if_0 = io_wb_resps_1_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_ae_if_0 = io_wb_resps_1_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_xcpt_ma_if_0 = io_wb_resps_1_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bp_debug_if_0 = io_wb_resps_1_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_uop_bp_xcpt_if_0 = io_wb_resps_1_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_debug_fsrc_0 = io_wb_resps_1_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_uop_debug_tsrc_0 = io_wb_resps_1_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_1_bits_data_0 = io_wb_resps_1_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_2_valid_0 = io_wb_resps_2_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_uopc_0 = io_wb_resps_2_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_uop_inst_0 = io_wb_resps_2_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_uop_debug_inst_0 = io_wb_resps_2_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_rvc_0 = io_wb_resps_2_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_2_bits_uop_debug_pc_0 = io_wb_resps_2_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_iq_type_0 = io_wb_resps_2_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_2_bits_uop_fu_code_0 = io_wb_resps_2_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_uop_ctrl_br_type_0 = io_wb_resps_2_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_ctrl_op1_sel_0 = io_wb_resps_2_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_op2_sel_0 = io_wb_resps_2_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_imm_sel_0 = io_wb_resps_2_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_ctrl_op_fcn_0 = io_wb_resps_2_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_2_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_2_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_load_0 = io_wb_resps_2_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_sta_0 = io_wb_resps_2_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ctrl_is_std_0 = io_wb_resps_2_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_iw_state_0 = io_wb_resps_2_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_iw_p1_poisoned_0 = io_wb_resps_2_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_iw_p2_poisoned_0 = io_wb_resps_2_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_br_0 = io_wb_resps_2_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_jalr_0 = io_wb_resps_2_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_jal_0 = io_wb_resps_2_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_sfb_0 = io_wb_resps_2_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_2_bits_uop_br_mask_0 = io_wb_resps_2_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_uop_br_tag_0 = io_wb_resps_2_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_edge_inst_0 = io_wb_resps_2_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_pc_lob_0 = io_wb_resps_2_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_taken_0 = io_wb_resps_2_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_2_bits_uop_imm_packed_0 = io_wb_resps_2_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_2_bits_uop_csr_addr_0 = io_wb_resps_2_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_rob_idx_0 = io_wb_resps_2_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_stq_idx_0 = io_wb_resps_2_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_pdst_0 = io_wb_resps_2_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_prs1_0 = io_wb_resps_2_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_prs2_0 = io_wb_resps_2_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_prs3_0 = io_wb_resps_2_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_ppred_0 = io_wb_resps_2_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_exception_0 = io_wb_resps_2_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_2_bits_uop_exc_cause_0 = io_wb_resps_2_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bypassable_0 = io_wb_resps_2_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_mem_size_0 = io_wb_resps_2_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_mem_signed_0 = io_wb_resps_2_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_fence_0 = io_wb_resps_2_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_fencei_0 = io_wb_resps_2_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_amo_0 = io_wb_resps_2_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_uses_stq_0 = io_wb_resps_2_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_is_unique_0 = io_wb_resps_2_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_ldst_0 = io_wb_resps_2_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs1_0 = io_wb_resps_2_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs2_0 = io_wb_resps_2_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs3_0 = io_wb_resps_2_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_ldst_val_0 = io_wb_resps_2_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_frs3_en_0 = io_wb_resps_2_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_fp_val_0 = io_wb_resps_2_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_fp_single_0 = io_wb_resps_2_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_2_bits_data_0 = io_wb_resps_2_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_3_valid_0 = io_wb_resps_3_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_uopc_0 = io_wb_resps_3_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_uop_inst_0 = io_wb_resps_3_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_uop_debug_inst_0 = io_wb_resps_3_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_rvc_0 = io_wb_resps_3_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_3_bits_uop_debug_pc_0 = io_wb_resps_3_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_iq_type_0 = io_wb_resps_3_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_3_bits_uop_fu_code_0 = io_wb_resps_3_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_uop_ctrl_br_type_0 = io_wb_resps_3_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_ctrl_op1_sel_0 = io_wb_resps_3_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_op2_sel_0 = io_wb_resps_3_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_imm_sel_0 = io_wb_resps_3_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_ctrl_op_fcn_0 = io_wb_resps_3_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_3_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_3_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_load_0 = io_wb_resps_3_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_sta_0 = io_wb_resps_3_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ctrl_is_std_0 = io_wb_resps_3_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_iw_state_0 = io_wb_resps_3_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_iw_p1_poisoned_0 = io_wb_resps_3_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_iw_p2_poisoned_0 = io_wb_resps_3_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_br_0 = io_wb_resps_3_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_jalr_0 = io_wb_resps_3_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_jal_0 = io_wb_resps_3_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_sfb_0 = io_wb_resps_3_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_3_bits_uop_br_mask_0 = io_wb_resps_3_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_uop_br_tag_0 = io_wb_resps_3_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_edge_inst_0 = io_wb_resps_3_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_pc_lob_0 = io_wb_resps_3_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_taken_0 = io_wb_resps_3_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_3_bits_uop_imm_packed_0 = io_wb_resps_3_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_3_bits_uop_csr_addr_0 = io_wb_resps_3_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_rob_idx_0 = io_wb_resps_3_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_stq_idx_0 = io_wb_resps_3_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_pdst_0 = io_wb_resps_3_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_prs1_0 = io_wb_resps_3_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_prs2_0 = io_wb_resps_3_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_prs3_0 = io_wb_resps_3_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_ppred_0 = io_wb_resps_3_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_exception_0 = io_wb_resps_3_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_3_bits_uop_exc_cause_0 = io_wb_resps_3_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bypassable_0 = io_wb_resps_3_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_mem_size_0 = io_wb_resps_3_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_mem_signed_0 = io_wb_resps_3_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_fence_0 = io_wb_resps_3_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_fencei_0 = io_wb_resps_3_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_amo_0 = io_wb_resps_3_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_uses_stq_0 = io_wb_resps_3_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_is_unique_0 = io_wb_resps_3_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_ldst_0 = io_wb_resps_3_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs1_0 = io_wb_resps_3_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs2_0 = io_wb_resps_3_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs3_0 = io_wb_resps_3_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_ldst_val_0 = io_wb_resps_3_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_frs3_en_0 = io_wb_resps_3_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_fp_val_0 = io_wb_resps_3_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_fp_single_0 = io_wb_resps_3_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_3_bits_data_0 = io_wb_resps_3_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_4_valid_0 = io_wb_resps_4_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_uopc_0 = io_wb_resps_4_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_4_bits_uop_inst_0 = io_wb_resps_4_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_4_bits_uop_debug_inst_0 = io_wb_resps_4_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_rvc_0 = io_wb_resps_4_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_4_bits_uop_debug_pc_0 = io_wb_resps_4_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_uop_iq_type_0 = io_wb_resps_4_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_4_bits_uop_fu_code_0 = io_wb_resps_4_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_4_bits_uop_ctrl_br_type_0 = io_wb_resps_4_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_ctrl_op1_sel_0 = io_wb_resps_4_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_uop_ctrl_op2_sel_0 = io_wb_resps_4_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_uop_ctrl_imm_sel_0 = io_wb_resps_4_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_ctrl_op_fcn_0 = io_wb_resps_4_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_4_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_4_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ctrl_is_load_0 = io_wb_resps_4_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ctrl_is_sta_0 = io_wb_resps_4_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ctrl_is_std_0 = io_wb_resps_4_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_iw_state_0 = io_wb_resps_4_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_iw_p1_poisoned_0 = io_wb_resps_4_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_iw_p2_poisoned_0 = io_wb_resps_4_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_br_0 = io_wb_resps_4_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_jalr_0 = io_wb_resps_4_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_jal_0 = io_wb_resps_4_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_sfb_0 = io_wb_resps_4_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_4_bits_uop_br_mask_0 = io_wb_resps_4_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_4_bits_uop_br_tag_0 = io_wb_resps_4_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_ftq_idx_0 = io_wb_resps_4_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_edge_inst_0 = io_wb_resps_4_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_uop_pc_lob_0 = io_wb_resps_4_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_taken_0 = io_wb_resps_4_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_4_bits_uop_imm_packed_0 = io_wb_resps_4_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_4_bits_uop_csr_addr_0 = io_wb_resps_4_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_rob_idx_0 = io_wb_resps_4_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_ldq_idx_0 = io_wb_resps_4_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_stq_idx_0 = io_wb_resps_4_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_rxq_idx_0 = io_wb_resps_4_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_pdst_0 = io_wb_resps_4_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_prs1_0 = io_wb_resps_4_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_prs2_0 = io_wb_resps_4_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_prs3_0 = io_wb_resps_4_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_ppred_0 = io_wb_resps_4_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_prs1_busy_0 = io_wb_resps_4_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_prs2_busy_0 = io_wb_resps_4_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_prs3_busy_0 = io_wb_resps_4_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ppred_busy_0 = io_wb_resps_4_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_uop_stale_pdst_0 = io_wb_resps_4_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_exception_0 = io_wb_resps_4_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_4_bits_uop_exc_cause_0 = io_wb_resps_4_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_bypassable_0 = io_wb_resps_4_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_uop_mem_cmd_0 = io_wb_resps_4_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_mem_size_0 = io_wb_resps_4_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_mem_signed_0 = io_wb_resps_4_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_fence_0 = io_wb_resps_4_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_fencei_0 = io_wb_resps_4_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_amo_0 = io_wb_resps_4_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_uses_ldq_0 = io_wb_resps_4_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_uses_stq_0 = io_wb_resps_4_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_sys_pc2epc_0 = io_wb_resps_4_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_is_unique_0 = io_wb_resps_4_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_flush_on_commit_0 = io_wb_resps_4_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ldst_is_rs1_0 = io_wb_resps_4_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_uop_ldst_0 = io_wb_resps_4_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs1_0 = io_wb_resps_4_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs2_0 = io_wb_resps_4_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs3_0 = io_wb_resps_4_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_ldst_val_0 = io_wb_resps_4_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_dst_rtype_0 = io_wb_resps_4_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_lrs1_rtype_0 = io_wb_resps_4_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_lrs2_rtype_0 = io_wb_resps_4_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_frs3_en_0 = io_wb_resps_4_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_fp_val_0 = io_wb_resps_4_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_fp_single_0 = io_wb_resps_4_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_xcpt_pf_if_0 = io_wb_resps_4_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_xcpt_ae_if_0 = io_wb_resps_4_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_xcpt_ma_if_0 = io_wb_resps_4_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_bp_debug_if_0 = io_wb_resps_4_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_uop_bp_xcpt_if_0 = io_wb_resps_4_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_debug_fsrc_0 = io_wb_resps_4_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_uop_debug_tsrc_0 = io_wb_resps_4_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_4_bits_data_0 = io_wb_resps_4_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_predicated_0 = io_wb_resps_4_bits_predicated; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_valid_0 = io_wb_resps_4_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_uopc_0 = io_wb_resps_4_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_4_bits_fflags_bits_uop_inst_0 = io_wb_resps_4_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_4_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_4_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_4_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_4_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_4_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_4_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_4_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_4_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_4_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_4_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_4_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_4_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_4_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_br_0 = io_wb_resps_4_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_4_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_4_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_4_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_4_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_4_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_4_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_4_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_4_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_4_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_4_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_taken_0 = io_wb_resps_4_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_4_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_4_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_4_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_4_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_4_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_4_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_4_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_4_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_pdst_0 = io_wb_resps_4_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs1_0 = io_wb_resps_4_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs2_0 = io_wb_resps_4_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_prs3_0 = io_wb_resps_4_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_ppred_0 = io_wb_resps_4_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_4_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_4_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_4_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_4_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_4_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_4_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_exception_0 = io_wb_resps_4_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_4_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_4_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_4_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_4_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_4_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_4_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_4_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_4_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_4_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_4_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_4_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_4_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_4_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_4_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_4_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_fflags_bits_uop_ldst_0 = io_wb_resps_4_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_4_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_4_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_4_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_4_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_4_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_4_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_4_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_4_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_4_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_4_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_4_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_4_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_4_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_4_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_4_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_4_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_4_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_4_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_4_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_4_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_flags_0 = io_wb_resps_4_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_wb_resps_5_valid_0 = io_wb_resps_5_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_uopc_0 = io_wb_resps_5_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_5_bits_uop_inst_0 = io_wb_resps_5_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_5_bits_uop_debug_inst_0 = io_wb_resps_5_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_rvc_0 = io_wb_resps_5_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_5_bits_uop_debug_pc_0 = io_wb_resps_5_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_uop_iq_type_0 = io_wb_resps_5_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_5_bits_uop_fu_code_0 = io_wb_resps_5_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_5_bits_uop_ctrl_br_type_0 = io_wb_resps_5_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_ctrl_op1_sel_0 = io_wb_resps_5_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_uop_ctrl_op2_sel_0 = io_wb_resps_5_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_uop_ctrl_imm_sel_0 = io_wb_resps_5_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_ctrl_op_fcn_0 = io_wb_resps_5_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_5_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_5_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ctrl_is_load_0 = io_wb_resps_5_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ctrl_is_sta_0 = io_wb_resps_5_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ctrl_is_std_0 = io_wb_resps_5_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_iw_state_0 = io_wb_resps_5_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_iw_p1_poisoned_0 = io_wb_resps_5_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_iw_p2_poisoned_0 = io_wb_resps_5_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_br_0 = io_wb_resps_5_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_jalr_0 = io_wb_resps_5_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_jal_0 = io_wb_resps_5_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_sfb_0 = io_wb_resps_5_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_5_bits_uop_br_mask_0 = io_wb_resps_5_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_5_bits_uop_br_tag_0 = io_wb_resps_5_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_ftq_idx_0 = io_wb_resps_5_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_edge_inst_0 = io_wb_resps_5_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_uop_pc_lob_0 = io_wb_resps_5_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_taken_0 = io_wb_resps_5_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_5_bits_uop_imm_packed_0 = io_wb_resps_5_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_5_bits_uop_csr_addr_0 = io_wb_resps_5_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_rob_idx_0 = io_wb_resps_5_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_ldq_idx_0 = io_wb_resps_5_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_stq_idx_0 = io_wb_resps_5_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_rxq_idx_0 = io_wb_resps_5_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_pdst_0 = io_wb_resps_5_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_prs1_0 = io_wb_resps_5_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_prs2_0 = io_wb_resps_5_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_prs3_0 = io_wb_resps_5_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_ppred_0 = io_wb_resps_5_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_prs1_busy_0 = io_wb_resps_5_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_prs2_busy_0 = io_wb_resps_5_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_prs3_busy_0 = io_wb_resps_5_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ppred_busy_0 = io_wb_resps_5_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_uop_stale_pdst_0 = io_wb_resps_5_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_exception_0 = io_wb_resps_5_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_5_bits_uop_exc_cause_0 = io_wb_resps_5_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_bypassable_0 = io_wb_resps_5_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_uop_mem_cmd_0 = io_wb_resps_5_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_mem_size_0 = io_wb_resps_5_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_mem_signed_0 = io_wb_resps_5_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_fence_0 = io_wb_resps_5_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_fencei_0 = io_wb_resps_5_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_amo_0 = io_wb_resps_5_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_uses_ldq_0 = io_wb_resps_5_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_uses_stq_0 = io_wb_resps_5_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_sys_pc2epc_0 = io_wb_resps_5_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_is_unique_0 = io_wb_resps_5_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_flush_on_commit_0 = io_wb_resps_5_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ldst_is_rs1_0 = io_wb_resps_5_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_uop_ldst_0 = io_wb_resps_5_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs1_0 = io_wb_resps_5_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs2_0 = io_wb_resps_5_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs3_0 = io_wb_resps_5_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_ldst_val_0 = io_wb_resps_5_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_dst_rtype_0 = io_wb_resps_5_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_lrs1_rtype_0 = io_wb_resps_5_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_lrs2_rtype_0 = io_wb_resps_5_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_frs3_en_0 = io_wb_resps_5_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_fp_val_0 = io_wb_resps_5_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_fp_single_0 = io_wb_resps_5_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_xcpt_pf_if_0 = io_wb_resps_5_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_xcpt_ae_if_0 = io_wb_resps_5_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_xcpt_ma_if_0 = io_wb_resps_5_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_bp_debug_if_0 = io_wb_resps_5_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_uop_bp_xcpt_if_0 = io_wb_resps_5_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_debug_fsrc_0 = io_wb_resps_5_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_uop_debug_tsrc_0 = io_wb_resps_5_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [64:0] io_wb_resps_5_bits_data_0 = io_wb_resps_5_bits_data; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_valid_0 = io_wb_resps_5_bits_fflags_valid; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_uopc_0 = io_wb_resps_5_bits_fflags_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_5_bits_fflags_bits_uop_inst_0 = io_wb_resps_5_bits_fflags_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_5_bits_fflags_bits_uop_debug_inst_0 = io_wb_resps_5_bits_fflags_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_rvc_0 = io_wb_resps_5_bits_fflags_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_5_bits_fflags_bits_uop_debug_pc_0 = io_wb_resps_5_bits_fflags_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_fflags_bits_uop_iq_type_0 = io_wb_resps_5_bits_fflags_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_5_bits_fflags_bits_uop_fu_code_0 = io_wb_resps_5_bits_fflags_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_br_type_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_5_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_load_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_sta_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_std_0 = io_wb_resps_5_bits_fflags_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_iw_state_0 = io_wb_resps_5_bits_fflags_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_wb_resps_5_bits_fflags_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_wb_resps_5_bits_fflags_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_br_0 = io_wb_resps_5_bits_fflags_bits_uop_is_br; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_jalr_0 = io_wb_resps_5_bits_fflags_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_jal_0 = io_wb_resps_5_bits_fflags_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_sfb_0 = io_wb_resps_5_bits_fflags_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_5_bits_fflags_bits_uop_br_mask_0 = io_wb_resps_5_bits_fflags_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_5_bits_fflags_bits_uop_br_tag_0 = io_wb_resps_5_bits_fflags_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_ftq_idx_0 = io_wb_resps_5_bits_fflags_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_edge_inst_0 = io_wb_resps_5_bits_fflags_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_fflags_bits_uop_pc_lob_0 = io_wb_resps_5_bits_fflags_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_taken_0 = io_wb_resps_5_bits_fflags_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_5_bits_fflags_bits_uop_imm_packed_0 = io_wb_resps_5_bits_fflags_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_5_bits_fflags_bits_uop_csr_addr_0 = io_wb_resps_5_bits_fflags_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_rob_idx_0 = io_wb_resps_5_bits_fflags_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_ldq_idx_0 = io_wb_resps_5_bits_fflags_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_stq_idx_0 = io_wb_resps_5_bits_fflags_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_rxq_idx_0 = io_wb_resps_5_bits_fflags_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_pdst_0 = io_wb_resps_5_bits_fflags_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs1_0 = io_wb_resps_5_bits_fflags_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs2_0 = io_wb_resps_5_bits_fflags_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_prs3_0 = io_wb_resps_5_bits_fflags_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_ppred_0 = io_wb_resps_5_bits_fflags_bits_uop_ppred; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_prs1_busy_0 = io_wb_resps_5_bits_fflags_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_prs2_busy_0 = io_wb_resps_5_bits_fflags_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_prs3_busy_0 = io_wb_resps_5_bits_fflags_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ppred_busy_0 = io_wb_resps_5_bits_fflags_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_5_bits_fflags_bits_uop_stale_pdst_0 = io_wb_resps_5_bits_fflags_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_exception_0 = io_wb_resps_5_bits_fflags_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_5_bits_fflags_bits_uop_exc_cause_0 = io_wb_resps_5_bits_fflags_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_bypassable_0 = io_wb_resps_5_bits_fflags_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_uop_mem_cmd_0 = io_wb_resps_5_bits_fflags_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_mem_size_0 = io_wb_resps_5_bits_fflags_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_mem_signed_0 = io_wb_resps_5_bits_fflags_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_fence_0 = io_wb_resps_5_bits_fflags_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_fencei_0 = io_wb_resps_5_bits_fflags_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_amo_0 = io_wb_resps_5_bits_fflags_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_uses_ldq_0 = io_wb_resps_5_bits_fflags_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_uses_stq_0 = io_wb_resps_5_bits_fflags_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_wb_resps_5_bits_fflags_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_is_unique_0 = io_wb_resps_5_bits_fflags_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_flush_on_commit_0 = io_wb_resps_5_bits_fflags_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ldst_is_rs1_0 = io_wb_resps_5_bits_fflags_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_fflags_bits_uop_ldst_0 = io_wb_resps_5_bits_fflags_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs1_0 = io_wb_resps_5_bits_fflags_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs2_0 = io_wb_resps_5_bits_fflags_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_5_bits_fflags_bits_uop_lrs3_0 = io_wb_resps_5_bits_fflags_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_ldst_val_0 = io_wb_resps_5_bits_fflags_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_dst_rtype_0 = io_wb_resps_5_bits_fflags_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_lrs1_rtype_0 = io_wb_resps_5_bits_fflags_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_lrs2_rtype_0 = io_wb_resps_5_bits_fflags_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_frs3_en_0 = io_wb_resps_5_bits_fflags_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_fp_val_0 = io_wb_resps_5_bits_fflags_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_fp_single_0 = io_wb_resps_5_bits_fflags_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_xcpt_pf_if_0 = io_wb_resps_5_bits_fflags_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_xcpt_ae_if_0 = io_wb_resps_5_bits_fflags_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_xcpt_ma_if_0 = io_wb_resps_5_bits_fflags_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_bp_debug_if_0 = io_wb_resps_5_bits_fflags_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_fflags_bits_uop_bp_xcpt_if_0 = io_wb_resps_5_bits_fflags_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_debug_fsrc_0 = io_wb_resps_5_bits_fflags_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_5_bits_fflags_bits_uop_debug_tsrc_0 = io_wb_resps_5_bits_fflags_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_flags_0 = io_wb_resps_5_bits_fflags_bits_flags; // @[rob.scala:211:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[rob.scala:211:7]
wire [6:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[rob.scala:211:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[rob.scala:211:7]
wire [6:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[rob.scala:211:7]
wire [6:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[rob.scala:211:7]
wire io_debug_wb_valids_0_0 = io_debug_wb_valids_0; // @[rob.scala:211:7]
wire io_debug_wb_valids_1_0 = io_debug_wb_valids_1; // @[rob.scala:211:7]
wire io_debug_wb_valids_2_0 = io_debug_wb_valids_2; // @[rob.scala:211:7]
wire io_debug_wb_valids_3_0 = io_debug_wb_valids_3; // @[rob.scala:211:7]
wire io_debug_wb_valids_4_0 = io_debug_wb_valids_4; // @[rob.scala:211:7]
wire io_debug_wb_valids_5_0 = io_debug_wb_valids_5; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_0_0 = io_debug_wb_wdata_0; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_1_0 = io_debug_wb_wdata_1; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_2_0 = io_debug_wb_wdata_2; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_3_0 = io_debug_wb_wdata_3; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_4_0 = io_debug_wb_wdata_4; // @[rob.scala:211:7]
wire [63:0] io_debug_wb_wdata_5_0 = io_debug_wb_wdata_5; // @[rob.scala:211:7]
wire io_fflags_0_valid_0 = io_fflags_0_valid; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_uopc_0 = io_fflags_0_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_fflags_0_bits_uop_inst_0 = io_fflags_0_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_fflags_0_bits_uop_debug_inst_0 = io_fflags_0_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_rvc_0 = io_fflags_0_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_fflags_0_bits_uop_debug_pc_0 = io_fflags_0_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_iq_type_0 = io_fflags_0_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_fflags_0_bits_uop_fu_code_0 = io_fflags_0_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_fflags_0_bits_uop_ctrl_br_type_0 = io_fflags_0_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_ctrl_op1_sel_0 = io_fflags_0_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_op2_sel_0 = io_fflags_0_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_imm_sel_0 = io_fflags_0_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_ctrl_op_fcn_0 = io_fflags_0_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_fcn_dw_0 = io_fflags_0_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_fflags_0_bits_uop_ctrl_csr_cmd_0 = io_fflags_0_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_load_0 = io_fflags_0_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_sta_0 = io_fflags_0_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ctrl_is_std_0 = io_fflags_0_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_iw_state_0 = io_fflags_0_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_iw_p1_poisoned_0 = io_fflags_0_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_iw_p2_poisoned_0 = io_fflags_0_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_br_0 = io_fflags_0_bits_uop_is_br; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_jalr_0 = io_fflags_0_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_jal_0 = io_fflags_0_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_sfb_0 = io_fflags_0_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_fflags_0_bits_uop_br_mask_0 = io_fflags_0_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_fflags_0_bits_uop_br_tag_0 = io_fflags_0_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_ftq_idx_0 = io_fflags_0_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_edge_inst_0 = io_fflags_0_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_pc_lob_0 = io_fflags_0_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_taken_0 = io_fflags_0_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_fflags_0_bits_uop_imm_packed_0 = io_fflags_0_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_fflags_0_bits_uop_csr_addr_0 = io_fflags_0_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_rob_idx_0 = io_fflags_0_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_ldq_idx_0 = io_fflags_0_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_stq_idx_0 = io_fflags_0_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_rxq_idx_0 = io_fflags_0_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_pdst_0 = io_fflags_0_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_prs1_0 = io_fflags_0_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_prs2_0 = io_fflags_0_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_prs3_0 = io_fflags_0_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_ppred_0 = io_fflags_0_bits_uop_ppred; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs1_busy_0 = io_fflags_0_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs2_busy_0 = io_fflags_0_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_prs3_busy_0 = io_fflags_0_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ppred_busy_0 = io_fflags_0_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_fflags_0_bits_uop_stale_pdst_0 = io_fflags_0_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_exception_0 = io_fflags_0_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_fflags_0_bits_uop_exc_cause_0 = io_fflags_0_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bypassable_0 = io_fflags_0_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_uop_mem_cmd_0 = io_fflags_0_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_mem_size_0 = io_fflags_0_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_mem_signed_0 = io_fflags_0_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_fence_0 = io_fflags_0_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_fencei_0 = io_fflags_0_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_amo_0 = io_fflags_0_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_uses_ldq_0 = io_fflags_0_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_uses_stq_0 = io_fflags_0_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_sys_pc2epc_0 = io_fflags_0_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_is_unique_0 = io_fflags_0_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_flush_on_commit_0 = io_fflags_0_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ldst_is_rs1_0 = io_fflags_0_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_ldst_0 = io_fflags_0_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs1_0 = io_fflags_0_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs2_0 = io_fflags_0_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_0_bits_uop_lrs3_0 = io_fflags_0_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_ldst_val_0 = io_fflags_0_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_dst_rtype_0 = io_fflags_0_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_lrs1_rtype_0 = io_fflags_0_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_lrs2_rtype_0 = io_fflags_0_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_frs3_en_0 = io_fflags_0_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_fp_val_0 = io_fflags_0_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_fp_single_0 = io_fflags_0_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_pf_if_0 = io_fflags_0_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_ae_if_0 = io_fflags_0_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_xcpt_ma_if_0 = io_fflags_0_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bp_debug_if_0 = io_fflags_0_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_fflags_0_bits_uop_bp_xcpt_if_0 = io_fflags_0_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_debug_fsrc_0 = io_fflags_0_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_fflags_0_bits_uop_debug_tsrc_0 = io_fflags_0_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_fflags_0_bits_flags_0 = io_fflags_0_bits_flags; // @[rob.scala:211:7]
wire io_fflags_1_valid_0 = io_fflags_1_valid; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_uopc_0 = io_fflags_1_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_fflags_1_bits_uop_inst_0 = io_fflags_1_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_fflags_1_bits_uop_debug_inst_0 = io_fflags_1_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_rvc_0 = io_fflags_1_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_fflags_1_bits_uop_debug_pc_0 = io_fflags_1_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_iq_type_0 = io_fflags_1_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_fflags_1_bits_uop_fu_code_0 = io_fflags_1_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_fflags_1_bits_uop_ctrl_br_type_0 = io_fflags_1_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_ctrl_op1_sel_0 = io_fflags_1_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_op2_sel_0 = io_fflags_1_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_imm_sel_0 = io_fflags_1_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_ctrl_op_fcn_0 = io_fflags_1_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_fcn_dw_0 = io_fflags_1_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_fflags_1_bits_uop_ctrl_csr_cmd_0 = io_fflags_1_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_load_0 = io_fflags_1_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_sta_0 = io_fflags_1_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ctrl_is_std_0 = io_fflags_1_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_iw_state_0 = io_fflags_1_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_iw_p1_poisoned_0 = io_fflags_1_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_iw_p2_poisoned_0 = io_fflags_1_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_br_0 = io_fflags_1_bits_uop_is_br; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_jalr_0 = io_fflags_1_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_jal_0 = io_fflags_1_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_sfb_0 = io_fflags_1_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_fflags_1_bits_uop_br_mask_0 = io_fflags_1_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_fflags_1_bits_uop_br_tag_0 = io_fflags_1_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_ftq_idx_0 = io_fflags_1_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_edge_inst_0 = io_fflags_1_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_pc_lob_0 = io_fflags_1_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_taken_0 = io_fflags_1_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_fflags_1_bits_uop_imm_packed_0 = io_fflags_1_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_fflags_1_bits_uop_csr_addr_0 = io_fflags_1_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_rob_idx_0 = io_fflags_1_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_ldq_idx_0 = io_fflags_1_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_stq_idx_0 = io_fflags_1_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_rxq_idx_0 = io_fflags_1_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_pdst_0 = io_fflags_1_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_prs1_0 = io_fflags_1_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_prs2_0 = io_fflags_1_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_prs3_0 = io_fflags_1_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_ppred_0 = io_fflags_1_bits_uop_ppred; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs1_busy_0 = io_fflags_1_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs2_busy_0 = io_fflags_1_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_prs3_busy_0 = io_fflags_1_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ppred_busy_0 = io_fflags_1_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_fflags_1_bits_uop_stale_pdst_0 = io_fflags_1_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_exception_0 = io_fflags_1_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_fflags_1_bits_uop_exc_cause_0 = io_fflags_1_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bypassable_0 = io_fflags_1_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_uop_mem_cmd_0 = io_fflags_1_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_mem_size_0 = io_fflags_1_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_mem_signed_0 = io_fflags_1_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_fence_0 = io_fflags_1_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_fencei_0 = io_fflags_1_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_amo_0 = io_fflags_1_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_uses_ldq_0 = io_fflags_1_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_uses_stq_0 = io_fflags_1_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_sys_pc2epc_0 = io_fflags_1_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_is_unique_0 = io_fflags_1_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_flush_on_commit_0 = io_fflags_1_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ldst_is_rs1_0 = io_fflags_1_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_ldst_0 = io_fflags_1_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs1_0 = io_fflags_1_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs2_0 = io_fflags_1_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_fflags_1_bits_uop_lrs3_0 = io_fflags_1_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_ldst_val_0 = io_fflags_1_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_dst_rtype_0 = io_fflags_1_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_lrs1_rtype_0 = io_fflags_1_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_lrs2_rtype_0 = io_fflags_1_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_frs3_en_0 = io_fflags_1_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_fp_val_0 = io_fflags_1_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_fp_single_0 = io_fflags_1_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_pf_if_0 = io_fflags_1_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_ae_if_0 = io_fflags_1_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_xcpt_ma_if_0 = io_fflags_1_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bp_debug_if_0 = io_fflags_1_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_fflags_1_bits_uop_bp_xcpt_if_0 = io_fflags_1_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_debug_fsrc_0 = io_fflags_1_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_fflags_1_bits_uop_debug_tsrc_0 = io_fflags_1_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_fflags_1_bits_flags_0 = io_fflags_1_bits_flags; // @[rob.scala:211:7]
wire io_lxcpt_valid_0 = io_lxcpt_valid; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_uopc_0 = io_lxcpt_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_lxcpt_bits_uop_inst_0 = io_lxcpt_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_lxcpt_bits_uop_debug_inst_0 = io_lxcpt_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_rvc_0 = io_lxcpt_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_lxcpt_bits_uop_debug_pc_0 = io_lxcpt_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_iq_type_0 = io_lxcpt_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_lxcpt_bits_uop_fu_code_0 = io_lxcpt_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_lxcpt_bits_uop_ctrl_br_type_0 = io_lxcpt_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lxcpt_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lxcpt_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lxcpt_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lxcpt_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lxcpt_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lxcpt_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_load_0 = io_lxcpt_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_sta_0 = io_lxcpt_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ctrl_is_std_0 = io_lxcpt_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_iw_state_0 = io_lxcpt_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lxcpt_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lxcpt_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_br_0 = io_lxcpt_bits_uop_is_br; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_jalr_0 = io_lxcpt_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_jal_0 = io_lxcpt_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_sfb_0 = io_lxcpt_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_lxcpt_bits_uop_br_mask_0 = io_lxcpt_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_lxcpt_bits_uop_br_tag_0 = io_lxcpt_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_ftq_idx_0 = io_lxcpt_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_edge_inst_0 = io_lxcpt_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_pc_lob_0 = io_lxcpt_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_taken_0 = io_lxcpt_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_lxcpt_bits_uop_imm_packed_0 = io_lxcpt_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_lxcpt_bits_uop_csr_addr_0 = io_lxcpt_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_rob_idx_0 = io_lxcpt_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_ldq_idx_0 = io_lxcpt_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_stq_idx_0 = io_lxcpt_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_rxq_idx_0 = io_lxcpt_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_pdst_0 = io_lxcpt_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_prs1_0 = io_lxcpt_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_prs2_0 = io_lxcpt_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_prs3_0 = io_lxcpt_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_ppred_0 = io_lxcpt_bits_uop_ppred; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs1_busy_0 = io_lxcpt_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs2_busy_0 = io_lxcpt_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_prs3_busy_0 = io_lxcpt_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ppred_busy_0 = io_lxcpt_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_lxcpt_bits_uop_stale_pdst_0 = io_lxcpt_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_exception_0 = io_lxcpt_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_lxcpt_bits_uop_exc_cause_0 = io_lxcpt_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bypassable_0 = io_lxcpt_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_uop_mem_cmd_0 = io_lxcpt_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_mem_size_0 = io_lxcpt_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_mem_signed_0 = io_lxcpt_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_fence_0 = io_lxcpt_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_fencei_0 = io_lxcpt_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_amo_0 = io_lxcpt_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_uses_ldq_0 = io_lxcpt_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_uses_stq_0 = io_lxcpt_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lxcpt_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_is_unique_0 = io_lxcpt_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_flush_on_commit_0 = io_lxcpt_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ldst_is_rs1_0 = io_lxcpt_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_ldst_0 = io_lxcpt_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs1_0 = io_lxcpt_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs2_0 = io_lxcpt_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_lxcpt_bits_uop_lrs3_0 = io_lxcpt_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_ldst_val_0 = io_lxcpt_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_dst_rtype_0 = io_lxcpt_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_lrs1_rtype_0 = io_lxcpt_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_lrs2_rtype_0 = io_lxcpt_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_frs3_en_0 = io_lxcpt_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_fp_val_0 = io_lxcpt_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_fp_single_0 = io_lxcpt_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_pf_if_0 = io_lxcpt_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_ae_if_0 = io_lxcpt_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_xcpt_ma_if_0 = io_lxcpt_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bp_debug_if_0 = io_lxcpt_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_lxcpt_bits_uop_bp_xcpt_if_0 = io_lxcpt_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_debug_fsrc_0 = io_lxcpt_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_lxcpt_bits_uop_debug_tsrc_0 = io_lxcpt_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire [4:0] io_lxcpt_bits_cause_0 = io_lxcpt_bits_cause; // @[rob.scala:211:7]
wire [39:0] io_lxcpt_bits_badvaddr_0 = io_lxcpt_bits_badvaddr; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_uopc_0 = io_csr_replay_bits_uop_uopc; // @[rob.scala:211:7]
wire [31:0] io_csr_replay_bits_uop_inst_0 = io_csr_replay_bits_uop_inst; // @[rob.scala:211:7]
wire [31:0] io_csr_replay_bits_uop_debug_inst_0 = io_csr_replay_bits_uop_debug_inst; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_rvc_0 = io_csr_replay_bits_uop_is_rvc; // @[rob.scala:211:7]
wire [39:0] io_csr_replay_bits_uop_debug_pc_0 = io_csr_replay_bits_uop_debug_pc; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_iq_type_0 = io_csr_replay_bits_uop_iq_type; // @[rob.scala:211:7]
wire [9:0] io_csr_replay_bits_uop_fu_code_0 = io_csr_replay_bits_uop_fu_code; // @[rob.scala:211:7]
wire [3:0] io_csr_replay_bits_uop_ctrl_br_type_0 = io_csr_replay_bits_uop_ctrl_br_type; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_ctrl_op1_sel_0 = io_csr_replay_bits_uop_ctrl_op1_sel; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_op2_sel_0 = io_csr_replay_bits_uop_ctrl_op2_sel; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_imm_sel_0 = io_csr_replay_bits_uop_ctrl_imm_sel; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_ctrl_op_fcn_0 = io_csr_replay_bits_uop_ctrl_op_fcn; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_fcn_dw_0 = io_csr_replay_bits_uop_ctrl_fcn_dw; // @[rob.scala:211:7]
wire [2:0] io_csr_replay_bits_uop_ctrl_csr_cmd_0 = io_csr_replay_bits_uop_ctrl_csr_cmd; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_load_0 = io_csr_replay_bits_uop_ctrl_is_load; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_sta_0 = io_csr_replay_bits_uop_ctrl_is_sta; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ctrl_is_std_0 = io_csr_replay_bits_uop_ctrl_is_std; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_iw_state_0 = io_csr_replay_bits_uop_iw_state; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_iw_p1_poisoned_0 = io_csr_replay_bits_uop_iw_p1_poisoned; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_iw_p2_poisoned_0 = io_csr_replay_bits_uop_iw_p2_poisoned; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_br_0 = io_csr_replay_bits_uop_is_br; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_jalr_0 = io_csr_replay_bits_uop_is_jalr; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_jal_0 = io_csr_replay_bits_uop_is_jal; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_sfb_0 = io_csr_replay_bits_uop_is_sfb; // @[rob.scala:211:7]
wire [15:0] io_csr_replay_bits_uop_br_mask_0 = io_csr_replay_bits_uop_br_mask; // @[rob.scala:211:7]
wire [3:0] io_csr_replay_bits_uop_br_tag_0 = io_csr_replay_bits_uop_br_tag; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_ftq_idx_0 = io_csr_replay_bits_uop_ftq_idx; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_edge_inst_0 = io_csr_replay_bits_uop_edge_inst; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_pc_lob_0 = io_csr_replay_bits_uop_pc_lob; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_taken_0 = io_csr_replay_bits_uop_taken; // @[rob.scala:211:7]
wire [19:0] io_csr_replay_bits_uop_imm_packed_0 = io_csr_replay_bits_uop_imm_packed; // @[rob.scala:211:7]
wire [11:0] io_csr_replay_bits_uop_csr_addr_0 = io_csr_replay_bits_uop_csr_addr; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_rob_idx_0 = io_csr_replay_bits_uop_rob_idx; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_ldq_idx_0 = io_csr_replay_bits_uop_ldq_idx; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_stq_idx_0 = io_csr_replay_bits_uop_stq_idx; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_rxq_idx_0 = io_csr_replay_bits_uop_rxq_idx; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_pdst_0 = io_csr_replay_bits_uop_pdst; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_prs1_0 = io_csr_replay_bits_uop_prs1; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_prs2_0 = io_csr_replay_bits_uop_prs2; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_prs3_0 = io_csr_replay_bits_uop_prs3; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_ppred_0 = io_csr_replay_bits_uop_ppred; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs1_busy_0 = io_csr_replay_bits_uop_prs1_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs2_busy_0 = io_csr_replay_bits_uop_prs2_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_prs3_busy_0 = io_csr_replay_bits_uop_prs3_busy; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ppred_busy_0 = io_csr_replay_bits_uop_ppred_busy; // @[rob.scala:211:7]
wire [6:0] io_csr_replay_bits_uop_stale_pdst_0 = io_csr_replay_bits_uop_stale_pdst; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_exception_0 = io_csr_replay_bits_uop_exception; // @[rob.scala:211:7]
wire [63:0] io_csr_replay_bits_uop_exc_cause_0 = io_csr_replay_bits_uop_exc_cause; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bypassable_0 = io_csr_replay_bits_uop_bypassable; // @[rob.scala:211:7]
wire [4:0] io_csr_replay_bits_uop_mem_cmd_0 = io_csr_replay_bits_uop_mem_cmd; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_mem_size_0 = io_csr_replay_bits_uop_mem_size; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_mem_signed_0 = io_csr_replay_bits_uop_mem_signed; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_fence_0 = io_csr_replay_bits_uop_is_fence; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_fencei_0 = io_csr_replay_bits_uop_is_fencei; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_amo_0 = io_csr_replay_bits_uop_is_amo; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_uses_ldq_0 = io_csr_replay_bits_uop_uses_ldq; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_uses_stq_0 = io_csr_replay_bits_uop_uses_stq; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_sys_pc2epc_0 = io_csr_replay_bits_uop_is_sys_pc2epc; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_is_unique_0 = io_csr_replay_bits_uop_is_unique; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_flush_on_commit_0 = io_csr_replay_bits_uop_flush_on_commit; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ldst_is_rs1_0 = io_csr_replay_bits_uop_ldst_is_rs1; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_ldst_0 = io_csr_replay_bits_uop_ldst; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs1_0 = io_csr_replay_bits_uop_lrs1; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs2_0 = io_csr_replay_bits_uop_lrs2; // @[rob.scala:211:7]
wire [5:0] io_csr_replay_bits_uop_lrs3_0 = io_csr_replay_bits_uop_lrs3; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_ldst_val_0 = io_csr_replay_bits_uop_ldst_val; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_dst_rtype_0 = io_csr_replay_bits_uop_dst_rtype; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_lrs1_rtype_0 = io_csr_replay_bits_uop_lrs1_rtype; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_lrs2_rtype_0 = io_csr_replay_bits_uop_lrs2_rtype; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_frs3_en_0 = io_csr_replay_bits_uop_frs3_en; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_fp_val_0 = io_csr_replay_bits_uop_fp_val; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_fp_single_0 = io_csr_replay_bits_uop_fp_single; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_pf_if_0 = io_csr_replay_bits_uop_xcpt_pf_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_ae_if_0 = io_csr_replay_bits_uop_xcpt_ae_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_xcpt_ma_if_0 = io_csr_replay_bits_uop_xcpt_ma_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bp_debug_if_0 = io_csr_replay_bits_uop_bp_debug_if; // @[rob.scala:211:7]
wire io_csr_replay_bits_uop_bp_xcpt_if_0 = io_csr_replay_bits_uop_bp_xcpt_if; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_debug_fsrc_0 = io_csr_replay_bits_uop_debug_fsrc; // @[rob.scala:211:7]
wire [1:0] io_csr_replay_bits_uop_debug_tsrc_0 = io_csr_replay_bits_uop_debug_tsrc; // @[rob.scala:211:7]
wire io_csr_stall_0 = io_csr_stall; // @[rob.scala:211:7]
wire [63:0] io_debug_tsc_0 = io_debug_tsc; // @[rob.scala:211:7]
wire _io_commit_rbk_valids_0_T_1 = 1'h1; // @[rob.scala:211:7, :431:63]
wire _io_commit_rbk_valids_1_T_1 = 1'h1; // @[rob.scala:211:7, :431:63]
wire _io_commit_rbk_valids_2_T_1 = 1'h1; // @[rob.scala:211:7, :431:63]
wire _lxcpt_older_T = 1'h1; // @[rob.scala:211:7, :640:23]
wire lxcpt_older = 1'h1; // @[rob.scala:211:7, :640:44]
wire io_enq_uops_0_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_enq_uops_1_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_enq_uops_2_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_valid = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_br = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_taken = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_exception = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_valid = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_br = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_taken = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_exception = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_valid = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_br = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_taken = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_exception = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[rob.scala:211:7]
wire io_wb_resps_5_bits_predicated = 1'h0; // @[rob.scala:211:7]
wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[rob.scala:211:7]
wire io_csr_replay_valid = 1'h0; // @[rob.scala:211:7]
wire io_commit_uops_0_ppred_busy_0 = 1'h0; // @[rob.scala:211:7]
wire io_commit_uops_1_ppred_busy_0 = 1'h0; // @[rob.scala:211:7]
wire io_commit_uops_2_ppred_busy_0 = 1'h0; // @[rob.scala:211:7]
wire debug_entry_0_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_0_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_1_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_2_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_3_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_4_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_5_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_6_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_7_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_8_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_9_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_10_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_11_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_12_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_13_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_14_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_15_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_16_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_17_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_18_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_19_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_20_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_21_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_22_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_23_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_24_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_25_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_26_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_27_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_28_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_29_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_30_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_31_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_32_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_33_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_34_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_35_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_36_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_37_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_38_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_39_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_40_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_41_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_42_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_43_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_44_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_45_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_46_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_47_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_48_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_49_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_50_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_51_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_52_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_53_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_54_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_55_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_56_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_57_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_58_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_59_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_60_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_61_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_62_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_63_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_64_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_65_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_66_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_67_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_68_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_69_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_70_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_71_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_72_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_73_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_74_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_75_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_76_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_77_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_78_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_79_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_80_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_81_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_82_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_83_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_84_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_85_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_86_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_87_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_88_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_89_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_90_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_91_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_92_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_93_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_94_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_valid = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_unsafe = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_rvc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ctrl_fcn_dw = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ctrl_is_load = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ctrl_is_sta = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ctrl_is_std = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_iw_p1_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_iw_p2_poisoned = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_br = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_jalr = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_jal = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_sfb = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_edge_inst = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_taken = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_prs1_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_prs2_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_prs3_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ppred_busy = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_exception = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_bypassable = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_mem_signed = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_fence = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_fencei = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_amo = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_uses_ldq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_uses_stq = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_is_unique = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_flush_on_commit = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_ldst_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_frs3_en = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_fp_val = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_fp_single = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_xcpt_pf_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_xcpt_ae_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_xcpt_ma_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_bp_debug_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_uop_bp_xcpt_if = 1'h0; // @[rob.scala:285:25]
wire debug_entry_95_exception = 1'h0; // @[rob.scala:285:25]
wire _rob_unsafe_masked_WIRE_0 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_1 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_2 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_3 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_4 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_5 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_6 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_7 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_8 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_9 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_10 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_11 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_12 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_13 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_14 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_15 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_16 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_17 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_18 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_19 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_20 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_21 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_22 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_23 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_24 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_25 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_26 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_27 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_28 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_29 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_30 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_31 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_32 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_33 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_34 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_35 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_36 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_37 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_38 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_39 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_40 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_41 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_42 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_43 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_44 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_45 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_46 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_47 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_48 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_49 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_50 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_51 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_52 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_53 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_54 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_55 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_56 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_57 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_58 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_59 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_60 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_61 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_62 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_63 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_64 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_65 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_66 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_67 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_68 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_69 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_70 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_71 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_72 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_73 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_74 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_75 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_76 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_77 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_78 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_79 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_80 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_81 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_82 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_83 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_84 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_85 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_86 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_87 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_88 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_89 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_90 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_91 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_92 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_93 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_94 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_95 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_96 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_97 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_98 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_99 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_100 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_101 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_102 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_103 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_104 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_105 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_106 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_107 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_108 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_109 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_110 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_111 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_112 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_113 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_114 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_115 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_116 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_117 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_118 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_119 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_120 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_121 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_122 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_123 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_124 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_125 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_126 = 1'h0; // @[rob.scala:293:43]
wire _rob_unsafe_masked_WIRE_127 = 1'h0; // @[rob.scala:293:43]
wire rob_unsafe_masked_3 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_7 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_11 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_15 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_19 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_23 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_27 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_31 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_35 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_39 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_43 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_47 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_51 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_55 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_59 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_63 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_67 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_71 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_75 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_79 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_83 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_87 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_91 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_95 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_99 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_103 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_107 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_111 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_115 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_119 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_123 = 1'h0; // @[rob.scala:293:35]
wire rob_unsafe_masked_127 = 1'h0; // @[rob.scala:293:35]
wire _rob_debug_inst_wmask_WIRE_0 = 1'h0; // @[rob.scala:297:46]
wire _rob_debug_inst_wmask_WIRE_1 = 1'h0; // @[rob.scala:297:46]
wire _rob_debug_inst_wmask_WIRE_2 = 1'h0; // @[rob.scala:297:46]
wire _rob_val_WIRE_0 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_3 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_4 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_5 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_6 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_7 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_8 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_9 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_10 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_11 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_12 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_13 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_14 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_15 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_16 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_17 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_18 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_19 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_20 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_21 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_22 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_23 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_24 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_25 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_26 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_27 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_28 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_29 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_30 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_31 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_0 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_1 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_2 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_3 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_4 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_5 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_6 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_7 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_8 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_9 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_10 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_11 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_12 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_13 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_14 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_15 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_16 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_17 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_18 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_19 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_20 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_21 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_22 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_23 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_24 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_25 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_26 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_27 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_28 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_29 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_30 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_1_31 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_0 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_1 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_2 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_3 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_4 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_5 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_6 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_7 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_8 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_9 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_10 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_11 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_12 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_13 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_14 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_15 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_16 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_17 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_18 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_19 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_20 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_21 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_22 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_23 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_24 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_25 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_26 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_27 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_28 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_29 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_30 = 1'h0; // @[rob.scala:308:40]
wire _rob_val_WIRE_2_31 = 1'h0; // @[rob.scala:308:40]
wire [4:0] io_enq_uops_0_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_1_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_enq_uops_2_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_flags = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_2_bits_fflags_bits_flags = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_ppred = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits_flags = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_ppred_0 = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_ppred_0 = 5'h0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_ppred_0 = 5'h0; // @[rob.scala:211:7]
wire [4:0] debug_entry_0_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_0_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_1_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_2_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_3_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_4_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_5_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_6_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_7_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_8_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_9_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_10_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_11_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_12_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_13_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_14_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_15_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_16_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_17_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_18_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_19_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_20_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_21_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_22_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_23_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_24_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_25_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_26_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_27_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_28_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_29_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_30_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_31_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_32_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_33_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_34_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_35_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_36_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_37_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_38_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_39_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_40_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_41_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_42_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_43_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_44_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_45_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_46_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_47_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_48_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_49_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_50_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_51_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_52_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_53_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_54_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_55_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_56_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_57_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_58_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_59_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_60_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_61_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_62_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_63_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_64_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_65_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_66_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_67_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_68_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_69_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_70_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_71_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_72_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_73_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_74_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_75_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_76_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_77_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_78_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_79_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_80_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_81_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_82_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_83_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_84_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_85_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_86_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_87_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_88_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_89_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_90_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_91_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_92_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_93_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_94_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_ctrl_op_fcn = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_ftq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_ldq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_stq_idx = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_ppred = 5'h0; // @[rob.scala:285:25]
wire [4:0] debug_entry_95_uop_mem_cmd = 5'h0; // @[rob.scala:285:25]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_uopc = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_uopc = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_uopc = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[rob.scala:211:7]
wire [6:0] io_wb_resps_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[rob.scala:211:7]
wire [6:0] debug_entry_0_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_0_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_1_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_2_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_3_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_4_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_5_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_6_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_7_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_8_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_9_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_10_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_11_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_12_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_13_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_14_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_15_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_16_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_17_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_18_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_19_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_20_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_21_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_22_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_23_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_24_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_25_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_26_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_27_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_28_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_29_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_30_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_31_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_32_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_33_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_34_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_35_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_36_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_37_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_38_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_39_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_40_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_41_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_42_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_43_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_44_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_45_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_46_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_47_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_48_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_49_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_50_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_51_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_52_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_53_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_54_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_55_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_56_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_57_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_58_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_59_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_60_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_61_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_62_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_63_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_64_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_65_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_66_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_67_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_68_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_69_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_70_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_71_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_72_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_73_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_74_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_75_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_76_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_77_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_78_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_79_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_80_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_81_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_82_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_83_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_84_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_85_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_86_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_87_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_88_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_89_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_90_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_91_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_92_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_93_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_94_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_uopc = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_rob_idx = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_pdst = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_prs1 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_prs2 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_prs3 = 7'h0; // @[rob.scala:285:25]
wire [6:0] debug_entry_95_uop_stale_pdst = 7'h0; // @[rob.scala:285:25]
wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] io_wb_resps_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[rob.scala:211:7]
wire [31:0] debug_entry_0_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_0_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_1_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_1_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_2_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_2_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_3_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_3_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_4_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_4_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_5_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_5_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_6_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_6_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_7_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_7_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_8_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_8_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_9_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_9_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_10_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_10_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_11_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_11_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_12_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_12_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_13_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_13_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_14_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_14_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_15_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_15_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_16_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_16_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_17_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_17_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_18_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_18_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_19_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_19_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_20_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_20_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_21_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_21_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_22_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_22_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_23_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_23_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_24_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_24_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_25_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_25_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_26_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_26_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_27_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_27_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_28_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_28_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_29_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_29_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_30_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_30_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_31_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_31_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_32_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_32_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_33_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_33_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_34_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_34_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_35_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_35_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_36_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_36_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_37_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_37_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_38_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_38_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_39_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_39_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_40_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_40_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_41_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_41_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_42_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_42_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_43_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_43_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_44_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_44_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_45_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_45_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_46_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_46_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_47_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_47_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_48_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_48_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_49_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_49_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_50_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_50_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_51_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_51_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_52_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_52_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_53_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_53_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_54_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_54_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_55_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_55_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_56_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_56_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_57_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_57_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_58_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_58_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_59_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_59_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_60_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_60_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_61_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_61_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_62_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_62_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_63_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_63_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_64_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_64_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_65_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_65_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_66_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_66_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_67_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_67_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_68_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_68_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_69_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_69_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_70_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_70_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_71_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_71_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_72_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_72_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_73_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_73_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_74_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_74_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_75_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_75_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_76_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_76_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_77_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_77_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_78_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_78_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_79_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_79_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_80_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_80_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_81_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_81_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_82_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_82_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_83_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_83_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_84_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_84_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_85_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_85_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_86_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_86_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_87_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_87_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_88_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_88_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_89_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_89_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_90_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_90_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_91_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_91_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_92_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_92_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_93_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_93_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_94_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_94_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_95_uop_inst = 32'h0; // @[rob.scala:285:25]
wire [31:0] debug_entry_95_uop_debug_inst = 32'h0; // @[rob.scala:285:25]
wire [39:0] io_wb_resps_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rob.scala:211:7]
wire [39:0] io_wb_resps_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[rob.scala:211:7]
wire [39:0] io_csr_replay_bits_badvaddr = 40'h0; // @[rob.scala:211:7]
wire [39:0] debug_entry_0_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_1_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_2_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_3_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_4_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_5_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_6_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_7_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_8_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_9_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_10_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_11_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_12_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_13_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_14_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_15_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_16_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_17_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_18_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_19_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_20_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_21_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_22_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_23_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_24_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_25_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_26_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_27_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_28_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_29_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_30_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_31_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_32_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_33_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_34_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_35_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_36_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_37_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_38_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_39_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_40_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_41_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_42_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_43_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_44_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_45_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_46_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_47_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_48_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_49_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_50_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_51_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_52_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_53_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_54_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_55_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_56_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_57_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_58_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_59_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_60_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_61_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_62_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_63_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_64_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_65_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_66_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_67_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_68_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_69_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_70_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_71_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_72_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_73_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_74_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_75_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_76_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_77_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_78_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_79_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_80_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_81_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_82_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_83_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_84_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_85_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_86_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_87_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_88_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_89_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_90_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_91_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_92_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_93_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_94_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [39:0] debug_entry_95_uop_debug_pc = 40'h0; // @[rob.scala:285:25]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:211:7]
wire [2:0] io_com_xcpt_bits_flush_typ = 3'h0; // @[rob.scala:211:7]
wire [2:0] debug_entry_0_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_0_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_1_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_2_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_3_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_4_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_5_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_6_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_7_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_8_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_9_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_10_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_11_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_12_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_13_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_14_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_15_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_16_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_17_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_18_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_19_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_20_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_21_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_22_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_23_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_24_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_25_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_26_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_27_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_28_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_29_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_30_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_31_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_32_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_32_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_32_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_32_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_33_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_33_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_33_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_33_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_34_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_34_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_34_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_34_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_35_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_35_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_35_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_35_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_36_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_36_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_36_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_36_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_37_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_37_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_37_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_37_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_38_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_38_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_38_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_38_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_39_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_39_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_39_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_39_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_40_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_40_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_40_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_40_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_41_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_41_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_41_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_41_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_42_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_42_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_42_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_42_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_43_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_43_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_43_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_43_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_44_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_44_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_44_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_44_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_45_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_45_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_45_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_45_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_46_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_46_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_46_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_46_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_47_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_47_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_47_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_47_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_48_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_48_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_48_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_48_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_49_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_49_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_49_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_49_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_50_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_50_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_50_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_50_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_51_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_51_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_51_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_51_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_52_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_52_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_52_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_52_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_53_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_53_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_53_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_53_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_54_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_54_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_54_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_54_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_55_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_55_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_55_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_55_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_56_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_56_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_56_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_56_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_57_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_57_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_57_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_57_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_58_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_58_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_58_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_58_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_59_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_59_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_59_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_59_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_60_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_60_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_60_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_60_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_61_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_61_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_61_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_61_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_62_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_62_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_62_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_62_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_63_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_63_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_63_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_63_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_64_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_64_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_64_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_64_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_65_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_65_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_65_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_65_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_66_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_66_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_66_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_66_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_67_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_67_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_67_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_67_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_68_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_68_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_68_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_68_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_69_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_69_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_69_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_69_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_70_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_70_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_70_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_70_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_71_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_71_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_71_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_71_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_72_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_72_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_72_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_72_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_73_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_73_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_73_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_73_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_74_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_74_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_74_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_74_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_75_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_75_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_75_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_75_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_76_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_76_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_76_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_76_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_77_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_77_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_77_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_77_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_78_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_78_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_78_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_78_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_79_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_79_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_79_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_79_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_80_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_80_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_80_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_80_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_81_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_81_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_81_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_81_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_82_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_82_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_82_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_82_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_83_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_83_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_83_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_83_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_84_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_84_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_84_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_84_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_85_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_85_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_85_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_85_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_86_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_86_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_86_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_86_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_87_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_87_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_87_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_87_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_88_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_88_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_88_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_88_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_89_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_89_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_89_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_89_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_90_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_90_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_90_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_90_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_91_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_91_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_91_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_91_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_92_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_92_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_92_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_92_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_93_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_93_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_93_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_93_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_94_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_94_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_94_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_94_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_95_uop_iq_type = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_95_uop_ctrl_op2_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_95_uop_ctrl_imm_sel = 3'h0; // @[rob.scala:285:25]
wire [2:0] debug_entry_95_uop_ctrl_csr_cmd = 3'h0; // @[rob.scala:285:25]
wire [9:0] io_wb_resps_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[rob.scala:211:7]
wire [9:0] io_wb_resps_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[rob.scala:211:7]
wire [9:0] debug_entry_0_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_1_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_2_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_3_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_4_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_5_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_6_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_7_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_8_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_9_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_10_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_11_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_12_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_13_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_14_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_15_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_16_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_17_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_18_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_19_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_20_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_21_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_22_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_23_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_24_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_25_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_26_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_27_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_28_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_29_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_30_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_31_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_32_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_33_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_34_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_35_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_36_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_37_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_38_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_39_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_40_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_41_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_42_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_43_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_44_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_45_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_46_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_47_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_48_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_49_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_50_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_51_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_52_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_53_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_54_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_55_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_56_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_57_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_58_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_59_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_60_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_61_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_62_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_63_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_64_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_65_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_66_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_67_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_68_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_69_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_70_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_71_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_72_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_73_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_74_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_75_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_76_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_77_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_78_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_79_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_80_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_81_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_82_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_83_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_84_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_85_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_86_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_87_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_88_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_89_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_90_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_91_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_92_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_93_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_94_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [9:0] debug_entry_95_uop_fu_code = 10'h0; // @[rob.scala:285:25]
wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[rob.scala:211:7]
wire [3:0] io_wb_resps_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[rob.scala:211:7]
wire [3:0] debug_entry_0_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_0_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_1_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_1_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_2_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_2_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_3_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_3_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_4_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_4_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_5_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_5_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_6_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_6_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_7_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_7_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_8_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_8_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_9_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_9_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_10_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_10_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_11_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_11_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_12_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_12_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_13_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_13_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_14_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_14_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_15_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_15_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_16_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_16_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_17_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_17_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_18_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_18_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_19_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_19_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_20_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_20_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_21_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_21_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_22_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_22_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_23_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_23_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_24_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_24_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_25_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_25_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_26_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_26_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_27_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_27_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_28_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_28_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_29_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_29_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_30_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_30_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_31_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_31_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_32_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_32_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_33_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_33_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_34_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_34_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_35_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_35_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_36_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_36_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_37_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_37_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_38_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_38_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_39_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_39_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_40_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_40_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_41_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_41_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_42_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_42_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_43_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_43_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_44_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_44_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_45_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_45_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_46_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_46_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_47_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_47_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_48_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_48_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_49_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_49_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_50_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_50_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_51_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_51_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_52_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_52_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_53_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_53_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_54_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_54_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_55_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_55_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_56_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_56_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_57_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_57_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_58_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_58_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_59_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_59_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_60_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_60_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_61_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_61_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_62_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_62_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_63_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_63_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_64_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_64_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_65_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_65_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_66_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_66_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_67_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_67_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_68_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_68_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_69_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_69_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_70_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_70_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_71_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_71_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_72_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_72_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_73_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_73_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_74_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_74_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_75_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_75_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_76_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_76_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_77_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_77_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_78_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_78_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_79_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_79_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_80_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_80_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_81_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_81_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_82_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_82_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_83_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_83_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_84_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_84_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_85_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_85_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_86_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_86_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_87_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_87_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_88_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_88_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_89_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_89_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_90_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_90_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_91_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_91_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_92_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_92_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_93_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_93_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_94_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_94_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_95_uop_ctrl_br_type = 4'h0; // @[rob.scala:285:25]
wire [3:0] debug_entry_95_uop_br_tag = 4'h0; // @[rob.scala:285:25]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] io_wb_resps_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[rob.scala:211:7]
wire [1:0] debug_entry_0_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_0_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_1_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_2_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_3_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_4_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_5_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_6_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_7_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_8_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_9_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_10_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_11_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_12_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_13_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_14_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_15_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_16_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_17_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_18_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_19_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_20_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_21_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_22_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_23_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_24_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_25_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_26_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_27_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_28_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_29_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_30_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_31_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_32_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_33_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_34_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_35_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_36_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_37_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_38_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_39_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_40_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_41_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_42_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_43_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_44_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_45_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_46_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_47_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_48_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_49_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_50_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_51_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_52_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_53_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_54_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_55_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_56_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_57_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_58_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_59_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_60_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_61_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_62_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_63_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_64_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_65_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_66_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_67_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_68_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_69_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_70_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_71_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_72_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_73_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_74_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_75_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_76_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_77_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_78_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_79_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_80_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_81_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_82_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_83_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_84_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_85_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_86_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_87_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_88_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_89_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_90_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_91_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_92_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_93_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_94_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_ctrl_op1_sel = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_iw_state = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_rxq_idx = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_mem_size = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_dst_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_lrs1_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_lrs2_rtype = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_debug_fsrc = 2'h0; // @[rob.scala:285:25]
wire [1:0] debug_entry_95_uop_debug_tsrc = 2'h0; // @[rob.scala:285:25]
wire [15:0] io_wb_resps_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[rob.scala:211:7]
wire [15:0] io_wb_resps_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[rob.scala:211:7]
wire [15:0] debug_entry_0_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_1_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_2_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_3_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_4_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_5_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_6_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_7_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_8_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_9_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_10_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_11_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_12_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_13_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_14_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_15_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_16_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_17_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_18_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_19_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_20_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_21_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_22_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_23_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_24_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_25_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_26_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_27_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_28_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_29_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_30_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_31_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_32_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_33_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_34_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_35_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_36_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_37_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_38_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_39_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_40_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_41_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_42_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_43_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_44_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_45_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_46_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_47_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_48_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_49_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_50_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_51_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_52_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_53_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_54_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_55_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_56_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_57_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_58_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_59_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_60_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_61_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_62_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_63_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_64_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_65_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_66_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_67_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_68_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_69_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_70_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_71_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_72_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_73_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_74_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_75_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_76_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_77_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_78_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_79_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_80_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_81_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_82_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_83_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_84_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_85_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_86_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_87_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_88_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_89_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_90_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_91_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_92_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_93_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_94_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [15:0] debug_entry_95_uop_br_mask = 16'h0; // @[rob.scala:285:25]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_ldst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_ldst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_ldst = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[rob.scala:211:7]
wire [5:0] io_wb_resps_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[rob.scala:211:7]
wire [5:0] debug_entry_0_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_0_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_1_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_2_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_3_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_4_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_5_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_6_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_7_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_8_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_9_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_10_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_11_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_12_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_13_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_14_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_15_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_16_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_17_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_18_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_19_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_20_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_21_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_22_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_23_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_24_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_25_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_26_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_27_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_28_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_29_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_30_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_31_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_32_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_32_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_32_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_32_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_32_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_33_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_33_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_33_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_33_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_33_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_34_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_34_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_34_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_34_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_34_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_35_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_35_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_35_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_35_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_35_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_36_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_36_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_36_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_36_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_36_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_37_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_37_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_37_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_37_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_37_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_38_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_38_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_38_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_38_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_38_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_39_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_39_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_39_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_39_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_39_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_40_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_40_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_40_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_40_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_40_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_41_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_41_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_41_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_41_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_41_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_42_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_42_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_42_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_42_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_42_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_43_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_43_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_43_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_43_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_43_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_44_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_44_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_44_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_44_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_44_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_45_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_45_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_45_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_45_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_45_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_46_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_46_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_46_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_46_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_46_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_47_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_47_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_47_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_47_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_47_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_48_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_48_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_48_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_48_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_48_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_49_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_49_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_49_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_49_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_49_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_50_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_50_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_50_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_50_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_50_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_51_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_51_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_51_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_51_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_51_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_52_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_52_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_52_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_52_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_52_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_53_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_53_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_53_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_53_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_53_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_54_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_54_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_54_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_54_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_54_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_55_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_55_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_55_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_55_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_55_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_56_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_56_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_56_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_56_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_56_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_57_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_57_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_57_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_57_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_57_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_58_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_58_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_58_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_58_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_58_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_59_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_59_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_59_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_59_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_59_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_60_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_60_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_60_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_60_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_60_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_61_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_61_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_61_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_61_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_61_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_62_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_62_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_62_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_62_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_62_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_63_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_63_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_63_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_63_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_63_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_64_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_64_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_64_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_64_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_64_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_65_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_65_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_65_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_65_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_65_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_66_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_66_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_66_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_66_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_66_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_67_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_67_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_67_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_67_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_67_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_68_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_68_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_68_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_68_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_68_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_69_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_69_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_69_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_69_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_69_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_70_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_70_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_70_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_70_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_70_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_71_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_71_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_71_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_71_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_71_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_72_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_72_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_72_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_72_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_72_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_73_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_73_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_73_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_73_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_73_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_74_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_74_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_74_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_74_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_74_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_75_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_75_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_75_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_75_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_75_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_76_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_76_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_76_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_76_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_76_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_77_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_77_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_77_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_77_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_77_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_78_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_78_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_78_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_78_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_78_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_79_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_79_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_79_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_79_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_79_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_80_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_80_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_80_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_80_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_80_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_81_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_81_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_81_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_81_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_81_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_82_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_82_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_82_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_82_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_82_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_83_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_83_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_83_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_83_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_83_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_84_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_84_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_84_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_84_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_84_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_85_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_85_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_85_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_85_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_85_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_86_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_86_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_86_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_86_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_86_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_87_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_87_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_87_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_87_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_87_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_88_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_88_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_88_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_88_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_88_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_89_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_89_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_89_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_89_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_89_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_90_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_90_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_90_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_90_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_90_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_91_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_91_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_91_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_91_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_91_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_92_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_92_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_92_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_92_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_92_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_93_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_93_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_93_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_93_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_93_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_94_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_94_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_94_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_94_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_94_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_95_uop_pc_lob = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_95_uop_ldst = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_95_uop_lrs1 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_95_uop_lrs2 = 6'h0; // @[rob.scala:285:25]
wire [5:0] debug_entry_95_uop_lrs3 = 6'h0; // @[rob.scala:285:25]
wire [19:0] io_wb_resps_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rob.scala:211:7]
wire [19:0] io_wb_resps_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[rob.scala:211:7]
wire [19:0] debug_entry_0_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_1_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_2_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_3_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_4_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_5_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_6_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_7_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_8_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_9_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_10_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_11_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_12_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_13_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_14_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_15_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_16_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_17_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_18_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_19_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_20_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_21_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_22_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_23_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_24_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_25_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_26_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_27_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_28_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_29_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_30_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_31_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_32_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_33_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_34_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_35_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_36_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_37_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_38_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_39_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_40_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_41_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_42_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_43_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_44_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_45_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_46_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_47_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_48_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_49_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_50_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_51_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_52_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_53_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_54_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_55_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_56_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_57_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_58_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_59_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_60_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_61_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_62_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_63_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_64_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_65_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_66_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_67_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_68_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_69_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_70_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_71_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_72_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_73_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_74_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_75_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_76_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_77_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_78_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_79_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_80_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_81_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_82_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_83_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_84_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_85_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_86_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_87_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_88_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_89_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_90_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_91_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_92_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_93_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_94_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [19:0] debug_entry_95_uop_imm_packed = 20'h0; // @[rob.scala:285:25]
wire [11:0] io_wb_resps_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rob.scala:211:7]
wire [11:0] io_wb_resps_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[rob.scala:211:7]
wire [11:0] debug_entry_0_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_1_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_2_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_3_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_4_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_5_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_6_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_7_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_8_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_9_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_10_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_11_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_12_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_13_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_14_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_15_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_16_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_17_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_18_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_19_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_20_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_21_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_22_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_23_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_24_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_25_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_26_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_27_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_28_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_29_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_30_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_31_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_32_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_33_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_34_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_35_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_36_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_37_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_38_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_39_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_40_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_41_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_42_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_43_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_44_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_45_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_46_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_47_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_48_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_49_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_50_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_51_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_52_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_53_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_54_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_55_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_56_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_57_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_58_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_59_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_60_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_61_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_62_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_63_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_64_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_65_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_66_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_67_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_68_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_69_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_70_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_71_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_72_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_73_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_74_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_75_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_76_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_77_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_78_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_79_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_80_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_81_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_82_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_83_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_84_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_85_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_86_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_87_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_88_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_89_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_90_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_91_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_92_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_93_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_94_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [11:0] debug_entry_95_uop_csr_addr = 12'h0; // @[rob.scala:285:25]
wire [63:0] io_wb_resps_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_wb_resps_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_flush_bits_cause = 64'h0; // @[rob.scala:211:7]
wire [63:0] io_flush_bits_badvaddr = 64'h0; // @[rob.scala:211:7]
wire [63:0] debug_entry_0_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_1_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_2_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_3_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_4_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_5_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_6_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_7_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_8_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_9_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_10_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_11_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_12_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_13_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_14_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_15_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_16_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_17_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_18_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_19_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_20_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_21_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_22_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_23_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_24_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_25_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_26_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_27_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_28_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_29_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_30_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_31_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_32_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_33_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_34_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_35_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_36_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_37_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_38_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_39_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_40_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_41_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_42_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_43_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_44_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_45_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_46_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_47_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_48_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_49_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_50_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_51_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_52_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_53_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_54_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_55_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_56_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_57_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_58_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_59_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_60_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_61_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_62_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_63_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_64_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_65_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_66_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_67_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_68_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_69_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_70_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_71_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_72_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_73_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_74_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_75_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_76_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_77_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_78_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_79_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_80_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_81_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_82_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_83_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_84_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_85_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_86_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_87_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_88_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_89_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_90_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_91_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_92_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_93_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_94_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [63:0] debug_entry_95_uop_exc_cause = 64'h0; // @[rob.scala:285:25]
wire [4:0] io_csr_replay_bits_cause = 5'h11; // @[rob.scala:211:7]
wire rob_debug_inst_wmask_0 = io_enq_valids_0_0; // @[rob.scala:211:7, :297:38]
wire rob_debug_inst_wmask_1 = io_enq_valids_1_0; // @[rob.scala:211:7, :297:38]
wire rob_debug_inst_wmask_2 = io_enq_valids_2_0; // @[rob.scala:211:7, :297:38]
wire [31:0] rob_debug_inst_wdata_0 = io_enq_uops_0_debug_inst_0; // @[rob.scala:211:7, :298:34]
wire [31:0] rob_debug_inst_wdata_1 = io_enq_uops_1_debug_inst_0; // @[rob.scala:211:7, :298:34]
wire [31:0] rob_debug_inst_wdata_2 = io_enq_uops_2_debug_inst_0; // @[rob.scala:211:7, :298:34]
wire [6:0] rob_tail_idx; // @[rob.scala:229:59]
wire [6:0] rob_pnr_idx; // @[rob.scala:233:59]
wire [6:0] rob_head_idx; // @[rob.scala:225:59]
wire new_xcpt_valid = io_lxcpt_valid_0; // @[rob.scala:211:7, :639:41]
wire [6:0] new_xcpt_uop_uopc = io_lxcpt_bits_uop_uopc_0; // @[rob.scala:211:7, :641:23]
wire [31:0] new_xcpt_uop_inst = io_lxcpt_bits_uop_inst_0; // @[rob.scala:211:7, :641:23]
wire [31:0] new_xcpt_uop_debug_inst = io_lxcpt_bits_uop_debug_inst_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_rvc = io_lxcpt_bits_uop_is_rvc_0; // @[rob.scala:211:7, :641:23]
wire [39:0] new_xcpt_uop_debug_pc = io_lxcpt_bits_uop_debug_pc_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_iq_type = io_lxcpt_bits_uop_iq_type_0; // @[rob.scala:211:7, :641:23]
wire [9:0] new_xcpt_uop_fu_code = io_lxcpt_bits_uop_fu_code_0; // @[rob.scala:211:7, :641:23]
wire [3:0] new_xcpt_uop_ctrl_br_type = io_lxcpt_bits_uop_ctrl_br_type_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_ctrl_op1_sel = io_lxcpt_bits_uop_ctrl_op1_sel_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_op2_sel = io_lxcpt_bits_uop_ctrl_op2_sel_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_imm_sel = io_lxcpt_bits_uop_ctrl_imm_sel_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_ctrl_op_fcn = io_lxcpt_bits_uop_ctrl_op_fcn_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_fcn_dw = io_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[rob.scala:211:7, :641:23]
wire [2:0] new_xcpt_uop_ctrl_csr_cmd = io_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_load = io_lxcpt_bits_uop_ctrl_is_load_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_sta = io_lxcpt_bits_uop_ctrl_is_sta_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ctrl_is_std = io_lxcpt_bits_uop_ctrl_is_std_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_iw_state = io_lxcpt_bits_uop_iw_state_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_iw_p1_poisoned = io_lxcpt_bits_uop_iw_p1_poisoned_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_iw_p2_poisoned = io_lxcpt_bits_uop_iw_p2_poisoned_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_br = io_lxcpt_bits_uop_is_br_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_jalr = io_lxcpt_bits_uop_is_jalr_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_jal = io_lxcpt_bits_uop_is_jal_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_sfb = io_lxcpt_bits_uop_is_sfb_0; // @[rob.scala:211:7, :641:23]
wire [15:0] new_xcpt_uop_br_mask = io_lxcpt_bits_uop_br_mask_0; // @[rob.scala:211:7, :641:23]
wire [3:0] new_xcpt_uop_br_tag = io_lxcpt_bits_uop_br_tag_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_ftq_idx = io_lxcpt_bits_uop_ftq_idx_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_edge_inst = io_lxcpt_bits_uop_edge_inst_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_pc_lob = io_lxcpt_bits_uop_pc_lob_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_taken = io_lxcpt_bits_uop_taken_0; // @[rob.scala:211:7, :641:23]
wire [19:0] new_xcpt_uop_imm_packed = io_lxcpt_bits_uop_imm_packed_0; // @[rob.scala:211:7, :641:23]
wire [11:0] new_xcpt_uop_csr_addr = io_lxcpt_bits_uop_csr_addr_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_rob_idx = io_lxcpt_bits_uop_rob_idx_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_ldq_idx = io_lxcpt_bits_uop_ldq_idx_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_stq_idx = io_lxcpt_bits_uop_stq_idx_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_rxq_idx = io_lxcpt_bits_uop_rxq_idx_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_pdst = io_lxcpt_bits_uop_pdst_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_prs1 = io_lxcpt_bits_uop_prs1_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_prs2 = io_lxcpt_bits_uop_prs2_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_prs3 = io_lxcpt_bits_uop_prs3_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_ppred = io_lxcpt_bits_uop_ppred_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs1_busy = io_lxcpt_bits_uop_prs1_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs2_busy = io_lxcpt_bits_uop_prs2_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_prs3_busy = io_lxcpt_bits_uop_prs3_busy_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ppred_busy = io_lxcpt_bits_uop_ppred_busy_0; // @[rob.scala:211:7, :641:23]
wire [6:0] new_xcpt_uop_stale_pdst = io_lxcpt_bits_uop_stale_pdst_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_exception = io_lxcpt_bits_uop_exception_0; // @[rob.scala:211:7, :641:23]
wire [63:0] new_xcpt_uop_exc_cause = io_lxcpt_bits_uop_exc_cause_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bypassable = io_lxcpt_bits_uop_bypassable_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_uop_mem_cmd = io_lxcpt_bits_uop_mem_cmd_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_mem_size = io_lxcpt_bits_uop_mem_size_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_mem_signed = io_lxcpt_bits_uop_mem_signed_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_fence = io_lxcpt_bits_uop_is_fence_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_fencei = io_lxcpt_bits_uop_is_fencei_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_amo = io_lxcpt_bits_uop_is_amo_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_uses_ldq = io_lxcpt_bits_uop_uses_ldq_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_uses_stq = io_lxcpt_bits_uop_uses_stq_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_sys_pc2epc = io_lxcpt_bits_uop_is_sys_pc2epc_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_is_unique = io_lxcpt_bits_uop_is_unique_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_flush_on_commit = io_lxcpt_bits_uop_flush_on_commit_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ldst_is_rs1 = io_lxcpt_bits_uop_ldst_is_rs1_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_ldst = io_lxcpt_bits_uop_ldst_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs1 = io_lxcpt_bits_uop_lrs1_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs2 = io_lxcpt_bits_uop_lrs2_0; // @[rob.scala:211:7, :641:23]
wire [5:0] new_xcpt_uop_lrs3 = io_lxcpt_bits_uop_lrs3_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_ldst_val = io_lxcpt_bits_uop_ldst_val_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_dst_rtype = io_lxcpt_bits_uop_dst_rtype_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_lrs1_rtype = io_lxcpt_bits_uop_lrs1_rtype_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_lrs2_rtype = io_lxcpt_bits_uop_lrs2_rtype_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_frs3_en = io_lxcpt_bits_uop_frs3_en_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_fp_val = io_lxcpt_bits_uop_fp_val_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_fp_single = io_lxcpt_bits_uop_fp_single_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_pf_if = io_lxcpt_bits_uop_xcpt_pf_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_ae_if = io_lxcpt_bits_uop_xcpt_ae_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_xcpt_ma_if = io_lxcpt_bits_uop_xcpt_ma_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bp_debug_if = io_lxcpt_bits_uop_bp_debug_if_0; // @[rob.scala:211:7, :641:23]
wire new_xcpt_uop_bp_xcpt_if = io_lxcpt_bits_uop_bp_xcpt_if_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_debug_fsrc = io_lxcpt_bits_uop_debug_fsrc_0; // @[rob.scala:211:7, :641:23]
wire [1:0] new_xcpt_uop_debug_tsrc = io_lxcpt_bits_uop_debug_tsrc_0; // @[rob.scala:211:7, :641:23]
wire [4:0] new_xcpt_cause = io_lxcpt_bits_cause_0; // @[rob.scala:211:7, :641:23]
wire [39:0] new_xcpt_badvaddr = io_lxcpt_bits_badvaddr_0; // @[rob.scala:211:7, :641:23]
wire will_commit_0; // @[rob.scala:242:33]
wire will_commit_1; // @[rob.scala:242:33]
wire will_commit_2; // @[rob.scala:242:33]
wire _io_commit_arch_valids_0_T_1; // @[rob.scala:414:48]
wire _io_commit_arch_valids_1_T_1; // @[rob.scala:414:48]
wire _io_commit_arch_valids_2_T_1; // @[rob.scala:414:48]
wire _io_commit_fflags_valid_T_1; // @[rob.scala:623:48]
wire [4:0] _io_commit_fflags_bits_T_1; // @[rob.scala:624:44]
wire _io_commit_rbk_valids_0_T_2; // @[rob.scala:431:60]
wire _io_commit_rbk_valids_1_T_2; // @[rob.scala:431:60]
wire _io_commit_rbk_valids_2_T_2; // @[rob.scala:431:60]
wire _io_commit_rollback_T_2; // @[rob.scala:432:38]
wire _io_com_xcpt_valid_T_1; // @[rob.scala:561:41]
wire [4:0] com_xcpt_uop_ftq_idx; // @[Mux.scala:50:70]
wire com_xcpt_uop_edge_inst; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_rvc; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_pc_lob; // @[Mux.scala:50:70]
wire [63:0] _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:261:20]
wire flush_val; // @[rob.scala:578:36]
wire [4:0] flush_uop_ftq_idx; // @[rob.scala:583:22]
wire flush_uop_edge_inst; // @[rob.scala:583:22]
wire flush_uop_is_rvc; // @[rob.scala:583:22]
wire [5:0] flush_uop_pc_lob; // @[rob.scala:583:22]
wire [2:0] io_flush_bits_flush_typ_ret; // @[rob.scala:172:10]
wire empty; // @[rob.scala:240:26]
wire _io_ready_T_4; // @[rob.scala:803:56]
wire io_commit_valids_0_0; // @[rob.scala:211:7]
wire io_commit_valids_1_0; // @[rob.scala:211:7]
wire io_commit_valids_2_0; // @[rob.scala:211:7]
wire io_commit_arch_valids_0_0; // @[rob.scala:211:7]
wire io_commit_arch_valids_1_0; // @[rob.scala:211:7]
wire io_commit_arch_valids_2_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_0_ctrl_br_type_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_ctrl_op1_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_op2_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_imm_sel_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_ctrl_op_fcn_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_fcn_dw_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_ctrl_csr_cmd_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_load_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_sta_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ctrl_is_std_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_uopc_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_0_inst_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_0_debug_inst_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_rvc_0; // @[rob.scala:211:7]
wire [39:0] io_commit_uops_0_debug_pc_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_0_iq_type_0; // @[rob.scala:211:7]
wire [9:0] io_commit_uops_0_fu_code_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_iw_state_0; // @[rob.scala:211:7]
wire io_commit_uops_0_iw_p1_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_0_iw_p2_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_br_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_jalr_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_jal_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_sfb_0; // @[rob.scala:211:7]
wire [15:0] io_commit_uops_0_br_mask_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_0_br_tag_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_ftq_idx_0; // @[rob.scala:211:7]
wire io_commit_uops_0_edge_inst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_pc_lob_0; // @[rob.scala:211:7]
wire io_commit_uops_0_taken_0; // @[rob.scala:211:7]
wire [19:0] io_commit_uops_0_imm_packed_0; // @[rob.scala:211:7]
wire [11:0] io_commit_uops_0_csr_addr_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_rob_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_ldq_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_stq_idx_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_rxq_idx_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_pdst_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_prs1_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_prs2_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_prs3_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs1_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs2_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_0_prs3_busy_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_0_stale_pdst_0; // @[rob.scala:211:7]
wire io_commit_uops_0_exception_0; // @[rob.scala:211:7]
wire [63:0] io_commit_uops_0_exc_cause_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bypassable_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_0_mem_cmd_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_mem_size_0; // @[rob.scala:211:7]
wire io_commit_uops_0_mem_signed_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_fence_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_fencei_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_amo_0; // @[rob.scala:211:7]
wire io_commit_uops_0_uses_ldq_0; // @[rob.scala:211:7]
wire io_commit_uops_0_uses_stq_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_sys_pc2epc_0; // @[rob.scala:211:7]
wire io_commit_uops_0_is_unique_0; // @[rob.scala:211:7]
wire io_commit_uops_0_flush_on_commit_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ldst_is_rs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_ldst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs2_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_0_lrs3_0; // @[rob.scala:211:7]
wire io_commit_uops_0_ldst_val_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_dst_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_lrs1_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_lrs2_rtype_0; // @[rob.scala:211:7]
wire io_commit_uops_0_frs3_en_0; // @[rob.scala:211:7]
wire io_commit_uops_0_fp_val_0; // @[rob.scala:211:7]
wire io_commit_uops_0_fp_single_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_pf_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_ae_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_xcpt_ma_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bp_debug_if_0; // @[rob.scala:211:7]
wire io_commit_uops_0_bp_xcpt_if_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_debug_fsrc_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_0_debug_tsrc_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_1_ctrl_br_type_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_ctrl_op1_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_1_ctrl_op2_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_1_ctrl_imm_sel_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_ctrl_op_fcn_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ctrl_fcn_dw_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_1_ctrl_csr_cmd_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ctrl_is_load_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ctrl_is_sta_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ctrl_is_std_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_uopc_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_1_inst_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_1_debug_inst_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_rvc_0; // @[rob.scala:211:7]
wire [39:0] io_commit_uops_1_debug_pc_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_1_iq_type_0; // @[rob.scala:211:7]
wire [9:0] io_commit_uops_1_fu_code_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_iw_state_0; // @[rob.scala:211:7]
wire io_commit_uops_1_iw_p1_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_1_iw_p2_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_br_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_jalr_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_jal_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_sfb_0; // @[rob.scala:211:7]
wire [15:0] io_commit_uops_1_br_mask_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_1_br_tag_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_ftq_idx_0; // @[rob.scala:211:7]
wire io_commit_uops_1_edge_inst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_1_pc_lob_0; // @[rob.scala:211:7]
wire io_commit_uops_1_taken_0; // @[rob.scala:211:7]
wire [19:0] io_commit_uops_1_imm_packed_0; // @[rob.scala:211:7]
wire [11:0] io_commit_uops_1_csr_addr_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_rob_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_ldq_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_stq_idx_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_rxq_idx_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_pdst_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_prs1_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_prs2_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_prs3_0; // @[rob.scala:211:7]
wire io_commit_uops_1_prs1_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_1_prs2_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_1_prs3_busy_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_1_stale_pdst_0; // @[rob.scala:211:7]
wire io_commit_uops_1_exception_0; // @[rob.scala:211:7]
wire [63:0] io_commit_uops_1_exc_cause_0; // @[rob.scala:211:7]
wire io_commit_uops_1_bypassable_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_1_mem_cmd_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_mem_size_0; // @[rob.scala:211:7]
wire io_commit_uops_1_mem_signed_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_fence_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_fencei_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_amo_0; // @[rob.scala:211:7]
wire io_commit_uops_1_uses_ldq_0; // @[rob.scala:211:7]
wire io_commit_uops_1_uses_stq_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_sys_pc2epc_0; // @[rob.scala:211:7]
wire io_commit_uops_1_is_unique_0; // @[rob.scala:211:7]
wire io_commit_uops_1_flush_on_commit_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ldst_is_rs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_1_ldst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_1_lrs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_1_lrs2_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_1_lrs3_0; // @[rob.scala:211:7]
wire io_commit_uops_1_ldst_val_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_dst_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_lrs1_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_lrs2_rtype_0; // @[rob.scala:211:7]
wire io_commit_uops_1_frs3_en_0; // @[rob.scala:211:7]
wire io_commit_uops_1_fp_val_0; // @[rob.scala:211:7]
wire io_commit_uops_1_fp_single_0; // @[rob.scala:211:7]
wire io_commit_uops_1_xcpt_pf_if_0; // @[rob.scala:211:7]
wire io_commit_uops_1_xcpt_ae_if_0; // @[rob.scala:211:7]
wire io_commit_uops_1_xcpt_ma_if_0; // @[rob.scala:211:7]
wire io_commit_uops_1_bp_debug_if_0; // @[rob.scala:211:7]
wire io_commit_uops_1_bp_xcpt_if_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_debug_fsrc_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_1_debug_tsrc_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_2_ctrl_br_type_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_ctrl_op1_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_2_ctrl_op2_sel_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_2_ctrl_imm_sel_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_ctrl_op_fcn_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ctrl_fcn_dw_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_2_ctrl_csr_cmd_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ctrl_is_load_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ctrl_is_sta_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ctrl_is_std_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_uopc_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_2_inst_0; // @[rob.scala:211:7]
wire [31:0] io_commit_uops_2_debug_inst_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_rvc_0; // @[rob.scala:211:7]
wire [39:0] io_commit_uops_2_debug_pc_0; // @[rob.scala:211:7]
wire [2:0] io_commit_uops_2_iq_type_0; // @[rob.scala:211:7]
wire [9:0] io_commit_uops_2_fu_code_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_iw_state_0; // @[rob.scala:211:7]
wire io_commit_uops_2_iw_p1_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_2_iw_p2_poisoned_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_br_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_jalr_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_jal_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_sfb_0; // @[rob.scala:211:7]
wire [15:0] io_commit_uops_2_br_mask_0; // @[rob.scala:211:7]
wire [3:0] io_commit_uops_2_br_tag_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_ftq_idx_0; // @[rob.scala:211:7]
wire io_commit_uops_2_edge_inst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_2_pc_lob_0; // @[rob.scala:211:7]
wire io_commit_uops_2_taken_0; // @[rob.scala:211:7]
wire [19:0] io_commit_uops_2_imm_packed_0; // @[rob.scala:211:7]
wire [11:0] io_commit_uops_2_csr_addr_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_rob_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_ldq_idx_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_stq_idx_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_rxq_idx_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_pdst_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_prs1_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_prs2_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_prs3_0; // @[rob.scala:211:7]
wire io_commit_uops_2_prs1_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_2_prs2_busy_0; // @[rob.scala:211:7]
wire io_commit_uops_2_prs3_busy_0; // @[rob.scala:211:7]
wire [6:0] io_commit_uops_2_stale_pdst_0; // @[rob.scala:211:7]
wire io_commit_uops_2_exception_0; // @[rob.scala:211:7]
wire [63:0] io_commit_uops_2_exc_cause_0; // @[rob.scala:211:7]
wire io_commit_uops_2_bypassable_0; // @[rob.scala:211:7]
wire [4:0] io_commit_uops_2_mem_cmd_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_mem_size_0; // @[rob.scala:211:7]
wire io_commit_uops_2_mem_signed_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_fence_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_fencei_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_amo_0; // @[rob.scala:211:7]
wire io_commit_uops_2_uses_ldq_0; // @[rob.scala:211:7]
wire io_commit_uops_2_uses_stq_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_sys_pc2epc_0; // @[rob.scala:211:7]
wire io_commit_uops_2_is_unique_0; // @[rob.scala:211:7]
wire io_commit_uops_2_flush_on_commit_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ldst_is_rs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_2_ldst_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_2_lrs1_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_2_lrs2_0; // @[rob.scala:211:7]
wire [5:0] io_commit_uops_2_lrs3_0; // @[rob.scala:211:7]
wire io_commit_uops_2_ldst_val_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_dst_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_lrs1_rtype_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_lrs2_rtype_0; // @[rob.scala:211:7]
wire io_commit_uops_2_frs3_en_0; // @[rob.scala:211:7]
wire io_commit_uops_2_fp_val_0; // @[rob.scala:211:7]
wire io_commit_uops_2_fp_single_0; // @[rob.scala:211:7]
wire io_commit_uops_2_xcpt_pf_if_0; // @[rob.scala:211:7]
wire io_commit_uops_2_xcpt_ae_if_0; // @[rob.scala:211:7]
wire io_commit_uops_2_xcpt_ma_if_0; // @[rob.scala:211:7]
wire io_commit_uops_2_bp_debug_if_0; // @[rob.scala:211:7]
wire io_commit_uops_2_bp_xcpt_if_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_debug_fsrc_0; // @[rob.scala:211:7]
wire [1:0] io_commit_uops_2_debug_tsrc_0; // @[rob.scala:211:7]
wire io_commit_fflags_valid_0; // @[rob.scala:211:7]
wire [4:0] io_commit_fflags_bits_0; // @[rob.scala:211:7]
wire [31:0] io_commit_debug_insts_0_0; // @[rob.scala:211:7]
wire [31:0] io_commit_debug_insts_1_0; // @[rob.scala:211:7]
wire [31:0] io_commit_debug_insts_2_0; // @[rob.scala:211:7]
wire io_commit_rbk_valids_0_0; // @[rob.scala:211:7]
wire io_commit_rbk_valids_1_0; // @[rob.scala:211:7]
wire io_commit_rbk_valids_2_0; // @[rob.scala:211:7]
wire [63:0] io_commit_debug_wdata_0_0; // @[rob.scala:211:7]
wire [63:0] io_commit_debug_wdata_1_0; // @[rob.scala:211:7]
wire [63:0] io_commit_debug_wdata_2_0; // @[rob.scala:211:7]
wire io_commit_rollback_0; // @[rob.scala:211:7]
wire [4:0] io_com_xcpt_bits_ftq_idx_0; // @[rob.scala:211:7]
wire io_com_xcpt_bits_edge_inst_0; // @[rob.scala:211:7]
wire io_com_xcpt_bits_is_rvc; // @[rob.scala:211:7]
wire [5:0] io_com_xcpt_bits_pc_lob_0; // @[rob.scala:211:7]
wire [63:0] io_com_xcpt_bits_cause_0; // @[rob.scala:211:7]
wire [63:0] io_com_xcpt_bits_badvaddr_0; // @[rob.scala:211:7]
wire io_com_xcpt_valid_0; // @[rob.scala:211:7]
wire [4:0] io_flush_bits_ftq_idx_0; // @[rob.scala:211:7]
wire io_flush_bits_edge_inst_0; // @[rob.scala:211:7]
wire io_flush_bits_is_rvc_0; // @[rob.scala:211:7]
wire [5:0] io_flush_bits_pc_lob_0; // @[rob.scala:211:7]
wire [2:0] io_flush_bits_flush_typ_0; // @[rob.scala:211:7]
wire io_flush_valid_0; // @[rob.scala:211:7]
wire [6:0] io_rob_tail_idx_0; // @[rob.scala:211:7]
wire [6:0] io_rob_pnr_idx_0; // @[rob.scala:211:7]
wire [6:0] io_rob_head_idx_0; // @[rob.scala:211:7]
wire io_com_load_is_at_rob_head_0; // @[rob.scala:211:7]
wire io_empty_0; // @[rob.scala:211:7]
wire io_ready_0; // @[rob.scala:211:7]
wire io_flush_frontend_0; // @[rob.scala:211:7]
reg [1:0] rob_state; // @[rob.scala:220:26]
reg [4:0] rob_head; // @[rob.scala:223:29]
wire [4:0] _rob_debug_inst_rdata_WIRE = rob_head; // @[rob.scala:223:29, :300:53]
reg [1:0] rob_head_lsb; // @[rob.scala:224:29]
assign rob_head_idx = {rob_head, rob_head_lsb}; // @[rob.scala:223:29, :224:29, :225:59]
assign io_rob_head_idx_0 = rob_head_idx; // @[rob.scala:211:7, :225:59]
reg [4:0] rob_tail; // @[rob.scala:227:29]
reg [1:0] rob_tail_lsb; // @[rob.scala:228:29]
assign rob_tail_idx = {rob_tail, rob_tail_lsb}; // @[rob.scala:227:29, :228:29, :229:59]
assign io_rob_tail_idx_0 = rob_tail_idx; // @[rob.scala:211:7, :229:59]
reg [4:0] rob_pnr; // @[rob.scala:231:29]
reg [1:0] rob_pnr_lsb; // @[rob.scala:232:29]
assign rob_pnr_idx = {rob_pnr, rob_pnr_lsb}; // @[rob.scala:231:29, :232:29, :233:59]
assign io_rob_pnr_idx_0 = rob_pnr_idx; // @[rob.scala:211:7, :233:59]
wire _T_1432 = rob_state == 2'h2; // @[rob.scala:220:26, :235:31]
wire _com_idx_T; // @[rob.scala:235:31]
assign _com_idx_T = _T_1432; // @[rob.scala:235:31]
wire _rbk_row_T; // @[rob.scala:429:29]
assign _rbk_row_T = _T_1432; // @[rob.scala:235:31, :429:29]
wire _io_commit_rollback_T; // @[rob.scala:432:38]
assign _io_commit_rollback_T = _T_1432; // @[rob.scala:235:31, :432:38]
wire _rbk_row_T_2; // @[rob.scala:429:29]
assign _rbk_row_T_2 = _T_1432; // @[rob.scala:235:31, :429:29]
wire _io_commit_rollback_T_1; // @[rob.scala:432:38]
assign _io_commit_rollback_T_1 = _T_1432; // @[rob.scala:235:31, :432:38]
wire _rbk_row_T_4; // @[rob.scala:429:29]
assign _rbk_row_T_4 = _T_1432; // @[rob.scala:235:31, :429:29]
assign _io_commit_rollback_T_2 = _T_1432; // @[rob.scala:235:31, :432:38]
wire [4:0] com_idx = _com_idx_T ? rob_tail : rob_head; // @[rob.scala:223:29, :227:29, :235:{20,31}]
reg maybe_full; // @[rob.scala:238:29]
wire _full_T_1; // @[rob.scala:796:39]
wire full; // @[rob.scala:239:26]
wire _empty_T_3; // @[rob.scala:797:41]
assign io_empty_0 = empty; // @[rob.scala:211:7, :240:26]
wire _will_commit_0_T_3; // @[rob.scala:551:70]
assign io_commit_valids_0_0 = will_commit_0; // @[rob.scala:211:7, :242:33]
wire _will_commit_1_T_3; // @[rob.scala:551:70]
assign io_commit_valids_1_0 = will_commit_1; // @[rob.scala:211:7, :242:33]
wire _will_commit_2_T_3; // @[rob.scala:551:70]
assign io_commit_valids_2_0 = will_commit_2; // @[rob.scala:211:7, :242:33]
wire _can_commit_0_T_3; // @[rob.scala:408:64]
wire _can_commit_1_T_3; // @[rob.scala:408:64]
wire _can_commit_2_T_3; // @[rob.scala:408:64]
wire can_commit_0; // @[rob.scala:243:33]
wire can_commit_1; // @[rob.scala:243:33]
wire can_commit_2; // @[rob.scala:243:33]
wire _can_throw_exception_0_T; // @[rob.scala:402:49]
wire _can_throw_exception_1_T; // @[rob.scala:402:49]
wire _can_throw_exception_2_T; // @[rob.scala:402:49]
wire can_throw_exception_0; // @[rob.scala:244:33]
wire can_throw_exception_1; // @[rob.scala:244:33]
wire can_throw_exception_2; // @[rob.scala:244:33]
wire _rob_pnr_unsafe_0_T_1; // @[rob.scala:497:43]
wire _rob_pnr_unsafe_1_T_1; // @[rob.scala:497:43]
wire _rob_pnr_unsafe_2_T_1; // @[rob.scala:497:43]
wire rob_pnr_unsafe_0; // @[rob.scala:246:33]
wire rob_pnr_unsafe_1; // @[rob.scala:246:33]
wire rob_pnr_unsafe_2; // @[rob.scala:246:33]
wire rob_head_vals_0; // @[rob.scala:247:33]
wire rob_head_vals_1; // @[rob.scala:247:33]
wire rob_head_vals_2; // @[rob.scala:247:33]
wire rob_tail_vals_0; // @[rob.scala:248:33]
wire rob_tail_vals_1; // @[rob.scala:248:33]
wire rob_tail_vals_2; // @[rob.scala:248:33]
wire rob_head_uses_stq_0; // @[rob.scala:249:33]
wire rob_head_uses_stq_1; // @[rob.scala:249:33]
wire rob_head_uses_stq_2; // @[rob.scala:249:33]
wire rob_head_uses_ldq_0; // @[rob.scala:250:33]
wire rob_head_uses_ldq_1; // @[rob.scala:250:33]
wire rob_head_uses_ldq_2; // @[rob.scala:250:33]
wire [4:0] rob_head_fflags_0; // @[rob.scala:251:33]
wire [4:0] rob_head_fflags_1; // @[rob.scala:251:33]
wire [4:0] rob_head_fflags_2; // @[rob.scala:251:33]
wire exception_thrown; // @[rob.scala:253:30]
reg r_xcpt_val; // @[rob.scala:257:33]
assign io_flush_frontend_0 = r_xcpt_val; // @[rob.scala:211:7, :257:33]
reg [6:0] r_xcpt_uop_uopc; // @[rob.scala:258:29]
reg [31:0] r_xcpt_uop_inst; // @[rob.scala:258:29]
reg [31:0] r_xcpt_uop_debug_inst; // @[rob.scala:258:29]
reg r_xcpt_uop_is_rvc; // @[rob.scala:258:29]
reg [39:0] r_xcpt_uop_debug_pc; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_iq_type; // @[rob.scala:258:29]
reg [9:0] r_xcpt_uop_fu_code; // @[rob.scala:258:29]
reg [3:0] r_xcpt_uop_ctrl_br_type; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:258:29]
reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_load; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_sta; // @[rob.scala:258:29]
reg r_xcpt_uop_ctrl_is_std; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_iw_state; // @[rob.scala:258:29]
reg r_xcpt_uop_iw_p1_poisoned; // @[rob.scala:258:29]
reg r_xcpt_uop_iw_p2_poisoned; // @[rob.scala:258:29]
reg r_xcpt_uop_is_br; // @[rob.scala:258:29]
reg r_xcpt_uop_is_jalr; // @[rob.scala:258:29]
reg r_xcpt_uop_is_jal; // @[rob.scala:258:29]
reg r_xcpt_uop_is_sfb; // @[rob.scala:258:29]
reg [15:0] r_xcpt_uop_br_mask; // @[rob.scala:258:29]
reg [3:0] r_xcpt_uop_br_tag; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_ftq_idx; // @[rob.scala:258:29]
reg r_xcpt_uop_edge_inst; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_pc_lob; // @[rob.scala:258:29]
reg r_xcpt_uop_taken; // @[rob.scala:258:29]
reg [19:0] r_xcpt_uop_imm_packed; // @[rob.scala:258:29]
reg [11:0] r_xcpt_uop_csr_addr; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_rob_idx; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_ldq_idx; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_stq_idx; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_rxq_idx; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_pdst; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_prs1; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_prs2; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_prs3; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_ppred; // @[rob.scala:258:29]
reg r_xcpt_uop_prs1_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_prs2_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_prs3_busy; // @[rob.scala:258:29]
reg r_xcpt_uop_ppred_busy; // @[rob.scala:258:29]
reg [6:0] r_xcpt_uop_stale_pdst; // @[rob.scala:258:29]
reg r_xcpt_uop_exception; // @[rob.scala:258:29]
reg [63:0] r_xcpt_uop_exc_cause; // @[rob.scala:258:29]
assign io_com_xcpt_bits_cause_0 = r_xcpt_uop_exc_cause; // @[rob.scala:211:7, :258:29]
reg r_xcpt_uop_bypassable; // @[rob.scala:258:29]
reg [4:0] r_xcpt_uop_mem_cmd; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_mem_size; // @[rob.scala:258:29]
reg r_xcpt_uop_mem_signed; // @[rob.scala:258:29]
reg r_xcpt_uop_is_fence; // @[rob.scala:258:29]
reg r_xcpt_uop_is_fencei; // @[rob.scala:258:29]
reg r_xcpt_uop_is_amo; // @[rob.scala:258:29]
reg r_xcpt_uop_uses_ldq; // @[rob.scala:258:29]
reg r_xcpt_uop_uses_stq; // @[rob.scala:258:29]
reg r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:258:29]
reg r_xcpt_uop_is_unique; // @[rob.scala:258:29]
reg r_xcpt_uop_flush_on_commit; // @[rob.scala:258:29]
reg r_xcpt_uop_ldst_is_rs1; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_ldst; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs1; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs2; // @[rob.scala:258:29]
reg [5:0] r_xcpt_uop_lrs3; // @[rob.scala:258:29]
reg r_xcpt_uop_ldst_val; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_dst_rtype; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_lrs1_rtype; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_lrs2_rtype; // @[rob.scala:258:29]
reg r_xcpt_uop_frs3_en; // @[rob.scala:258:29]
reg r_xcpt_uop_fp_val; // @[rob.scala:258:29]
reg r_xcpt_uop_fp_single; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_pf_if; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_ae_if; // @[rob.scala:258:29]
reg r_xcpt_uop_xcpt_ma_if; // @[rob.scala:258:29]
reg r_xcpt_uop_bp_debug_if; // @[rob.scala:258:29]
reg r_xcpt_uop_bp_xcpt_if; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_debug_fsrc; // @[rob.scala:258:29]
reg [1:0] r_xcpt_uop_debug_tsrc; // @[rob.scala:258:29]
reg [39:0] r_xcpt_badvaddr; // @[rob.scala:259:29]
wire _rob_unsafe_masked_0_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_1_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_2_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_4_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_5_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_6_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_8_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_9_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_10_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_12_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_13_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_14_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_16_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_17_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_18_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_20_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_21_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_22_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_24_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_25_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_26_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_28_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_29_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_30_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_32_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_33_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_34_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_36_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_37_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_38_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_40_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_41_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_42_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_44_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_45_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_46_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_48_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_49_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_50_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_52_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_53_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_54_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_56_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_57_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_58_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_60_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_61_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_62_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_64_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_65_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_66_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_68_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_69_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_70_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_72_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_73_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_74_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_76_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_77_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_78_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_80_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_81_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_82_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_84_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_85_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_86_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_88_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_89_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_90_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_92_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_93_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_94_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_96_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_97_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_98_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_100_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_101_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_102_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_104_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_105_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_106_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_108_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_109_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_110_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_112_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_113_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_114_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_116_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_117_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_118_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_120_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_121_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_122_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_124_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_125_T_1; // @[rob.scala:494:71]
wire _rob_unsafe_masked_126_T_1; // @[rob.scala:494:71]
wire rob_unsafe_masked_0; // @[rob.scala:293:35]
wire rob_unsafe_masked_1; // @[rob.scala:293:35]
wire rob_unsafe_masked_2; // @[rob.scala:293:35]
wire rob_unsafe_masked_4; // @[rob.scala:293:35]
wire rob_unsafe_masked_5; // @[rob.scala:293:35]
wire rob_unsafe_masked_6; // @[rob.scala:293:35]
wire rob_unsafe_masked_8; // @[rob.scala:293:35]
wire rob_unsafe_masked_9; // @[rob.scala:293:35]
wire rob_unsafe_masked_10; // @[rob.scala:293:35]
wire rob_unsafe_masked_12; // @[rob.scala:293:35]
wire rob_unsafe_masked_13; // @[rob.scala:293:35]
wire rob_unsafe_masked_14; // @[rob.scala:293:35]
wire rob_unsafe_masked_16; // @[rob.scala:293:35]
wire rob_unsafe_masked_17; // @[rob.scala:293:35]
wire rob_unsafe_masked_18; // @[rob.scala:293:35]
wire rob_unsafe_masked_20; // @[rob.scala:293:35]
wire rob_unsafe_masked_21; // @[rob.scala:293:35]
wire rob_unsafe_masked_22; // @[rob.scala:293:35]
wire rob_unsafe_masked_24; // @[rob.scala:293:35]
wire rob_unsafe_masked_25; // @[rob.scala:293:35]
wire rob_unsafe_masked_26; // @[rob.scala:293:35]
wire rob_unsafe_masked_28; // @[rob.scala:293:35]
wire rob_unsafe_masked_29; // @[rob.scala:293:35]
wire rob_unsafe_masked_30; // @[rob.scala:293:35]
wire rob_unsafe_masked_32; // @[rob.scala:293:35]
wire rob_unsafe_masked_33; // @[rob.scala:293:35]
wire rob_unsafe_masked_34; // @[rob.scala:293:35]
wire rob_unsafe_masked_36; // @[rob.scala:293:35]
wire rob_unsafe_masked_37; // @[rob.scala:293:35]
wire rob_unsafe_masked_38; // @[rob.scala:293:35]
wire rob_unsafe_masked_40; // @[rob.scala:293:35]
wire rob_unsafe_masked_41; // @[rob.scala:293:35]
wire rob_unsafe_masked_42; // @[rob.scala:293:35]
wire rob_unsafe_masked_44; // @[rob.scala:293:35]
wire rob_unsafe_masked_45; // @[rob.scala:293:35]
wire rob_unsafe_masked_46; // @[rob.scala:293:35]
wire rob_unsafe_masked_48; // @[rob.scala:293:35]
wire rob_unsafe_masked_49; // @[rob.scala:293:35]
wire rob_unsafe_masked_50; // @[rob.scala:293:35]
wire rob_unsafe_masked_52; // @[rob.scala:293:35]
wire rob_unsafe_masked_53; // @[rob.scala:293:35]
wire rob_unsafe_masked_54; // @[rob.scala:293:35]
wire rob_unsafe_masked_56; // @[rob.scala:293:35]
wire rob_unsafe_masked_57; // @[rob.scala:293:35]
wire rob_unsafe_masked_58; // @[rob.scala:293:35]
wire rob_unsafe_masked_60; // @[rob.scala:293:35]
wire rob_unsafe_masked_61; // @[rob.scala:293:35]
wire rob_unsafe_masked_62; // @[rob.scala:293:35]
wire rob_unsafe_masked_64; // @[rob.scala:293:35]
wire rob_unsafe_masked_65; // @[rob.scala:293:35]
wire rob_unsafe_masked_66; // @[rob.scala:293:35]
wire rob_unsafe_masked_68; // @[rob.scala:293:35]
wire rob_unsafe_masked_69; // @[rob.scala:293:35]
wire rob_unsafe_masked_70; // @[rob.scala:293:35]
wire rob_unsafe_masked_72; // @[rob.scala:293:35]
wire rob_unsafe_masked_73; // @[rob.scala:293:35]
wire rob_unsafe_masked_74; // @[rob.scala:293:35]
wire rob_unsafe_masked_76; // @[rob.scala:293:35]
wire rob_unsafe_masked_77; // @[rob.scala:293:35]
wire rob_unsafe_masked_78; // @[rob.scala:293:35]
wire rob_unsafe_masked_80; // @[rob.scala:293:35]
wire rob_unsafe_masked_81; // @[rob.scala:293:35]
wire rob_unsafe_masked_82; // @[rob.scala:293:35]
wire rob_unsafe_masked_84; // @[rob.scala:293:35]
wire rob_unsafe_masked_85; // @[rob.scala:293:35]
wire rob_unsafe_masked_86; // @[rob.scala:293:35]
wire rob_unsafe_masked_88; // @[rob.scala:293:35]
wire rob_unsafe_masked_89; // @[rob.scala:293:35]
wire rob_unsafe_masked_90; // @[rob.scala:293:35]
wire rob_unsafe_masked_92; // @[rob.scala:293:35]
wire rob_unsafe_masked_93; // @[rob.scala:293:35]
wire rob_unsafe_masked_94; // @[rob.scala:293:35]
wire rob_unsafe_masked_96; // @[rob.scala:293:35]
wire rob_unsafe_masked_97; // @[rob.scala:293:35]
wire rob_unsafe_masked_98; // @[rob.scala:293:35]
wire rob_unsafe_masked_100; // @[rob.scala:293:35]
wire rob_unsafe_masked_101; // @[rob.scala:293:35]
wire rob_unsafe_masked_102; // @[rob.scala:293:35]
wire rob_unsafe_masked_104; // @[rob.scala:293:35]
wire rob_unsafe_masked_105; // @[rob.scala:293:35]
wire rob_unsafe_masked_106; // @[rob.scala:293:35]
wire rob_unsafe_masked_108; // @[rob.scala:293:35]
wire rob_unsafe_masked_109; // @[rob.scala:293:35]
wire rob_unsafe_masked_110; // @[rob.scala:293:35]
wire rob_unsafe_masked_112; // @[rob.scala:293:35]
wire rob_unsafe_masked_113; // @[rob.scala:293:35]
wire rob_unsafe_masked_114; // @[rob.scala:293:35]
wire rob_unsafe_masked_116; // @[rob.scala:293:35]
wire rob_unsafe_masked_117; // @[rob.scala:293:35]
wire rob_unsafe_masked_118; // @[rob.scala:293:35]
wire rob_unsafe_masked_120; // @[rob.scala:293:35]
wire rob_unsafe_masked_121; // @[rob.scala:293:35]
wire rob_unsafe_masked_122; // @[rob.scala:293:35]
wire rob_unsafe_masked_124; // @[rob.scala:293:35]
wire rob_unsafe_masked_125; // @[rob.scala:293:35]
wire rob_unsafe_masked_126; // @[rob.scala:293:35]
assign io_commit_debug_insts_0_0 = _rob_debug_inst_mem_R0_data[31:0]; // @[rob.scala:211:7, :296:41]
assign io_commit_debug_insts_1_0 = _rob_debug_inst_mem_R0_data[63:32]; // @[rob.scala:211:7, :296:41]
assign io_commit_debug_insts_2_0 = _rob_debug_inst_mem_R0_data[95:64]; // @[rob.scala:211:7, :296:41]
wire _GEN = will_commit_0 | will_commit_1; // @[rob.scala:242:33, :300:84]
wire _rob_debug_inst_rdata_T; // @[rob.scala:300:84]
assign _rob_debug_inst_rdata_T = _GEN; // @[rob.scala:300:84]
wire _io_com_load_is_at_rob_head_T_6; // @[rob.scala:875:62]
assign _io_com_load_is_at_rob_head_T_6 = _GEN; // @[rob.scala:300:84, :875:62]
wire _rob_debug_inst_rdata_T_1 = _rob_debug_inst_rdata_T | will_commit_2; // @[rob.scala:242:33, :300:84]
reg [4:0] rob_fflags_0_0; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_1; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_2; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_3; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_4; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_5; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_6; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_7; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_8; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_9; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_10; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_11; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_12; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_13; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_14; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_15; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_16; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_17; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_18; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_19; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_20; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_21; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_22; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_23; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_24; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_25; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_26; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_27; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_28; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_29; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_30; // @[rob.scala:302:46]
reg [4:0] rob_fflags_0_31; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_0; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_1; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_2; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_3; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_4; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_5; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_6; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_7; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_8; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_9; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_10; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_11; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_12; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_13; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_14; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_15; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_16; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_17; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_18; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_19; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_20; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_21; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_22; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_23; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_24; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_25; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_26; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_27; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_28; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_29; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_30; // @[rob.scala:302:46]
reg [4:0] rob_fflags_1_31; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_0; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_1; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_2; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_3; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_4; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_5; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_6; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_7; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_8; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_9; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_10; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_11; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_12; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_13; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_14; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_15; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_16; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_17; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_18; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_19; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_20; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_21; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_22; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_23; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_24; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_25; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_26; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_27; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_28; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_29; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_30; // @[rob.scala:302:46]
reg [4:0] rob_fflags_2_31; // @[rob.scala:302:46]
reg rob_val_0; // @[rob.scala:308:32]
reg rob_val_1; // @[rob.scala:308:32]
reg rob_val_2; // @[rob.scala:308:32]
reg rob_val_3; // @[rob.scala:308:32]
reg rob_val_4; // @[rob.scala:308:32]
reg rob_val_5; // @[rob.scala:308:32]
reg rob_val_6; // @[rob.scala:308:32]
reg rob_val_7; // @[rob.scala:308:32]
reg rob_val_8; // @[rob.scala:308:32]
reg rob_val_9; // @[rob.scala:308:32]
reg rob_val_10; // @[rob.scala:308:32]
reg rob_val_11; // @[rob.scala:308:32]
reg rob_val_12; // @[rob.scala:308:32]
reg rob_val_13; // @[rob.scala:308:32]
reg rob_val_14; // @[rob.scala:308:32]
reg rob_val_15; // @[rob.scala:308:32]
reg rob_val_16; // @[rob.scala:308:32]
reg rob_val_17; // @[rob.scala:308:32]
reg rob_val_18; // @[rob.scala:308:32]
reg rob_val_19; // @[rob.scala:308:32]
reg rob_val_20; // @[rob.scala:308:32]
reg rob_val_21; // @[rob.scala:308:32]
reg rob_val_22; // @[rob.scala:308:32]
reg rob_val_23; // @[rob.scala:308:32]
reg rob_val_24; // @[rob.scala:308:32]
reg rob_val_25; // @[rob.scala:308:32]
reg rob_val_26; // @[rob.scala:308:32]
reg rob_val_27; // @[rob.scala:308:32]
reg rob_val_28; // @[rob.scala:308:32]
reg rob_val_29; // @[rob.scala:308:32]
reg rob_val_30; // @[rob.scala:308:32]
reg rob_val_31; // @[rob.scala:308:32]
reg rob_bsy_0; // @[rob.scala:309:28]
reg rob_bsy_1; // @[rob.scala:309:28]
reg rob_bsy_2; // @[rob.scala:309:28]
reg rob_bsy_3; // @[rob.scala:309:28]
reg rob_bsy_4; // @[rob.scala:309:28]
reg rob_bsy_5; // @[rob.scala:309:28]
reg rob_bsy_6; // @[rob.scala:309:28]
reg rob_bsy_7; // @[rob.scala:309:28]
reg rob_bsy_8; // @[rob.scala:309:28]
reg rob_bsy_9; // @[rob.scala:309:28]
reg rob_bsy_10; // @[rob.scala:309:28]
reg rob_bsy_11; // @[rob.scala:309:28]
reg rob_bsy_12; // @[rob.scala:309:28]
reg rob_bsy_13; // @[rob.scala:309:28]
reg rob_bsy_14; // @[rob.scala:309:28]
reg rob_bsy_15; // @[rob.scala:309:28]
reg rob_bsy_16; // @[rob.scala:309:28]
reg rob_bsy_17; // @[rob.scala:309:28]
reg rob_bsy_18; // @[rob.scala:309:28]
reg rob_bsy_19; // @[rob.scala:309:28]
reg rob_bsy_20; // @[rob.scala:309:28]
reg rob_bsy_21; // @[rob.scala:309:28]
reg rob_bsy_22; // @[rob.scala:309:28]
reg rob_bsy_23; // @[rob.scala:309:28]
reg rob_bsy_24; // @[rob.scala:309:28]
reg rob_bsy_25; // @[rob.scala:309:28]
reg rob_bsy_26; // @[rob.scala:309:28]
reg rob_bsy_27; // @[rob.scala:309:28]
reg rob_bsy_28; // @[rob.scala:309:28]
reg rob_bsy_29; // @[rob.scala:309:28]
reg rob_bsy_30; // @[rob.scala:309:28]
reg rob_bsy_31; // @[rob.scala:309:28]
reg rob_unsafe_0; // @[rob.scala:310:28]
reg rob_unsafe_1; // @[rob.scala:310:28]
reg rob_unsafe_2; // @[rob.scala:310:28]
reg rob_unsafe_3; // @[rob.scala:310:28]
reg rob_unsafe_4; // @[rob.scala:310:28]
reg rob_unsafe_5; // @[rob.scala:310:28]
reg rob_unsafe_6; // @[rob.scala:310:28]
reg rob_unsafe_7; // @[rob.scala:310:28]
reg rob_unsafe_8; // @[rob.scala:310:28]
reg rob_unsafe_9; // @[rob.scala:310:28]
reg rob_unsafe_10; // @[rob.scala:310:28]
reg rob_unsafe_11; // @[rob.scala:310:28]
reg rob_unsafe_12; // @[rob.scala:310:28]
reg rob_unsafe_13; // @[rob.scala:310:28]
reg rob_unsafe_14; // @[rob.scala:310:28]
reg rob_unsafe_15; // @[rob.scala:310:28]
reg rob_unsafe_16; // @[rob.scala:310:28]
reg rob_unsafe_17; // @[rob.scala:310:28]
reg rob_unsafe_18; // @[rob.scala:310:28]
reg rob_unsafe_19; // @[rob.scala:310:28]
reg rob_unsafe_20; // @[rob.scala:310:28]
reg rob_unsafe_21; // @[rob.scala:310:28]
reg rob_unsafe_22; // @[rob.scala:310:28]
reg rob_unsafe_23; // @[rob.scala:310:28]
reg rob_unsafe_24; // @[rob.scala:310:28]
reg rob_unsafe_25; // @[rob.scala:310:28]
reg rob_unsafe_26; // @[rob.scala:310:28]
reg rob_unsafe_27; // @[rob.scala:310:28]
reg rob_unsafe_28; // @[rob.scala:310:28]
reg rob_unsafe_29; // @[rob.scala:310:28]
reg rob_unsafe_30; // @[rob.scala:310:28]
reg rob_unsafe_31; // @[rob.scala:310:28]
reg [6:0] rob_uop_0_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_0_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_0_debug_inst; // @[rob.scala:311:28]
reg rob_uop_0_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_0_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_0_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_0_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_0_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_0_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_iw_state; // @[rob.scala:311:28]
reg rob_uop_0_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_0_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_0_is_br; // @[rob.scala:311:28]
reg rob_uop_0_is_jalr; // @[rob.scala:311:28]
reg rob_uop_0_is_jal; // @[rob.scala:311:28]
reg rob_uop_0_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_0_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_0_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_0_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_pc_lob; // @[rob.scala:311:28]
reg rob_uop_0_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_0_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_0_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_prs3; // @[rob.scala:311:28]
reg rob_uop_0_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_0_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_0_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_0_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_0_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_0_exc_cause; // @[rob.scala:311:28]
reg rob_uop_0_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_0_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_mem_size; // @[rob.scala:311:28]
reg rob_uop_0_mem_signed; // @[rob.scala:311:28]
reg rob_uop_0_is_fence; // @[rob.scala:311:28]
reg rob_uop_0_is_fencei; // @[rob.scala:311:28]
reg rob_uop_0_is_amo; // @[rob.scala:311:28]
reg rob_uop_0_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_0_uses_stq; // @[rob.scala:311:28]
reg rob_uop_0_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_0_is_unique; // @[rob.scala:311:28]
reg rob_uop_0_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_0_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_0_lrs3; // @[rob.scala:311:28]
reg rob_uop_0_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_0_frs3_en; // @[rob.scala:311:28]
reg rob_uop_0_fp_val; // @[rob.scala:311:28]
reg rob_uop_0_fp_single; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_0_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_0_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_0_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_0_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_is_br; // @[rob.scala:311:28]
reg rob_uop_1_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_prs3; // @[rob.scala:311:28]
reg rob_uop_1_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_is_br; // @[rob.scala:311:28]
reg rob_uop_2_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_prs3; // @[rob.scala:311:28]
reg rob_uop_2_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_3_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_3_debug_inst; // @[rob.scala:311:28]
reg rob_uop_3_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_3_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_3_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_3_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_3_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_3_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_iw_state; // @[rob.scala:311:28]
reg rob_uop_3_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_3_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_3_is_br; // @[rob.scala:311:28]
reg rob_uop_3_is_jalr; // @[rob.scala:311:28]
reg rob_uop_3_is_jal; // @[rob.scala:311:28]
reg rob_uop_3_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_3_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_3_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_3_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_pc_lob; // @[rob.scala:311:28]
reg rob_uop_3_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_3_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_3_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_prs3; // @[rob.scala:311:28]
reg rob_uop_3_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_3_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_3_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_3_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_3_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_3_exc_cause; // @[rob.scala:311:28]
reg rob_uop_3_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_3_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_mem_size; // @[rob.scala:311:28]
reg rob_uop_3_mem_signed; // @[rob.scala:311:28]
reg rob_uop_3_is_fence; // @[rob.scala:311:28]
reg rob_uop_3_is_fencei; // @[rob.scala:311:28]
reg rob_uop_3_is_amo; // @[rob.scala:311:28]
reg rob_uop_3_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_3_uses_stq; // @[rob.scala:311:28]
reg rob_uop_3_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_3_is_unique; // @[rob.scala:311:28]
reg rob_uop_3_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_3_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_3_lrs3; // @[rob.scala:311:28]
reg rob_uop_3_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_3_frs3_en; // @[rob.scala:311:28]
reg rob_uop_3_fp_val; // @[rob.scala:311:28]
reg rob_uop_3_fp_single; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_3_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_3_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_3_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_3_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_4_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_4_debug_inst; // @[rob.scala:311:28]
reg rob_uop_4_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_4_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_4_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_4_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_4_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_4_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_iw_state; // @[rob.scala:311:28]
reg rob_uop_4_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_4_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_4_is_br; // @[rob.scala:311:28]
reg rob_uop_4_is_jalr; // @[rob.scala:311:28]
reg rob_uop_4_is_jal; // @[rob.scala:311:28]
reg rob_uop_4_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_4_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_4_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_4_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_pc_lob; // @[rob.scala:311:28]
reg rob_uop_4_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_4_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_4_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_prs3; // @[rob.scala:311:28]
reg rob_uop_4_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_4_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_4_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_4_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_4_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_4_exc_cause; // @[rob.scala:311:28]
reg rob_uop_4_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_4_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_mem_size; // @[rob.scala:311:28]
reg rob_uop_4_mem_signed; // @[rob.scala:311:28]
reg rob_uop_4_is_fence; // @[rob.scala:311:28]
reg rob_uop_4_is_fencei; // @[rob.scala:311:28]
reg rob_uop_4_is_amo; // @[rob.scala:311:28]
reg rob_uop_4_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_4_uses_stq; // @[rob.scala:311:28]
reg rob_uop_4_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_4_is_unique; // @[rob.scala:311:28]
reg rob_uop_4_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_4_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_4_lrs3; // @[rob.scala:311:28]
reg rob_uop_4_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_4_frs3_en; // @[rob.scala:311:28]
reg rob_uop_4_fp_val; // @[rob.scala:311:28]
reg rob_uop_4_fp_single; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_4_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_4_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_4_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_4_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_5_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_5_debug_inst; // @[rob.scala:311:28]
reg rob_uop_5_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_5_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_5_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_5_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_5_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_5_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_iw_state; // @[rob.scala:311:28]
reg rob_uop_5_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_5_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_5_is_br; // @[rob.scala:311:28]
reg rob_uop_5_is_jalr; // @[rob.scala:311:28]
reg rob_uop_5_is_jal; // @[rob.scala:311:28]
reg rob_uop_5_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_5_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_5_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_5_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_pc_lob; // @[rob.scala:311:28]
reg rob_uop_5_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_5_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_5_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_prs3; // @[rob.scala:311:28]
reg rob_uop_5_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_5_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_5_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_5_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_5_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_5_exc_cause; // @[rob.scala:311:28]
reg rob_uop_5_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_5_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_mem_size; // @[rob.scala:311:28]
reg rob_uop_5_mem_signed; // @[rob.scala:311:28]
reg rob_uop_5_is_fence; // @[rob.scala:311:28]
reg rob_uop_5_is_fencei; // @[rob.scala:311:28]
reg rob_uop_5_is_amo; // @[rob.scala:311:28]
reg rob_uop_5_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_5_uses_stq; // @[rob.scala:311:28]
reg rob_uop_5_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_5_is_unique; // @[rob.scala:311:28]
reg rob_uop_5_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_5_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_5_lrs3; // @[rob.scala:311:28]
reg rob_uop_5_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_5_frs3_en; // @[rob.scala:311:28]
reg rob_uop_5_fp_val; // @[rob.scala:311:28]
reg rob_uop_5_fp_single; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_5_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_5_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_5_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_5_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_6_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_6_debug_inst; // @[rob.scala:311:28]
reg rob_uop_6_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_6_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_6_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_6_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_6_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_6_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_iw_state; // @[rob.scala:311:28]
reg rob_uop_6_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_6_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_6_is_br; // @[rob.scala:311:28]
reg rob_uop_6_is_jalr; // @[rob.scala:311:28]
reg rob_uop_6_is_jal; // @[rob.scala:311:28]
reg rob_uop_6_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_6_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_6_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_6_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_pc_lob; // @[rob.scala:311:28]
reg rob_uop_6_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_6_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_6_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_prs3; // @[rob.scala:311:28]
reg rob_uop_6_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_6_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_6_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_6_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_6_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_6_exc_cause; // @[rob.scala:311:28]
reg rob_uop_6_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_6_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_mem_size; // @[rob.scala:311:28]
reg rob_uop_6_mem_signed; // @[rob.scala:311:28]
reg rob_uop_6_is_fence; // @[rob.scala:311:28]
reg rob_uop_6_is_fencei; // @[rob.scala:311:28]
reg rob_uop_6_is_amo; // @[rob.scala:311:28]
reg rob_uop_6_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_6_uses_stq; // @[rob.scala:311:28]
reg rob_uop_6_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_6_is_unique; // @[rob.scala:311:28]
reg rob_uop_6_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_6_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_6_lrs3; // @[rob.scala:311:28]
reg rob_uop_6_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_6_frs3_en; // @[rob.scala:311:28]
reg rob_uop_6_fp_val; // @[rob.scala:311:28]
reg rob_uop_6_fp_single; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_6_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_6_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_6_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_6_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_7_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_7_debug_inst; // @[rob.scala:311:28]
reg rob_uop_7_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_7_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_7_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_7_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_7_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_7_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_iw_state; // @[rob.scala:311:28]
reg rob_uop_7_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_7_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_7_is_br; // @[rob.scala:311:28]
reg rob_uop_7_is_jalr; // @[rob.scala:311:28]
reg rob_uop_7_is_jal; // @[rob.scala:311:28]
reg rob_uop_7_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_7_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_7_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_7_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_pc_lob; // @[rob.scala:311:28]
reg rob_uop_7_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_7_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_7_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_prs3; // @[rob.scala:311:28]
reg rob_uop_7_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_7_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_7_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_7_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_7_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_7_exc_cause; // @[rob.scala:311:28]
reg rob_uop_7_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_7_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_mem_size; // @[rob.scala:311:28]
reg rob_uop_7_mem_signed; // @[rob.scala:311:28]
reg rob_uop_7_is_fence; // @[rob.scala:311:28]
reg rob_uop_7_is_fencei; // @[rob.scala:311:28]
reg rob_uop_7_is_amo; // @[rob.scala:311:28]
reg rob_uop_7_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_7_uses_stq; // @[rob.scala:311:28]
reg rob_uop_7_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_7_is_unique; // @[rob.scala:311:28]
reg rob_uop_7_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_7_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_7_lrs3; // @[rob.scala:311:28]
reg rob_uop_7_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_7_frs3_en; // @[rob.scala:311:28]
reg rob_uop_7_fp_val; // @[rob.scala:311:28]
reg rob_uop_7_fp_single; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_7_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_7_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_7_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_7_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_8_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_8_debug_inst; // @[rob.scala:311:28]
reg rob_uop_8_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_8_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_8_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_8_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_8_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_8_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_iw_state; // @[rob.scala:311:28]
reg rob_uop_8_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_8_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_8_is_br; // @[rob.scala:311:28]
reg rob_uop_8_is_jalr; // @[rob.scala:311:28]
reg rob_uop_8_is_jal; // @[rob.scala:311:28]
reg rob_uop_8_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_8_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_8_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_8_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_pc_lob; // @[rob.scala:311:28]
reg rob_uop_8_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_8_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_8_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_prs3; // @[rob.scala:311:28]
reg rob_uop_8_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_8_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_8_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_8_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_8_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_8_exc_cause; // @[rob.scala:311:28]
reg rob_uop_8_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_8_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_mem_size; // @[rob.scala:311:28]
reg rob_uop_8_mem_signed; // @[rob.scala:311:28]
reg rob_uop_8_is_fence; // @[rob.scala:311:28]
reg rob_uop_8_is_fencei; // @[rob.scala:311:28]
reg rob_uop_8_is_amo; // @[rob.scala:311:28]
reg rob_uop_8_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_8_uses_stq; // @[rob.scala:311:28]
reg rob_uop_8_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_8_is_unique; // @[rob.scala:311:28]
reg rob_uop_8_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_8_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_8_lrs3; // @[rob.scala:311:28]
reg rob_uop_8_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_8_frs3_en; // @[rob.scala:311:28]
reg rob_uop_8_fp_val; // @[rob.scala:311:28]
reg rob_uop_8_fp_single; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_8_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_8_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_8_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_8_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_9_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_9_debug_inst; // @[rob.scala:311:28]
reg rob_uop_9_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_9_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_9_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_9_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_9_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_9_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_iw_state; // @[rob.scala:311:28]
reg rob_uop_9_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_9_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_9_is_br; // @[rob.scala:311:28]
reg rob_uop_9_is_jalr; // @[rob.scala:311:28]
reg rob_uop_9_is_jal; // @[rob.scala:311:28]
reg rob_uop_9_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_9_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_9_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_9_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_pc_lob; // @[rob.scala:311:28]
reg rob_uop_9_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_9_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_9_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_prs3; // @[rob.scala:311:28]
reg rob_uop_9_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_9_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_9_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_9_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_9_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_9_exc_cause; // @[rob.scala:311:28]
reg rob_uop_9_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_9_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_mem_size; // @[rob.scala:311:28]
reg rob_uop_9_mem_signed; // @[rob.scala:311:28]
reg rob_uop_9_is_fence; // @[rob.scala:311:28]
reg rob_uop_9_is_fencei; // @[rob.scala:311:28]
reg rob_uop_9_is_amo; // @[rob.scala:311:28]
reg rob_uop_9_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_9_uses_stq; // @[rob.scala:311:28]
reg rob_uop_9_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_9_is_unique; // @[rob.scala:311:28]
reg rob_uop_9_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_9_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_9_lrs3; // @[rob.scala:311:28]
reg rob_uop_9_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_9_frs3_en; // @[rob.scala:311:28]
reg rob_uop_9_fp_val; // @[rob.scala:311:28]
reg rob_uop_9_fp_single; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_9_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_9_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_9_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_9_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_10_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_10_debug_inst; // @[rob.scala:311:28]
reg rob_uop_10_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_10_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_10_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_10_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_10_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_10_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_iw_state; // @[rob.scala:311:28]
reg rob_uop_10_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_10_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_10_is_br; // @[rob.scala:311:28]
reg rob_uop_10_is_jalr; // @[rob.scala:311:28]
reg rob_uop_10_is_jal; // @[rob.scala:311:28]
reg rob_uop_10_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_10_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_10_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_10_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_pc_lob; // @[rob.scala:311:28]
reg rob_uop_10_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_10_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_10_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_prs3; // @[rob.scala:311:28]
reg rob_uop_10_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_10_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_10_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_10_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_10_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_10_exc_cause; // @[rob.scala:311:28]
reg rob_uop_10_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_10_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_mem_size; // @[rob.scala:311:28]
reg rob_uop_10_mem_signed; // @[rob.scala:311:28]
reg rob_uop_10_is_fence; // @[rob.scala:311:28]
reg rob_uop_10_is_fencei; // @[rob.scala:311:28]
reg rob_uop_10_is_amo; // @[rob.scala:311:28]
reg rob_uop_10_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_10_uses_stq; // @[rob.scala:311:28]
reg rob_uop_10_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_10_is_unique; // @[rob.scala:311:28]
reg rob_uop_10_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_10_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_10_lrs3; // @[rob.scala:311:28]
reg rob_uop_10_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_10_frs3_en; // @[rob.scala:311:28]
reg rob_uop_10_fp_val; // @[rob.scala:311:28]
reg rob_uop_10_fp_single; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_10_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_10_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_10_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_10_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_11_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_11_debug_inst; // @[rob.scala:311:28]
reg rob_uop_11_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_11_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_11_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_11_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_11_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_11_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_iw_state; // @[rob.scala:311:28]
reg rob_uop_11_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_11_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_11_is_br; // @[rob.scala:311:28]
reg rob_uop_11_is_jalr; // @[rob.scala:311:28]
reg rob_uop_11_is_jal; // @[rob.scala:311:28]
reg rob_uop_11_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_11_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_11_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_11_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_pc_lob; // @[rob.scala:311:28]
reg rob_uop_11_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_11_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_11_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_prs3; // @[rob.scala:311:28]
reg rob_uop_11_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_11_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_11_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_11_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_11_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_11_exc_cause; // @[rob.scala:311:28]
reg rob_uop_11_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_11_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_mem_size; // @[rob.scala:311:28]
reg rob_uop_11_mem_signed; // @[rob.scala:311:28]
reg rob_uop_11_is_fence; // @[rob.scala:311:28]
reg rob_uop_11_is_fencei; // @[rob.scala:311:28]
reg rob_uop_11_is_amo; // @[rob.scala:311:28]
reg rob_uop_11_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_11_uses_stq; // @[rob.scala:311:28]
reg rob_uop_11_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_11_is_unique; // @[rob.scala:311:28]
reg rob_uop_11_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_11_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_11_lrs3; // @[rob.scala:311:28]
reg rob_uop_11_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_11_frs3_en; // @[rob.scala:311:28]
reg rob_uop_11_fp_val; // @[rob.scala:311:28]
reg rob_uop_11_fp_single; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_11_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_11_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_11_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_11_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_12_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_12_debug_inst; // @[rob.scala:311:28]
reg rob_uop_12_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_12_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_12_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_12_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_12_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_12_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_iw_state; // @[rob.scala:311:28]
reg rob_uop_12_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_12_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_12_is_br; // @[rob.scala:311:28]
reg rob_uop_12_is_jalr; // @[rob.scala:311:28]
reg rob_uop_12_is_jal; // @[rob.scala:311:28]
reg rob_uop_12_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_12_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_12_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_12_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_pc_lob; // @[rob.scala:311:28]
reg rob_uop_12_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_12_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_12_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_prs3; // @[rob.scala:311:28]
reg rob_uop_12_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_12_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_12_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_12_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_12_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_12_exc_cause; // @[rob.scala:311:28]
reg rob_uop_12_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_12_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_mem_size; // @[rob.scala:311:28]
reg rob_uop_12_mem_signed; // @[rob.scala:311:28]
reg rob_uop_12_is_fence; // @[rob.scala:311:28]
reg rob_uop_12_is_fencei; // @[rob.scala:311:28]
reg rob_uop_12_is_amo; // @[rob.scala:311:28]
reg rob_uop_12_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_12_uses_stq; // @[rob.scala:311:28]
reg rob_uop_12_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_12_is_unique; // @[rob.scala:311:28]
reg rob_uop_12_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_12_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_12_lrs3; // @[rob.scala:311:28]
reg rob_uop_12_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_12_frs3_en; // @[rob.scala:311:28]
reg rob_uop_12_fp_val; // @[rob.scala:311:28]
reg rob_uop_12_fp_single; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_12_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_12_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_12_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_12_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_13_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_13_debug_inst; // @[rob.scala:311:28]
reg rob_uop_13_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_13_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_13_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_13_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_13_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_13_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_iw_state; // @[rob.scala:311:28]
reg rob_uop_13_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_13_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_13_is_br; // @[rob.scala:311:28]
reg rob_uop_13_is_jalr; // @[rob.scala:311:28]
reg rob_uop_13_is_jal; // @[rob.scala:311:28]
reg rob_uop_13_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_13_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_13_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_13_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_pc_lob; // @[rob.scala:311:28]
reg rob_uop_13_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_13_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_13_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_prs3; // @[rob.scala:311:28]
reg rob_uop_13_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_13_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_13_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_13_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_13_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_13_exc_cause; // @[rob.scala:311:28]
reg rob_uop_13_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_13_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_mem_size; // @[rob.scala:311:28]
reg rob_uop_13_mem_signed; // @[rob.scala:311:28]
reg rob_uop_13_is_fence; // @[rob.scala:311:28]
reg rob_uop_13_is_fencei; // @[rob.scala:311:28]
reg rob_uop_13_is_amo; // @[rob.scala:311:28]
reg rob_uop_13_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_13_uses_stq; // @[rob.scala:311:28]
reg rob_uop_13_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_13_is_unique; // @[rob.scala:311:28]
reg rob_uop_13_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_13_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_13_lrs3; // @[rob.scala:311:28]
reg rob_uop_13_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_13_frs3_en; // @[rob.scala:311:28]
reg rob_uop_13_fp_val; // @[rob.scala:311:28]
reg rob_uop_13_fp_single; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_13_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_13_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_13_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_13_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_14_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_14_debug_inst; // @[rob.scala:311:28]
reg rob_uop_14_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_14_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_14_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_14_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_14_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_14_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_iw_state; // @[rob.scala:311:28]
reg rob_uop_14_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_14_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_14_is_br; // @[rob.scala:311:28]
reg rob_uop_14_is_jalr; // @[rob.scala:311:28]
reg rob_uop_14_is_jal; // @[rob.scala:311:28]
reg rob_uop_14_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_14_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_14_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_14_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_pc_lob; // @[rob.scala:311:28]
reg rob_uop_14_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_14_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_14_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_prs3; // @[rob.scala:311:28]
reg rob_uop_14_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_14_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_14_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_14_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_14_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_14_exc_cause; // @[rob.scala:311:28]
reg rob_uop_14_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_14_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_mem_size; // @[rob.scala:311:28]
reg rob_uop_14_mem_signed; // @[rob.scala:311:28]
reg rob_uop_14_is_fence; // @[rob.scala:311:28]
reg rob_uop_14_is_fencei; // @[rob.scala:311:28]
reg rob_uop_14_is_amo; // @[rob.scala:311:28]
reg rob_uop_14_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_14_uses_stq; // @[rob.scala:311:28]
reg rob_uop_14_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_14_is_unique; // @[rob.scala:311:28]
reg rob_uop_14_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_14_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_14_lrs3; // @[rob.scala:311:28]
reg rob_uop_14_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_14_frs3_en; // @[rob.scala:311:28]
reg rob_uop_14_fp_val; // @[rob.scala:311:28]
reg rob_uop_14_fp_single; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_14_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_14_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_14_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_14_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_15_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_15_debug_inst; // @[rob.scala:311:28]
reg rob_uop_15_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_15_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_15_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_15_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_15_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_15_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_iw_state; // @[rob.scala:311:28]
reg rob_uop_15_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_15_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_15_is_br; // @[rob.scala:311:28]
reg rob_uop_15_is_jalr; // @[rob.scala:311:28]
reg rob_uop_15_is_jal; // @[rob.scala:311:28]
reg rob_uop_15_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_15_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_15_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_15_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_pc_lob; // @[rob.scala:311:28]
reg rob_uop_15_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_15_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_15_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_prs3; // @[rob.scala:311:28]
reg rob_uop_15_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_15_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_15_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_15_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_15_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_15_exc_cause; // @[rob.scala:311:28]
reg rob_uop_15_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_15_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_mem_size; // @[rob.scala:311:28]
reg rob_uop_15_mem_signed; // @[rob.scala:311:28]
reg rob_uop_15_is_fence; // @[rob.scala:311:28]
reg rob_uop_15_is_fencei; // @[rob.scala:311:28]
reg rob_uop_15_is_amo; // @[rob.scala:311:28]
reg rob_uop_15_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_15_uses_stq; // @[rob.scala:311:28]
reg rob_uop_15_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_15_is_unique; // @[rob.scala:311:28]
reg rob_uop_15_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_15_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_15_lrs3; // @[rob.scala:311:28]
reg rob_uop_15_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_15_frs3_en; // @[rob.scala:311:28]
reg rob_uop_15_fp_val; // @[rob.scala:311:28]
reg rob_uop_15_fp_single; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_15_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_15_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_15_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_15_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_16_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_16_debug_inst; // @[rob.scala:311:28]
reg rob_uop_16_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_16_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_16_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_16_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_16_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_16_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_iw_state; // @[rob.scala:311:28]
reg rob_uop_16_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_16_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_16_is_br; // @[rob.scala:311:28]
reg rob_uop_16_is_jalr; // @[rob.scala:311:28]
reg rob_uop_16_is_jal; // @[rob.scala:311:28]
reg rob_uop_16_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_16_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_16_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_16_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_pc_lob; // @[rob.scala:311:28]
reg rob_uop_16_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_16_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_16_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_prs3; // @[rob.scala:311:28]
reg rob_uop_16_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_16_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_16_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_16_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_16_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_16_exc_cause; // @[rob.scala:311:28]
reg rob_uop_16_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_16_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_mem_size; // @[rob.scala:311:28]
reg rob_uop_16_mem_signed; // @[rob.scala:311:28]
reg rob_uop_16_is_fence; // @[rob.scala:311:28]
reg rob_uop_16_is_fencei; // @[rob.scala:311:28]
reg rob_uop_16_is_amo; // @[rob.scala:311:28]
reg rob_uop_16_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_16_uses_stq; // @[rob.scala:311:28]
reg rob_uop_16_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_16_is_unique; // @[rob.scala:311:28]
reg rob_uop_16_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_16_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_16_lrs3; // @[rob.scala:311:28]
reg rob_uop_16_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_16_frs3_en; // @[rob.scala:311:28]
reg rob_uop_16_fp_val; // @[rob.scala:311:28]
reg rob_uop_16_fp_single; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_16_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_16_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_16_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_16_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_17_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_17_debug_inst; // @[rob.scala:311:28]
reg rob_uop_17_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_17_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_17_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_17_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_17_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_17_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_iw_state; // @[rob.scala:311:28]
reg rob_uop_17_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_17_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_17_is_br; // @[rob.scala:311:28]
reg rob_uop_17_is_jalr; // @[rob.scala:311:28]
reg rob_uop_17_is_jal; // @[rob.scala:311:28]
reg rob_uop_17_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_17_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_17_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_17_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_pc_lob; // @[rob.scala:311:28]
reg rob_uop_17_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_17_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_17_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_prs3; // @[rob.scala:311:28]
reg rob_uop_17_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_17_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_17_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_17_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_17_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_17_exc_cause; // @[rob.scala:311:28]
reg rob_uop_17_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_17_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_mem_size; // @[rob.scala:311:28]
reg rob_uop_17_mem_signed; // @[rob.scala:311:28]
reg rob_uop_17_is_fence; // @[rob.scala:311:28]
reg rob_uop_17_is_fencei; // @[rob.scala:311:28]
reg rob_uop_17_is_amo; // @[rob.scala:311:28]
reg rob_uop_17_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_17_uses_stq; // @[rob.scala:311:28]
reg rob_uop_17_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_17_is_unique; // @[rob.scala:311:28]
reg rob_uop_17_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_17_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_17_lrs3; // @[rob.scala:311:28]
reg rob_uop_17_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_17_frs3_en; // @[rob.scala:311:28]
reg rob_uop_17_fp_val; // @[rob.scala:311:28]
reg rob_uop_17_fp_single; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_17_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_17_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_17_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_17_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_18_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_18_debug_inst; // @[rob.scala:311:28]
reg rob_uop_18_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_18_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_18_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_18_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_18_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_18_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_iw_state; // @[rob.scala:311:28]
reg rob_uop_18_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_18_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_18_is_br; // @[rob.scala:311:28]
reg rob_uop_18_is_jalr; // @[rob.scala:311:28]
reg rob_uop_18_is_jal; // @[rob.scala:311:28]
reg rob_uop_18_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_18_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_18_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_18_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_pc_lob; // @[rob.scala:311:28]
reg rob_uop_18_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_18_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_18_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_prs3; // @[rob.scala:311:28]
reg rob_uop_18_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_18_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_18_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_18_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_18_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_18_exc_cause; // @[rob.scala:311:28]
reg rob_uop_18_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_18_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_mem_size; // @[rob.scala:311:28]
reg rob_uop_18_mem_signed; // @[rob.scala:311:28]
reg rob_uop_18_is_fence; // @[rob.scala:311:28]
reg rob_uop_18_is_fencei; // @[rob.scala:311:28]
reg rob_uop_18_is_amo; // @[rob.scala:311:28]
reg rob_uop_18_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_18_uses_stq; // @[rob.scala:311:28]
reg rob_uop_18_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_18_is_unique; // @[rob.scala:311:28]
reg rob_uop_18_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_18_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_18_lrs3; // @[rob.scala:311:28]
reg rob_uop_18_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_18_frs3_en; // @[rob.scala:311:28]
reg rob_uop_18_fp_val; // @[rob.scala:311:28]
reg rob_uop_18_fp_single; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_18_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_18_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_18_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_18_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_19_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_19_debug_inst; // @[rob.scala:311:28]
reg rob_uop_19_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_19_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_19_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_19_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_19_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_19_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_iw_state; // @[rob.scala:311:28]
reg rob_uop_19_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_19_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_19_is_br; // @[rob.scala:311:28]
reg rob_uop_19_is_jalr; // @[rob.scala:311:28]
reg rob_uop_19_is_jal; // @[rob.scala:311:28]
reg rob_uop_19_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_19_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_19_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_19_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_pc_lob; // @[rob.scala:311:28]
reg rob_uop_19_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_19_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_19_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_prs3; // @[rob.scala:311:28]
reg rob_uop_19_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_19_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_19_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_19_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_19_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_19_exc_cause; // @[rob.scala:311:28]
reg rob_uop_19_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_19_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_mem_size; // @[rob.scala:311:28]
reg rob_uop_19_mem_signed; // @[rob.scala:311:28]
reg rob_uop_19_is_fence; // @[rob.scala:311:28]
reg rob_uop_19_is_fencei; // @[rob.scala:311:28]
reg rob_uop_19_is_amo; // @[rob.scala:311:28]
reg rob_uop_19_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_19_uses_stq; // @[rob.scala:311:28]
reg rob_uop_19_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_19_is_unique; // @[rob.scala:311:28]
reg rob_uop_19_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_19_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_19_lrs3; // @[rob.scala:311:28]
reg rob_uop_19_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_19_frs3_en; // @[rob.scala:311:28]
reg rob_uop_19_fp_val; // @[rob.scala:311:28]
reg rob_uop_19_fp_single; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_19_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_19_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_19_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_19_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_20_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_20_debug_inst; // @[rob.scala:311:28]
reg rob_uop_20_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_20_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_20_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_20_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_20_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_20_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_iw_state; // @[rob.scala:311:28]
reg rob_uop_20_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_20_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_20_is_br; // @[rob.scala:311:28]
reg rob_uop_20_is_jalr; // @[rob.scala:311:28]
reg rob_uop_20_is_jal; // @[rob.scala:311:28]
reg rob_uop_20_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_20_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_20_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_20_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_pc_lob; // @[rob.scala:311:28]
reg rob_uop_20_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_20_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_20_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_prs3; // @[rob.scala:311:28]
reg rob_uop_20_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_20_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_20_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_20_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_20_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_20_exc_cause; // @[rob.scala:311:28]
reg rob_uop_20_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_20_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_mem_size; // @[rob.scala:311:28]
reg rob_uop_20_mem_signed; // @[rob.scala:311:28]
reg rob_uop_20_is_fence; // @[rob.scala:311:28]
reg rob_uop_20_is_fencei; // @[rob.scala:311:28]
reg rob_uop_20_is_amo; // @[rob.scala:311:28]
reg rob_uop_20_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_20_uses_stq; // @[rob.scala:311:28]
reg rob_uop_20_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_20_is_unique; // @[rob.scala:311:28]
reg rob_uop_20_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_20_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_20_lrs3; // @[rob.scala:311:28]
reg rob_uop_20_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_20_frs3_en; // @[rob.scala:311:28]
reg rob_uop_20_fp_val; // @[rob.scala:311:28]
reg rob_uop_20_fp_single; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_20_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_20_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_20_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_20_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_21_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_21_debug_inst; // @[rob.scala:311:28]
reg rob_uop_21_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_21_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_21_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_21_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_21_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_21_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_iw_state; // @[rob.scala:311:28]
reg rob_uop_21_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_21_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_21_is_br; // @[rob.scala:311:28]
reg rob_uop_21_is_jalr; // @[rob.scala:311:28]
reg rob_uop_21_is_jal; // @[rob.scala:311:28]
reg rob_uop_21_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_21_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_21_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_21_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_pc_lob; // @[rob.scala:311:28]
reg rob_uop_21_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_21_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_21_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_prs3; // @[rob.scala:311:28]
reg rob_uop_21_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_21_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_21_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_21_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_21_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_21_exc_cause; // @[rob.scala:311:28]
reg rob_uop_21_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_21_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_mem_size; // @[rob.scala:311:28]
reg rob_uop_21_mem_signed; // @[rob.scala:311:28]
reg rob_uop_21_is_fence; // @[rob.scala:311:28]
reg rob_uop_21_is_fencei; // @[rob.scala:311:28]
reg rob_uop_21_is_amo; // @[rob.scala:311:28]
reg rob_uop_21_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_21_uses_stq; // @[rob.scala:311:28]
reg rob_uop_21_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_21_is_unique; // @[rob.scala:311:28]
reg rob_uop_21_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_21_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_21_lrs3; // @[rob.scala:311:28]
reg rob_uop_21_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_21_frs3_en; // @[rob.scala:311:28]
reg rob_uop_21_fp_val; // @[rob.scala:311:28]
reg rob_uop_21_fp_single; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_21_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_21_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_21_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_21_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_22_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_22_debug_inst; // @[rob.scala:311:28]
reg rob_uop_22_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_22_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_22_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_22_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_22_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_22_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_iw_state; // @[rob.scala:311:28]
reg rob_uop_22_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_22_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_22_is_br; // @[rob.scala:311:28]
reg rob_uop_22_is_jalr; // @[rob.scala:311:28]
reg rob_uop_22_is_jal; // @[rob.scala:311:28]
reg rob_uop_22_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_22_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_22_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_22_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_pc_lob; // @[rob.scala:311:28]
reg rob_uop_22_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_22_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_22_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_prs3; // @[rob.scala:311:28]
reg rob_uop_22_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_22_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_22_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_22_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_22_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_22_exc_cause; // @[rob.scala:311:28]
reg rob_uop_22_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_22_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_mem_size; // @[rob.scala:311:28]
reg rob_uop_22_mem_signed; // @[rob.scala:311:28]
reg rob_uop_22_is_fence; // @[rob.scala:311:28]
reg rob_uop_22_is_fencei; // @[rob.scala:311:28]
reg rob_uop_22_is_amo; // @[rob.scala:311:28]
reg rob_uop_22_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_22_uses_stq; // @[rob.scala:311:28]
reg rob_uop_22_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_22_is_unique; // @[rob.scala:311:28]
reg rob_uop_22_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_22_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_22_lrs3; // @[rob.scala:311:28]
reg rob_uop_22_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_22_frs3_en; // @[rob.scala:311:28]
reg rob_uop_22_fp_val; // @[rob.scala:311:28]
reg rob_uop_22_fp_single; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_22_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_22_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_22_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_22_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_23_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_23_debug_inst; // @[rob.scala:311:28]
reg rob_uop_23_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_23_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_23_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_23_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_23_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_23_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_iw_state; // @[rob.scala:311:28]
reg rob_uop_23_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_23_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_23_is_br; // @[rob.scala:311:28]
reg rob_uop_23_is_jalr; // @[rob.scala:311:28]
reg rob_uop_23_is_jal; // @[rob.scala:311:28]
reg rob_uop_23_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_23_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_23_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_23_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_pc_lob; // @[rob.scala:311:28]
reg rob_uop_23_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_23_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_23_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_prs3; // @[rob.scala:311:28]
reg rob_uop_23_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_23_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_23_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_23_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_23_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_23_exc_cause; // @[rob.scala:311:28]
reg rob_uop_23_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_23_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_mem_size; // @[rob.scala:311:28]
reg rob_uop_23_mem_signed; // @[rob.scala:311:28]
reg rob_uop_23_is_fence; // @[rob.scala:311:28]
reg rob_uop_23_is_fencei; // @[rob.scala:311:28]
reg rob_uop_23_is_amo; // @[rob.scala:311:28]
reg rob_uop_23_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_23_uses_stq; // @[rob.scala:311:28]
reg rob_uop_23_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_23_is_unique; // @[rob.scala:311:28]
reg rob_uop_23_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_23_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_23_lrs3; // @[rob.scala:311:28]
reg rob_uop_23_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_23_frs3_en; // @[rob.scala:311:28]
reg rob_uop_23_fp_val; // @[rob.scala:311:28]
reg rob_uop_23_fp_single; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_23_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_23_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_23_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_23_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_24_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_24_debug_inst; // @[rob.scala:311:28]
reg rob_uop_24_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_24_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_24_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_24_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_24_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_24_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_iw_state; // @[rob.scala:311:28]
reg rob_uop_24_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_24_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_24_is_br; // @[rob.scala:311:28]
reg rob_uop_24_is_jalr; // @[rob.scala:311:28]
reg rob_uop_24_is_jal; // @[rob.scala:311:28]
reg rob_uop_24_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_24_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_24_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_24_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_pc_lob; // @[rob.scala:311:28]
reg rob_uop_24_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_24_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_24_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_prs3; // @[rob.scala:311:28]
reg rob_uop_24_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_24_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_24_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_24_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_24_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_24_exc_cause; // @[rob.scala:311:28]
reg rob_uop_24_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_24_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_mem_size; // @[rob.scala:311:28]
reg rob_uop_24_mem_signed; // @[rob.scala:311:28]
reg rob_uop_24_is_fence; // @[rob.scala:311:28]
reg rob_uop_24_is_fencei; // @[rob.scala:311:28]
reg rob_uop_24_is_amo; // @[rob.scala:311:28]
reg rob_uop_24_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_24_uses_stq; // @[rob.scala:311:28]
reg rob_uop_24_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_24_is_unique; // @[rob.scala:311:28]
reg rob_uop_24_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_24_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_24_lrs3; // @[rob.scala:311:28]
reg rob_uop_24_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_24_frs3_en; // @[rob.scala:311:28]
reg rob_uop_24_fp_val; // @[rob.scala:311:28]
reg rob_uop_24_fp_single; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_24_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_24_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_24_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_24_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_25_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_25_debug_inst; // @[rob.scala:311:28]
reg rob_uop_25_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_25_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_25_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_25_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_25_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_25_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_iw_state; // @[rob.scala:311:28]
reg rob_uop_25_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_25_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_25_is_br; // @[rob.scala:311:28]
reg rob_uop_25_is_jalr; // @[rob.scala:311:28]
reg rob_uop_25_is_jal; // @[rob.scala:311:28]
reg rob_uop_25_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_25_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_25_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_25_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_pc_lob; // @[rob.scala:311:28]
reg rob_uop_25_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_25_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_25_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_prs3; // @[rob.scala:311:28]
reg rob_uop_25_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_25_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_25_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_25_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_25_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_25_exc_cause; // @[rob.scala:311:28]
reg rob_uop_25_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_25_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_mem_size; // @[rob.scala:311:28]
reg rob_uop_25_mem_signed; // @[rob.scala:311:28]
reg rob_uop_25_is_fence; // @[rob.scala:311:28]
reg rob_uop_25_is_fencei; // @[rob.scala:311:28]
reg rob_uop_25_is_amo; // @[rob.scala:311:28]
reg rob_uop_25_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_25_uses_stq; // @[rob.scala:311:28]
reg rob_uop_25_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_25_is_unique; // @[rob.scala:311:28]
reg rob_uop_25_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_25_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_25_lrs3; // @[rob.scala:311:28]
reg rob_uop_25_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_25_frs3_en; // @[rob.scala:311:28]
reg rob_uop_25_fp_val; // @[rob.scala:311:28]
reg rob_uop_25_fp_single; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_25_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_25_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_25_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_25_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_26_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_26_debug_inst; // @[rob.scala:311:28]
reg rob_uop_26_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_26_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_26_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_26_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_26_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_26_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_iw_state; // @[rob.scala:311:28]
reg rob_uop_26_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_26_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_26_is_br; // @[rob.scala:311:28]
reg rob_uop_26_is_jalr; // @[rob.scala:311:28]
reg rob_uop_26_is_jal; // @[rob.scala:311:28]
reg rob_uop_26_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_26_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_26_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_26_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_pc_lob; // @[rob.scala:311:28]
reg rob_uop_26_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_26_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_26_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_prs3; // @[rob.scala:311:28]
reg rob_uop_26_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_26_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_26_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_26_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_26_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_26_exc_cause; // @[rob.scala:311:28]
reg rob_uop_26_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_26_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_mem_size; // @[rob.scala:311:28]
reg rob_uop_26_mem_signed; // @[rob.scala:311:28]
reg rob_uop_26_is_fence; // @[rob.scala:311:28]
reg rob_uop_26_is_fencei; // @[rob.scala:311:28]
reg rob_uop_26_is_amo; // @[rob.scala:311:28]
reg rob_uop_26_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_26_uses_stq; // @[rob.scala:311:28]
reg rob_uop_26_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_26_is_unique; // @[rob.scala:311:28]
reg rob_uop_26_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_26_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_26_lrs3; // @[rob.scala:311:28]
reg rob_uop_26_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_26_frs3_en; // @[rob.scala:311:28]
reg rob_uop_26_fp_val; // @[rob.scala:311:28]
reg rob_uop_26_fp_single; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_26_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_26_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_26_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_26_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_27_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_27_debug_inst; // @[rob.scala:311:28]
reg rob_uop_27_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_27_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_27_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_27_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_27_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_27_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_iw_state; // @[rob.scala:311:28]
reg rob_uop_27_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_27_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_27_is_br; // @[rob.scala:311:28]
reg rob_uop_27_is_jalr; // @[rob.scala:311:28]
reg rob_uop_27_is_jal; // @[rob.scala:311:28]
reg rob_uop_27_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_27_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_27_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_27_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_pc_lob; // @[rob.scala:311:28]
reg rob_uop_27_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_27_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_27_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_prs3; // @[rob.scala:311:28]
reg rob_uop_27_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_27_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_27_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_27_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_27_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_27_exc_cause; // @[rob.scala:311:28]
reg rob_uop_27_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_27_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_mem_size; // @[rob.scala:311:28]
reg rob_uop_27_mem_signed; // @[rob.scala:311:28]
reg rob_uop_27_is_fence; // @[rob.scala:311:28]
reg rob_uop_27_is_fencei; // @[rob.scala:311:28]
reg rob_uop_27_is_amo; // @[rob.scala:311:28]
reg rob_uop_27_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_27_uses_stq; // @[rob.scala:311:28]
reg rob_uop_27_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_27_is_unique; // @[rob.scala:311:28]
reg rob_uop_27_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_27_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_27_lrs3; // @[rob.scala:311:28]
reg rob_uop_27_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_27_frs3_en; // @[rob.scala:311:28]
reg rob_uop_27_fp_val; // @[rob.scala:311:28]
reg rob_uop_27_fp_single; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_27_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_27_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_27_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_27_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_28_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_28_debug_inst; // @[rob.scala:311:28]
reg rob_uop_28_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_28_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_28_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_28_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_28_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_28_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_iw_state; // @[rob.scala:311:28]
reg rob_uop_28_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_28_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_28_is_br; // @[rob.scala:311:28]
reg rob_uop_28_is_jalr; // @[rob.scala:311:28]
reg rob_uop_28_is_jal; // @[rob.scala:311:28]
reg rob_uop_28_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_28_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_28_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_28_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_pc_lob; // @[rob.scala:311:28]
reg rob_uop_28_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_28_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_28_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_prs3; // @[rob.scala:311:28]
reg rob_uop_28_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_28_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_28_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_28_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_28_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_28_exc_cause; // @[rob.scala:311:28]
reg rob_uop_28_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_28_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_mem_size; // @[rob.scala:311:28]
reg rob_uop_28_mem_signed; // @[rob.scala:311:28]
reg rob_uop_28_is_fence; // @[rob.scala:311:28]
reg rob_uop_28_is_fencei; // @[rob.scala:311:28]
reg rob_uop_28_is_amo; // @[rob.scala:311:28]
reg rob_uop_28_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_28_uses_stq; // @[rob.scala:311:28]
reg rob_uop_28_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_28_is_unique; // @[rob.scala:311:28]
reg rob_uop_28_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_28_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_28_lrs3; // @[rob.scala:311:28]
reg rob_uop_28_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_28_frs3_en; // @[rob.scala:311:28]
reg rob_uop_28_fp_val; // @[rob.scala:311:28]
reg rob_uop_28_fp_single; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_28_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_28_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_28_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_28_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_29_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_29_debug_inst; // @[rob.scala:311:28]
reg rob_uop_29_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_29_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_29_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_29_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_29_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_29_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_iw_state; // @[rob.scala:311:28]
reg rob_uop_29_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_29_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_29_is_br; // @[rob.scala:311:28]
reg rob_uop_29_is_jalr; // @[rob.scala:311:28]
reg rob_uop_29_is_jal; // @[rob.scala:311:28]
reg rob_uop_29_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_29_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_29_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_29_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_pc_lob; // @[rob.scala:311:28]
reg rob_uop_29_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_29_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_29_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_prs3; // @[rob.scala:311:28]
reg rob_uop_29_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_29_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_29_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_29_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_29_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_29_exc_cause; // @[rob.scala:311:28]
reg rob_uop_29_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_29_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_mem_size; // @[rob.scala:311:28]
reg rob_uop_29_mem_signed; // @[rob.scala:311:28]
reg rob_uop_29_is_fence; // @[rob.scala:311:28]
reg rob_uop_29_is_fencei; // @[rob.scala:311:28]
reg rob_uop_29_is_amo; // @[rob.scala:311:28]
reg rob_uop_29_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_29_uses_stq; // @[rob.scala:311:28]
reg rob_uop_29_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_29_is_unique; // @[rob.scala:311:28]
reg rob_uop_29_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_29_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_29_lrs3; // @[rob.scala:311:28]
reg rob_uop_29_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_29_frs3_en; // @[rob.scala:311:28]
reg rob_uop_29_fp_val; // @[rob.scala:311:28]
reg rob_uop_29_fp_single; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_29_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_29_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_29_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_29_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_30_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_30_debug_inst; // @[rob.scala:311:28]
reg rob_uop_30_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_30_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_30_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_30_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_30_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_30_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_iw_state; // @[rob.scala:311:28]
reg rob_uop_30_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_30_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_30_is_br; // @[rob.scala:311:28]
reg rob_uop_30_is_jalr; // @[rob.scala:311:28]
reg rob_uop_30_is_jal; // @[rob.scala:311:28]
reg rob_uop_30_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_30_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_30_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_30_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_pc_lob; // @[rob.scala:311:28]
reg rob_uop_30_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_30_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_30_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_prs3; // @[rob.scala:311:28]
reg rob_uop_30_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_30_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_30_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_30_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_30_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_30_exc_cause; // @[rob.scala:311:28]
reg rob_uop_30_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_30_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_mem_size; // @[rob.scala:311:28]
reg rob_uop_30_mem_signed; // @[rob.scala:311:28]
reg rob_uop_30_is_fence; // @[rob.scala:311:28]
reg rob_uop_30_is_fencei; // @[rob.scala:311:28]
reg rob_uop_30_is_amo; // @[rob.scala:311:28]
reg rob_uop_30_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_30_uses_stq; // @[rob.scala:311:28]
reg rob_uop_30_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_30_is_unique; // @[rob.scala:311:28]
reg rob_uop_30_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_30_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_30_lrs3; // @[rob.scala:311:28]
reg rob_uop_30_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_30_frs3_en; // @[rob.scala:311:28]
reg rob_uop_30_fp_val; // @[rob.scala:311:28]
reg rob_uop_30_fp_single; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_30_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_30_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_30_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_30_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_31_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_31_debug_inst; // @[rob.scala:311:28]
reg rob_uop_31_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_31_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_31_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_31_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_31_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_31_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_iw_state; // @[rob.scala:311:28]
reg rob_uop_31_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_31_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_31_is_br; // @[rob.scala:311:28]
reg rob_uop_31_is_jalr; // @[rob.scala:311:28]
reg rob_uop_31_is_jal; // @[rob.scala:311:28]
reg rob_uop_31_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_31_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_31_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_31_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_pc_lob; // @[rob.scala:311:28]
reg rob_uop_31_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_31_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_31_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_prs3; // @[rob.scala:311:28]
reg rob_uop_31_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_31_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_31_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_31_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_31_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_31_exc_cause; // @[rob.scala:311:28]
reg rob_uop_31_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_31_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_mem_size; // @[rob.scala:311:28]
reg rob_uop_31_mem_signed; // @[rob.scala:311:28]
reg rob_uop_31_is_fence; // @[rob.scala:311:28]
reg rob_uop_31_is_fencei; // @[rob.scala:311:28]
reg rob_uop_31_is_amo; // @[rob.scala:311:28]
reg rob_uop_31_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_31_uses_stq; // @[rob.scala:311:28]
reg rob_uop_31_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_31_is_unique; // @[rob.scala:311:28]
reg rob_uop_31_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_31_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_31_lrs3; // @[rob.scala:311:28]
reg rob_uop_31_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_31_frs3_en; // @[rob.scala:311:28]
reg rob_uop_31_fp_val; // @[rob.scala:311:28]
reg rob_uop_31_fp_single; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_31_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_31_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_31_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_31_debug_tsrc; // @[rob.scala:311:28]
reg rob_exception_0; // @[rob.scala:312:28]
reg rob_exception_1; // @[rob.scala:312:28]
reg rob_exception_2; // @[rob.scala:312:28]
reg rob_exception_3; // @[rob.scala:312:28]
reg rob_exception_4; // @[rob.scala:312:28]
reg rob_exception_5; // @[rob.scala:312:28]
reg rob_exception_6; // @[rob.scala:312:28]
reg rob_exception_7; // @[rob.scala:312:28]
reg rob_exception_8; // @[rob.scala:312:28]
reg rob_exception_9; // @[rob.scala:312:28]
reg rob_exception_10; // @[rob.scala:312:28]
reg rob_exception_11; // @[rob.scala:312:28]
reg rob_exception_12; // @[rob.scala:312:28]
reg rob_exception_13; // @[rob.scala:312:28]
reg rob_exception_14; // @[rob.scala:312:28]
reg rob_exception_15; // @[rob.scala:312:28]
reg rob_exception_16; // @[rob.scala:312:28]
reg rob_exception_17; // @[rob.scala:312:28]
reg rob_exception_18; // @[rob.scala:312:28]
reg rob_exception_19; // @[rob.scala:312:28]
reg rob_exception_20; // @[rob.scala:312:28]
reg rob_exception_21; // @[rob.scala:312:28]
reg rob_exception_22; // @[rob.scala:312:28]
reg rob_exception_23; // @[rob.scala:312:28]
reg rob_exception_24; // @[rob.scala:312:28]
reg rob_exception_25; // @[rob.scala:312:28]
reg rob_exception_26; // @[rob.scala:312:28]
reg rob_exception_27; // @[rob.scala:312:28]
reg rob_exception_28; // @[rob.scala:312:28]
reg rob_exception_29; // @[rob.scala:312:28]
reg rob_exception_30; // @[rob.scala:312:28]
reg rob_exception_31; // @[rob.scala:312:28]
reg rob_predicated_0; // @[rob.scala:313:29]
reg rob_predicated_1; // @[rob.scala:313:29]
reg rob_predicated_2; // @[rob.scala:313:29]
reg rob_predicated_3; // @[rob.scala:313:29]
reg rob_predicated_4; // @[rob.scala:313:29]
reg rob_predicated_5; // @[rob.scala:313:29]
reg rob_predicated_6; // @[rob.scala:313:29]
reg rob_predicated_7; // @[rob.scala:313:29]
reg rob_predicated_8; // @[rob.scala:313:29]
reg rob_predicated_9; // @[rob.scala:313:29]
reg rob_predicated_10; // @[rob.scala:313:29]
reg rob_predicated_11; // @[rob.scala:313:29]
reg rob_predicated_12; // @[rob.scala:313:29]
reg rob_predicated_13; // @[rob.scala:313:29]
reg rob_predicated_14; // @[rob.scala:313:29]
reg rob_predicated_15; // @[rob.scala:313:29]
reg rob_predicated_16; // @[rob.scala:313:29]
reg rob_predicated_17; // @[rob.scala:313:29]
reg rob_predicated_18; // @[rob.scala:313:29]
reg rob_predicated_19; // @[rob.scala:313:29]
reg rob_predicated_20; // @[rob.scala:313:29]
reg rob_predicated_21; // @[rob.scala:313:29]
reg rob_predicated_22; // @[rob.scala:313:29]
reg rob_predicated_23; // @[rob.scala:313:29]
reg rob_predicated_24; // @[rob.scala:313:29]
reg rob_predicated_25; // @[rob.scala:313:29]
reg rob_predicated_26; // @[rob.scala:313:29]
reg rob_predicated_27; // @[rob.scala:313:29]
reg rob_predicated_28; // @[rob.scala:313:29]
reg rob_predicated_29; // @[rob.scala:313:29]
reg rob_predicated_30; // @[rob.scala:313:29]
reg rob_predicated_31; // @[rob.scala:313:29]
wire [31:0] _GEN_0 = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}}; // @[rob.scala:308:32, :324:31]
assign rob_tail_vals_0 = _GEN_0[rob_tail]; // @[rob.scala:227:29, :248:33, :324:31]
wire _rob_bsy_T = io_enq_uops_0_is_fence_0 | io_enq_uops_0_is_fencei_0; // @[rob.scala:211:7, :325:60]
wire _rob_bsy_T_1 = ~_rob_bsy_T; // @[rob.scala:325:{34,60}]
wire _rob_unsafe_T = ~io_enq_uops_0_is_fence_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_1 = io_enq_uops_0_uses_stq_0 & _rob_unsafe_T; // @[rob.scala:211:7]
wire _rob_unsafe_T_2 = io_enq_uops_0_uses_ldq_0 | _rob_unsafe_T_1; // @[rob.scala:211:7]
wire _rob_unsafe_T_3 = _rob_unsafe_T_2 | io_enq_uops_0_is_br_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_4 = _rob_unsafe_T_3 | io_enq_uops_0_is_jalr_0; // @[rob.scala:211:7]
wire [6:0] _GEN_1 = {2'h0, io_wb_resps_0_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx; // @[rob.scala:267:25]
assign row_idx = _GEN_1; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T; // @[rob.scala:267:25]
assign _temp_uop_T = _GEN_1; // @[rob.scala:267:25]
wire [6:0] row_idx_6; // @[rob.scala:267:25]
assign row_idx_6 = _GEN_1; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_12; // @[rob.scala:267:25]
assign _temp_uop_T_12 = _GEN_1; // @[rob.scala:267:25]
wire [6:0] row_idx_12; // @[rob.scala:267:25]
assign row_idx_12 = _GEN_1; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_24; // @[rob.scala:267:25]
assign _temp_uop_T_24 = _GEN_1; // @[rob.scala:267:25]
wire [6:0] _GEN_2 = {2'h0, io_wb_resps_1_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx_1; // @[rob.scala:267:25]
assign row_idx_1 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_2; // @[rob.scala:267:25]
assign _temp_uop_T_2 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] row_idx_7; // @[rob.scala:267:25]
assign row_idx_7 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_14; // @[rob.scala:267:25]
assign _temp_uop_T_14 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] row_idx_13; // @[rob.scala:267:25]
assign row_idx_13 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_26; // @[rob.scala:267:25]
assign _temp_uop_T_26 = _GEN_2; // @[rob.scala:267:25]
wire [6:0] _GEN_3 = {2'h0, io_wb_resps_2_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx_2; // @[rob.scala:267:25]
assign row_idx_2 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_4; // @[rob.scala:267:25]
assign _temp_uop_T_4 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] row_idx_8; // @[rob.scala:267:25]
assign row_idx_8 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_16; // @[rob.scala:267:25]
assign _temp_uop_T_16 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] row_idx_14; // @[rob.scala:267:25]
assign row_idx_14 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_28; // @[rob.scala:267:25]
assign _temp_uop_T_28 = _GEN_3; // @[rob.scala:267:25]
wire [6:0] _GEN_4 = {2'h0, io_wb_resps_3_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx_3; // @[rob.scala:267:25]
assign row_idx_3 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_6; // @[rob.scala:267:25]
assign _temp_uop_T_6 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] row_idx_9; // @[rob.scala:267:25]
assign row_idx_9 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_18; // @[rob.scala:267:25]
assign _temp_uop_T_18 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] row_idx_15; // @[rob.scala:267:25]
assign row_idx_15 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_30; // @[rob.scala:267:25]
assign _temp_uop_T_30 = _GEN_4; // @[rob.scala:267:25]
wire [6:0] _GEN_5 = {2'h0, io_wb_resps_4_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx_4; // @[rob.scala:267:25]
assign row_idx_4 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_8; // @[rob.scala:267:25]
assign _temp_uop_T_8 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] row_idx_10; // @[rob.scala:267:25]
assign row_idx_10 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_20; // @[rob.scala:267:25]
assign _temp_uop_T_20 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] row_idx_16; // @[rob.scala:267:25]
assign row_idx_16 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_32; // @[rob.scala:267:25]
assign _temp_uop_T_32 = _GEN_5; // @[rob.scala:267:25]
wire [6:0] _GEN_6 = {2'h0, io_wb_resps_5_bits_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] row_idx_5; // @[rob.scala:267:25]
assign row_idx_5 = _GEN_6; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_10; // @[rob.scala:267:25]
assign _temp_uop_T_10 = _GEN_6; // @[rob.scala:267:25]
wire [6:0] row_idx_11; // @[rob.scala:267:25]
assign row_idx_11 = _GEN_6; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_22; // @[rob.scala:267:25]
assign _temp_uop_T_22 = _GEN_6; // @[rob.scala:267:25]
wire [6:0] row_idx_17; // @[rob.scala:267:25]
assign row_idx_17 = _GEN_6; // @[rob.scala:267:25]
wire [6:0] _temp_uop_T_34; // @[rob.scala:267:25]
assign _temp_uop_T_34 = _GEN_6; // @[rob.scala:267:25]
wire _T_51 = io_lsu_clr_bsy_0_valid_0 & io_lsu_clr_bsy_0_bits_0[1:0] == 2'h0; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire [6:0] _GEN_7 = {2'h0, io_lsu_clr_bsy_0_bits_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] cidx; // @[rob.scala:267:25]
assign cidx = _GEN_7; // @[rob.scala:267:25]
wire [6:0] cidx_3; // @[rob.scala:267:25]
assign cidx_3 = _GEN_7; // @[rob.scala:267:25]
wire [6:0] cidx_6; // @[rob.scala:267:25]
assign cidx_6 = _GEN_7; // @[rob.scala:267:25]
wire [31:0] _GEN_8 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[rob.scala:309:28, :366:31]
wire _T_66 = io_lsu_clr_bsy_1_valid_0 & io_lsu_clr_bsy_1_bits_0[1:0] == 2'h0; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire [6:0] _GEN_9 = {2'h0, io_lsu_clr_bsy_1_bits_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] cidx_1; // @[rob.scala:267:25]
assign cidx_1 = _GEN_9; // @[rob.scala:267:25]
wire [6:0] cidx_4; // @[rob.scala:267:25]
assign cidx_4 = _GEN_9; // @[rob.scala:267:25]
wire [6:0] cidx_7; // @[rob.scala:267:25]
assign cidx_7 = _GEN_9; // @[rob.scala:267:25]
wire [6:0] _GEN_10 = {2'h0, io_lsu_clr_unsafe_0_bits_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire [6:0] cidx_2; // @[rob.scala:267:25]
assign cidx_2 = _GEN_10; // @[rob.scala:267:25]
wire [6:0] cidx_5; // @[rob.scala:267:25]
assign cidx_5 = _GEN_10; // @[rob.scala:267:25]
wire [6:0] cidx_8; // @[rob.scala:267:25]
assign cidx_8 = _GEN_10; // @[rob.scala:267:25]
wire _T_95 = io_lxcpt_valid_0 & io_lxcpt_bits_uop_rob_idx_0[1:0] == 2'h0; // @[rob.scala:211:7, :271:36, :305:53, :390:26]
wire _GEN_11 = _T_95 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:211:7, :390:26, :392:{33,66}, :394:15]
wire [31:0] _GEN_12 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}}; // @[rob.scala:310:28, :394:15]
wire _GEN_13 = _GEN_12[io_lxcpt_bits_uop_rob_idx_0[6:2]]; // @[rob.scala:211:7, :267:25, :394:15]
assign rob_head_vals_0 = _GEN_0[rob_head]; // @[rob.scala:223:29, :247:33, :324:31, :402:49]
wire [31:0] _GEN_14 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}}; // @[rob.scala:312:28, :402:49]
assign _can_throw_exception_0_T = rob_head_vals_0 & _GEN_14[rob_head]; // @[rob.scala:223:29, :247:33, :402:49]
assign can_throw_exception_0 = _can_throw_exception_0_T; // @[rob.scala:244:33, :402:49]
wire _can_commit_0_T = ~_GEN_8[rob_head]; // @[rob.scala:223:29, :366:31, :408:43]
wire _can_commit_0_T_1 = rob_head_vals_0 & _can_commit_0_T; // @[rob.scala:247:33, :408:{40,43}]
wire _can_commit_0_T_2 = ~io_csr_stall_0; // @[rob.scala:211:7, :408:67]
assign _can_commit_0_T_3 = _can_commit_0_T_1 & _can_commit_0_T_2; // @[rob.scala:408:{40,64,67}]
assign can_commit_0 = _can_commit_0_T_3; // @[rob.scala:243:33, :408:64]
wire [31:0] _GEN_15 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}}; // @[rob.scala:313:29, :414:51]
wire _io_commit_arch_valids_0_T = ~_GEN_15[com_idx]; // @[rob.scala:235:20, :414:51]
assign _io_commit_arch_valids_0_T_1 = will_commit_0 & _io_commit_arch_valids_0_T; // @[rob.scala:242:33, :414:{48,51}]
assign io_commit_arch_valids_0_0 = _io_commit_arch_valids_0_T_1; // @[rob.scala:211:7, :414:48]
wire [31:0][6:0] _GEN_16 = {{rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uopc_0 = _GEN_16[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_17 = {{rob_uop_31_inst}, {rob_uop_30_inst}, {rob_uop_29_inst}, {rob_uop_28_inst}, {rob_uop_27_inst}, {rob_uop_26_inst}, {rob_uop_25_inst}, {rob_uop_24_inst}, {rob_uop_23_inst}, {rob_uop_22_inst}, {rob_uop_21_inst}, {rob_uop_20_inst}, {rob_uop_19_inst}, {rob_uop_18_inst}, {rob_uop_17_inst}, {rob_uop_16_inst}, {rob_uop_15_inst}, {rob_uop_14_inst}, {rob_uop_13_inst}, {rob_uop_12_inst}, {rob_uop_11_inst}, {rob_uop_10_inst}, {rob_uop_9_inst}, {rob_uop_8_inst}, {rob_uop_7_inst}, {rob_uop_6_inst}, {rob_uop_5_inst}, {rob_uop_4_inst}, {rob_uop_3_inst}, {rob_uop_2_inst}, {rob_uop_1_inst}, {rob_uop_0_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_inst_0 = _GEN_17[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_18 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_inst_0 = _GEN_18[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_19 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_rvc_0 = _GEN_19[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][39:0] _GEN_20 = {{rob_uop_31_debug_pc}, {rob_uop_30_debug_pc}, {rob_uop_29_debug_pc}, {rob_uop_28_debug_pc}, {rob_uop_27_debug_pc}, {rob_uop_26_debug_pc}, {rob_uop_25_debug_pc}, {rob_uop_24_debug_pc}, {rob_uop_23_debug_pc}, {rob_uop_22_debug_pc}, {rob_uop_21_debug_pc}, {rob_uop_20_debug_pc}, {rob_uop_19_debug_pc}, {rob_uop_18_debug_pc}, {rob_uop_17_debug_pc}, {rob_uop_16_debug_pc}, {rob_uop_15_debug_pc}, {rob_uop_14_debug_pc}, {rob_uop_13_debug_pc}, {rob_uop_12_debug_pc}, {rob_uop_11_debug_pc}, {rob_uop_10_debug_pc}, {rob_uop_9_debug_pc}, {rob_uop_8_debug_pc}, {rob_uop_7_debug_pc}, {rob_uop_6_debug_pc}, {rob_uop_5_debug_pc}, {rob_uop_4_debug_pc}, {rob_uop_3_debug_pc}, {rob_uop_2_debug_pc}, {rob_uop_1_debug_pc}, {rob_uop_0_debug_pc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_pc_0 = _GEN_20[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_21 = {{rob_uop_31_iq_type}, {rob_uop_30_iq_type}, {rob_uop_29_iq_type}, {rob_uop_28_iq_type}, {rob_uop_27_iq_type}, {rob_uop_26_iq_type}, {rob_uop_25_iq_type}, {rob_uop_24_iq_type}, {rob_uop_23_iq_type}, {rob_uop_22_iq_type}, {rob_uop_21_iq_type}, {rob_uop_20_iq_type}, {rob_uop_19_iq_type}, {rob_uop_18_iq_type}, {rob_uop_17_iq_type}, {rob_uop_16_iq_type}, {rob_uop_15_iq_type}, {rob_uop_14_iq_type}, {rob_uop_13_iq_type}, {rob_uop_12_iq_type}, {rob_uop_11_iq_type}, {rob_uop_10_iq_type}, {rob_uop_9_iq_type}, {rob_uop_8_iq_type}, {rob_uop_7_iq_type}, {rob_uop_6_iq_type}, {rob_uop_5_iq_type}, {rob_uop_4_iq_type}, {rob_uop_3_iq_type}, {rob_uop_2_iq_type}, {rob_uop_1_iq_type}, {rob_uop_0_iq_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iq_type_0 = _GEN_21[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][9:0] _GEN_22 = {{rob_uop_31_fu_code}, {rob_uop_30_fu_code}, {rob_uop_29_fu_code}, {rob_uop_28_fu_code}, {rob_uop_27_fu_code}, {rob_uop_26_fu_code}, {rob_uop_25_fu_code}, {rob_uop_24_fu_code}, {rob_uop_23_fu_code}, {rob_uop_22_fu_code}, {rob_uop_21_fu_code}, {rob_uop_20_fu_code}, {rob_uop_19_fu_code}, {rob_uop_18_fu_code}, {rob_uop_17_fu_code}, {rob_uop_16_fu_code}, {rob_uop_15_fu_code}, {rob_uop_14_fu_code}, {rob_uop_13_fu_code}, {rob_uop_12_fu_code}, {rob_uop_11_fu_code}, {rob_uop_10_fu_code}, {rob_uop_9_fu_code}, {rob_uop_8_fu_code}, {rob_uop_7_fu_code}, {rob_uop_6_fu_code}, {rob_uop_5_fu_code}, {rob_uop_4_fu_code}, {rob_uop_3_fu_code}, {rob_uop_2_fu_code}, {rob_uop_1_fu_code}, {rob_uop_0_fu_code}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fu_code_0 = _GEN_22[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_23 = {{rob_uop_31_ctrl_br_type}, {rob_uop_30_ctrl_br_type}, {rob_uop_29_ctrl_br_type}, {rob_uop_28_ctrl_br_type}, {rob_uop_27_ctrl_br_type}, {rob_uop_26_ctrl_br_type}, {rob_uop_25_ctrl_br_type}, {rob_uop_24_ctrl_br_type}, {rob_uop_23_ctrl_br_type}, {rob_uop_22_ctrl_br_type}, {rob_uop_21_ctrl_br_type}, {rob_uop_20_ctrl_br_type}, {rob_uop_19_ctrl_br_type}, {rob_uop_18_ctrl_br_type}, {rob_uop_17_ctrl_br_type}, {rob_uop_16_ctrl_br_type}, {rob_uop_15_ctrl_br_type}, {rob_uop_14_ctrl_br_type}, {rob_uop_13_ctrl_br_type}, {rob_uop_12_ctrl_br_type}, {rob_uop_11_ctrl_br_type}, {rob_uop_10_ctrl_br_type}, {rob_uop_9_ctrl_br_type}, {rob_uop_8_ctrl_br_type}, {rob_uop_7_ctrl_br_type}, {rob_uop_6_ctrl_br_type}, {rob_uop_5_ctrl_br_type}, {rob_uop_4_ctrl_br_type}, {rob_uop_3_ctrl_br_type}, {rob_uop_2_ctrl_br_type}, {rob_uop_1_ctrl_br_type}, {rob_uop_0_ctrl_br_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_br_type_0 = _GEN_23[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_24 = {{rob_uop_31_ctrl_op1_sel}, {rob_uop_30_ctrl_op1_sel}, {rob_uop_29_ctrl_op1_sel}, {rob_uop_28_ctrl_op1_sel}, {rob_uop_27_ctrl_op1_sel}, {rob_uop_26_ctrl_op1_sel}, {rob_uop_25_ctrl_op1_sel}, {rob_uop_24_ctrl_op1_sel}, {rob_uop_23_ctrl_op1_sel}, {rob_uop_22_ctrl_op1_sel}, {rob_uop_21_ctrl_op1_sel}, {rob_uop_20_ctrl_op1_sel}, {rob_uop_19_ctrl_op1_sel}, {rob_uop_18_ctrl_op1_sel}, {rob_uop_17_ctrl_op1_sel}, {rob_uop_16_ctrl_op1_sel}, {rob_uop_15_ctrl_op1_sel}, {rob_uop_14_ctrl_op1_sel}, {rob_uop_13_ctrl_op1_sel}, {rob_uop_12_ctrl_op1_sel}, {rob_uop_11_ctrl_op1_sel}, {rob_uop_10_ctrl_op1_sel}, {rob_uop_9_ctrl_op1_sel}, {rob_uop_8_ctrl_op1_sel}, {rob_uop_7_ctrl_op1_sel}, {rob_uop_6_ctrl_op1_sel}, {rob_uop_5_ctrl_op1_sel}, {rob_uop_4_ctrl_op1_sel}, {rob_uop_3_ctrl_op1_sel}, {rob_uop_2_ctrl_op1_sel}, {rob_uop_1_ctrl_op1_sel}, {rob_uop_0_ctrl_op1_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op1_sel_0 = _GEN_24[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_25 = {{rob_uop_31_ctrl_op2_sel}, {rob_uop_30_ctrl_op2_sel}, {rob_uop_29_ctrl_op2_sel}, {rob_uop_28_ctrl_op2_sel}, {rob_uop_27_ctrl_op2_sel}, {rob_uop_26_ctrl_op2_sel}, {rob_uop_25_ctrl_op2_sel}, {rob_uop_24_ctrl_op2_sel}, {rob_uop_23_ctrl_op2_sel}, {rob_uop_22_ctrl_op2_sel}, {rob_uop_21_ctrl_op2_sel}, {rob_uop_20_ctrl_op2_sel}, {rob_uop_19_ctrl_op2_sel}, {rob_uop_18_ctrl_op2_sel}, {rob_uop_17_ctrl_op2_sel}, {rob_uop_16_ctrl_op2_sel}, {rob_uop_15_ctrl_op2_sel}, {rob_uop_14_ctrl_op2_sel}, {rob_uop_13_ctrl_op2_sel}, {rob_uop_12_ctrl_op2_sel}, {rob_uop_11_ctrl_op2_sel}, {rob_uop_10_ctrl_op2_sel}, {rob_uop_9_ctrl_op2_sel}, {rob_uop_8_ctrl_op2_sel}, {rob_uop_7_ctrl_op2_sel}, {rob_uop_6_ctrl_op2_sel}, {rob_uop_5_ctrl_op2_sel}, {rob_uop_4_ctrl_op2_sel}, {rob_uop_3_ctrl_op2_sel}, {rob_uop_2_ctrl_op2_sel}, {rob_uop_1_ctrl_op2_sel}, {rob_uop_0_ctrl_op2_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op2_sel_0 = _GEN_25[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_26 = {{rob_uop_31_ctrl_imm_sel}, {rob_uop_30_ctrl_imm_sel}, {rob_uop_29_ctrl_imm_sel}, {rob_uop_28_ctrl_imm_sel}, {rob_uop_27_ctrl_imm_sel}, {rob_uop_26_ctrl_imm_sel}, {rob_uop_25_ctrl_imm_sel}, {rob_uop_24_ctrl_imm_sel}, {rob_uop_23_ctrl_imm_sel}, {rob_uop_22_ctrl_imm_sel}, {rob_uop_21_ctrl_imm_sel}, {rob_uop_20_ctrl_imm_sel}, {rob_uop_19_ctrl_imm_sel}, {rob_uop_18_ctrl_imm_sel}, {rob_uop_17_ctrl_imm_sel}, {rob_uop_16_ctrl_imm_sel}, {rob_uop_15_ctrl_imm_sel}, {rob_uop_14_ctrl_imm_sel}, {rob_uop_13_ctrl_imm_sel}, {rob_uop_12_ctrl_imm_sel}, {rob_uop_11_ctrl_imm_sel}, {rob_uop_10_ctrl_imm_sel}, {rob_uop_9_ctrl_imm_sel}, {rob_uop_8_ctrl_imm_sel}, {rob_uop_7_ctrl_imm_sel}, {rob_uop_6_ctrl_imm_sel}, {rob_uop_5_ctrl_imm_sel}, {rob_uop_4_ctrl_imm_sel}, {rob_uop_3_ctrl_imm_sel}, {rob_uop_2_ctrl_imm_sel}, {rob_uop_1_ctrl_imm_sel}, {rob_uop_0_ctrl_imm_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_imm_sel_0 = _GEN_26[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_27 = {{rob_uop_31_ctrl_op_fcn}, {rob_uop_30_ctrl_op_fcn}, {rob_uop_29_ctrl_op_fcn}, {rob_uop_28_ctrl_op_fcn}, {rob_uop_27_ctrl_op_fcn}, {rob_uop_26_ctrl_op_fcn}, {rob_uop_25_ctrl_op_fcn}, {rob_uop_24_ctrl_op_fcn}, {rob_uop_23_ctrl_op_fcn}, {rob_uop_22_ctrl_op_fcn}, {rob_uop_21_ctrl_op_fcn}, {rob_uop_20_ctrl_op_fcn}, {rob_uop_19_ctrl_op_fcn}, {rob_uop_18_ctrl_op_fcn}, {rob_uop_17_ctrl_op_fcn}, {rob_uop_16_ctrl_op_fcn}, {rob_uop_15_ctrl_op_fcn}, {rob_uop_14_ctrl_op_fcn}, {rob_uop_13_ctrl_op_fcn}, {rob_uop_12_ctrl_op_fcn}, {rob_uop_11_ctrl_op_fcn}, {rob_uop_10_ctrl_op_fcn}, {rob_uop_9_ctrl_op_fcn}, {rob_uop_8_ctrl_op_fcn}, {rob_uop_7_ctrl_op_fcn}, {rob_uop_6_ctrl_op_fcn}, {rob_uop_5_ctrl_op_fcn}, {rob_uop_4_ctrl_op_fcn}, {rob_uop_3_ctrl_op_fcn}, {rob_uop_2_ctrl_op_fcn}, {rob_uop_1_ctrl_op_fcn}, {rob_uop_0_ctrl_op_fcn}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_op_fcn_0 = _GEN_27[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_28 = {{rob_uop_31_ctrl_fcn_dw}, {rob_uop_30_ctrl_fcn_dw}, {rob_uop_29_ctrl_fcn_dw}, {rob_uop_28_ctrl_fcn_dw}, {rob_uop_27_ctrl_fcn_dw}, {rob_uop_26_ctrl_fcn_dw}, {rob_uop_25_ctrl_fcn_dw}, {rob_uop_24_ctrl_fcn_dw}, {rob_uop_23_ctrl_fcn_dw}, {rob_uop_22_ctrl_fcn_dw}, {rob_uop_21_ctrl_fcn_dw}, {rob_uop_20_ctrl_fcn_dw}, {rob_uop_19_ctrl_fcn_dw}, {rob_uop_18_ctrl_fcn_dw}, {rob_uop_17_ctrl_fcn_dw}, {rob_uop_16_ctrl_fcn_dw}, {rob_uop_15_ctrl_fcn_dw}, {rob_uop_14_ctrl_fcn_dw}, {rob_uop_13_ctrl_fcn_dw}, {rob_uop_12_ctrl_fcn_dw}, {rob_uop_11_ctrl_fcn_dw}, {rob_uop_10_ctrl_fcn_dw}, {rob_uop_9_ctrl_fcn_dw}, {rob_uop_8_ctrl_fcn_dw}, {rob_uop_7_ctrl_fcn_dw}, {rob_uop_6_ctrl_fcn_dw}, {rob_uop_5_ctrl_fcn_dw}, {rob_uop_4_ctrl_fcn_dw}, {rob_uop_3_ctrl_fcn_dw}, {rob_uop_2_ctrl_fcn_dw}, {rob_uop_1_ctrl_fcn_dw}, {rob_uop_0_ctrl_fcn_dw}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_fcn_dw_0 = _GEN_28[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_29 = {{rob_uop_31_ctrl_csr_cmd}, {rob_uop_30_ctrl_csr_cmd}, {rob_uop_29_ctrl_csr_cmd}, {rob_uop_28_ctrl_csr_cmd}, {rob_uop_27_ctrl_csr_cmd}, {rob_uop_26_ctrl_csr_cmd}, {rob_uop_25_ctrl_csr_cmd}, {rob_uop_24_ctrl_csr_cmd}, {rob_uop_23_ctrl_csr_cmd}, {rob_uop_22_ctrl_csr_cmd}, {rob_uop_21_ctrl_csr_cmd}, {rob_uop_20_ctrl_csr_cmd}, {rob_uop_19_ctrl_csr_cmd}, {rob_uop_18_ctrl_csr_cmd}, {rob_uop_17_ctrl_csr_cmd}, {rob_uop_16_ctrl_csr_cmd}, {rob_uop_15_ctrl_csr_cmd}, {rob_uop_14_ctrl_csr_cmd}, {rob_uop_13_ctrl_csr_cmd}, {rob_uop_12_ctrl_csr_cmd}, {rob_uop_11_ctrl_csr_cmd}, {rob_uop_10_ctrl_csr_cmd}, {rob_uop_9_ctrl_csr_cmd}, {rob_uop_8_ctrl_csr_cmd}, {rob_uop_7_ctrl_csr_cmd}, {rob_uop_6_ctrl_csr_cmd}, {rob_uop_5_ctrl_csr_cmd}, {rob_uop_4_ctrl_csr_cmd}, {rob_uop_3_ctrl_csr_cmd}, {rob_uop_2_ctrl_csr_cmd}, {rob_uop_1_ctrl_csr_cmd}, {rob_uop_0_ctrl_csr_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_csr_cmd_0 = _GEN_29[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_30 = {{rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_load_0 = _GEN_30[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_31 = {{rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_sta_0 = _GEN_31[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_32 = {{rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ctrl_is_std_0 = _GEN_32[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_33 = {{rob_uop_31_iw_state}, {rob_uop_30_iw_state}, {rob_uop_29_iw_state}, {rob_uop_28_iw_state}, {rob_uop_27_iw_state}, {rob_uop_26_iw_state}, {rob_uop_25_iw_state}, {rob_uop_24_iw_state}, {rob_uop_23_iw_state}, {rob_uop_22_iw_state}, {rob_uop_21_iw_state}, {rob_uop_20_iw_state}, {rob_uop_19_iw_state}, {rob_uop_18_iw_state}, {rob_uop_17_iw_state}, {rob_uop_16_iw_state}, {rob_uop_15_iw_state}, {rob_uop_14_iw_state}, {rob_uop_13_iw_state}, {rob_uop_12_iw_state}, {rob_uop_11_iw_state}, {rob_uop_10_iw_state}, {rob_uop_9_iw_state}, {rob_uop_8_iw_state}, {rob_uop_7_iw_state}, {rob_uop_6_iw_state}, {rob_uop_5_iw_state}, {rob_uop_4_iw_state}, {rob_uop_3_iw_state}, {rob_uop_2_iw_state}, {rob_uop_1_iw_state}, {rob_uop_0_iw_state}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_state_0 = _GEN_33[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_34 = {{rob_uop_31_iw_p1_poisoned}, {rob_uop_30_iw_p1_poisoned}, {rob_uop_29_iw_p1_poisoned}, {rob_uop_28_iw_p1_poisoned}, {rob_uop_27_iw_p1_poisoned}, {rob_uop_26_iw_p1_poisoned}, {rob_uop_25_iw_p1_poisoned}, {rob_uop_24_iw_p1_poisoned}, {rob_uop_23_iw_p1_poisoned}, {rob_uop_22_iw_p1_poisoned}, {rob_uop_21_iw_p1_poisoned}, {rob_uop_20_iw_p1_poisoned}, {rob_uop_19_iw_p1_poisoned}, {rob_uop_18_iw_p1_poisoned}, {rob_uop_17_iw_p1_poisoned}, {rob_uop_16_iw_p1_poisoned}, {rob_uop_15_iw_p1_poisoned}, {rob_uop_14_iw_p1_poisoned}, {rob_uop_13_iw_p1_poisoned}, {rob_uop_12_iw_p1_poisoned}, {rob_uop_11_iw_p1_poisoned}, {rob_uop_10_iw_p1_poisoned}, {rob_uop_9_iw_p1_poisoned}, {rob_uop_8_iw_p1_poisoned}, {rob_uop_7_iw_p1_poisoned}, {rob_uop_6_iw_p1_poisoned}, {rob_uop_5_iw_p1_poisoned}, {rob_uop_4_iw_p1_poisoned}, {rob_uop_3_iw_p1_poisoned}, {rob_uop_2_iw_p1_poisoned}, {rob_uop_1_iw_p1_poisoned}, {rob_uop_0_iw_p1_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_p1_poisoned_0 = _GEN_34[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_35 = {{rob_uop_31_iw_p2_poisoned}, {rob_uop_30_iw_p2_poisoned}, {rob_uop_29_iw_p2_poisoned}, {rob_uop_28_iw_p2_poisoned}, {rob_uop_27_iw_p2_poisoned}, {rob_uop_26_iw_p2_poisoned}, {rob_uop_25_iw_p2_poisoned}, {rob_uop_24_iw_p2_poisoned}, {rob_uop_23_iw_p2_poisoned}, {rob_uop_22_iw_p2_poisoned}, {rob_uop_21_iw_p2_poisoned}, {rob_uop_20_iw_p2_poisoned}, {rob_uop_19_iw_p2_poisoned}, {rob_uop_18_iw_p2_poisoned}, {rob_uop_17_iw_p2_poisoned}, {rob_uop_16_iw_p2_poisoned}, {rob_uop_15_iw_p2_poisoned}, {rob_uop_14_iw_p2_poisoned}, {rob_uop_13_iw_p2_poisoned}, {rob_uop_12_iw_p2_poisoned}, {rob_uop_11_iw_p2_poisoned}, {rob_uop_10_iw_p2_poisoned}, {rob_uop_9_iw_p2_poisoned}, {rob_uop_8_iw_p2_poisoned}, {rob_uop_7_iw_p2_poisoned}, {rob_uop_6_iw_p2_poisoned}, {rob_uop_5_iw_p2_poisoned}, {rob_uop_4_iw_p2_poisoned}, {rob_uop_3_iw_p2_poisoned}, {rob_uop_2_iw_p2_poisoned}, {rob_uop_1_iw_p2_poisoned}, {rob_uop_0_iw_p2_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_iw_p2_poisoned_0 = _GEN_35[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_36 = {{rob_uop_31_is_br}, {rob_uop_30_is_br}, {rob_uop_29_is_br}, {rob_uop_28_is_br}, {rob_uop_27_is_br}, {rob_uop_26_is_br}, {rob_uop_25_is_br}, {rob_uop_24_is_br}, {rob_uop_23_is_br}, {rob_uop_22_is_br}, {rob_uop_21_is_br}, {rob_uop_20_is_br}, {rob_uop_19_is_br}, {rob_uop_18_is_br}, {rob_uop_17_is_br}, {rob_uop_16_is_br}, {rob_uop_15_is_br}, {rob_uop_14_is_br}, {rob_uop_13_is_br}, {rob_uop_12_is_br}, {rob_uop_11_is_br}, {rob_uop_10_is_br}, {rob_uop_9_is_br}, {rob_uop_8_is_br}, {rob_uop_7_is_br}, {rob_uop_6_is_br}, {rob_uop_5_is_br}, {rob_uop_4_is_br}, {rob_uop_3_is_br}, {rob_uop_2_is_br}, {rob_uop_1_is_br}, {rob_uop_0_is_br}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_br_0 = _GEN_36[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_37 = {{rob_uop_31_is_jalr}, {rob_uop_30_is_jalr}, {rob_uop_29_is_jalr}, {rob_uop_28_is_jalr}, {rob_uop_27_is_jalr}, {rob_uop_26_is_jalr}, {rob_uop_25_is_jalr}, {rob_uop_24_is_jalr}, {rob_uop_23_is_jalr}, {rob_uop_22_is_jalr}, {rob_uop_21_is_jalr}, {rob_uop_20_is_jalr}, {rob_uop_19_is_jalr}, {rob_uop_18_is_jalr}, {rob_uop_17_is_jalr}, {rob_uop_16_is_jalr}, {rob_uop_15_is_jalr}, {rob_uop_14_is_jalr}, {rob_uop_13_is_jalr}, {rob_uop_12_is_jalr}, {rob_uop_11_is_jalr}, {rob_uop_10_is_jalr}, {rob_uop_9_is_jalr}, {rob_uop_8_is_jalr}, {rob_uop_7_is_jalr}, {rob_uop_6_is_jalr}, {rob_uop_5_is_jalr}, {rob_uop_4_is_jalr}, {rob_uop_3_is_jalr}, {rob_uop_2_is_jalr}, {rob_uop_1_is_jalr}, {rob_uop_0_is_jalr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_jalr_0 = _GEN_37[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_38 = {{rob_uop_31_is_jal}, {rob_uop_30_is_jal}, {rob_uop_29_is_jal}, {rob_uop_28_is_jal}, {rob_uop_27_is_jal}, {rob_uop_26_is_jal}, {rob_uop_25_is_jal}, {rob_uop_24_is_jal}, {rob_uop_23_is_jal}, {rob_uop_22_is_jal}, {rob_uop_21_is_jal}, {rob_uop_20_is_jal}, {rob_uop_19_is_jal}, {rob_uop_18_is_jal}, {rob_uop_17_is_jal}, {rob_uop_16_is_jal}, {rob_uop_15_is_jal}, {rob_uop_14_is_jal}, {rob_uop_13_is_jal}, {rob_uop_12_is_jal}, {rob_uop_11_is_jal}, {rob_uop_10_is_jal}, {rob_uop_9_is_jal}, {rob_uop_8_is_jal}, {rob_uop_7_is_jal}, {rob_uop_6_is_jal}, {rob_uop_5_is_jal}, {rob_uop_4_is_jal}, {rob_uop_3_is_jal}, {rob_uop_2_is_jal}, {rob_uop_1_is_jal}, {rob_uop_0_is_jal}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_jal_0 = _GEN_38[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_39 = {{rob_uop_31_is_sfb}, {rob_uop_30_is_sfb}, {rob_uop_29_is_sfb}, {rob_uop_28_is_sfb}, {rob_uop_27_is_sfb}, {rob_uop_26_is_sfb}, {rob_uop_25_is_sfb}, {rob_uop_24_is_sfb}, {rob_uop_23_is_sfb}, {rob_uop_22_is_sfb}, {rob_uop_21_is_sfb}, {rob_uop_20_is_sfb}, {rob_uop_19_is_sfb}, {rob_uop_18_is_sfb}, {rob_uop_17_is_sfb}, {rob_uop_16_is_sfb}, {rob_uop_15_is_sfb}, {rob_uop_14_is_sfb}, {rob_uop_13_is_sfb}, {rob_uop_12_is_sfb}, {rob_uop_11_is_sfb}, {rob_uop_10_is_sfb}, {rob_uop_9_is_sfb}, {rob_uop_8_is_sfb}, {rob_uop_7_is_sfb}, {rob_uop_6_is_sfb}, {rob_uop_5_is_sfb}, {rob_uop_4_is_sfb}, {rob_uop_3_is_sfb}, {rob_uop_2_is_sfb}, {rob_uop_1_is_sfb}, {rob_uop_0_is_sfb}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_sfb_0 = _GEN_39[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][15:0] _GEN_40 = {{rob_uop_31_br_mask}, {rob_uop_30_br_mask}, {rob_uop_29_br_mask}, {rob_uop_28_br_mask}, {rob_uop_27_br_mask}, {rob_uop_26_br_mask}, {rob_uop_25_br_mask}, {rob_uop_24_br_mask}, {rob_uop_23_br_mask}, {rob_uop_22_br_mask}, {rob_uop_21_br_mask}, {rob_uop_20_br_mask}, {rob_uop_19_br_mask}, {rob_uop_18_br_mask}, {rob_uop_17_br_mask}, {rob_uop_16_br_mask}, {rob_uop_15_br_mask}, {rob_uop_14_br_mask}, {rob_uop_13_br_mask}, {rob_uop_12_br_mask}, {rob_uop_11_br_mask}, {rob_uop_10_br_mask}, {rob_uop_9_br_mask}, {rob_uop_8_br_mask}, {rob_uop_7_br_mask}, {rob_uop_6_br_mask}, {rob_uop_5_br_mask}, {rob_uop_4_br_mask}, {rob_uop_3_br_mask}, {rob_uop_2_br_mask}, {rob_uop_1_br_mask}, {rob_uop_0_br_mask}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_br_mask_0 = _GEN_40[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_41 = {{rob_uop_31_br_tag}, {rob_uop_30_br_tag}, {rob_uop_29_br_tag}, {rob_uop_28_br_tag}, {rob_uop_27_br_tag}, {rob_uop_26_br_tag}, {rob_uop_25_br_tag}, {rob_uop_24_br_tag}, {rob_uop_23_br_tag}, {rob_uop_22_br_tag}, {rob_uop_21_br_tag}, {rob_uop_20_br_tag}, {rob_uop_19_br_tag}, {rob_uop_18_br_tag}, {rob_uop_17_br_tag}, {rob_uop_16_br_tag}, {rob_uop_15_br_tag}, {rob_uop_14_br_tag}, {rob_uop_13_br_tag}, {rob_uop_12_br_tag}, {rob_uop_11_br_tag}, {rob_uop_10_br_tag}, {rob_uop_9_br_tag}, {rob_uop_8_br_tag}, {rob_uop_7_br_tag}, {rob_uop_6_br_tag}, {rob_uop_5_br_tag}, {rob_uop_4_br_tag}, {rob_uop_3_br_tag}, {rob_uop_2_br_tag}, {rob_uop_1_br_tag}, {rob_uop_0_br_tag}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_br_tag_0 = _GEN_41[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_42 = {{rob_uop_31_ftq_idx}, {rob_uop_30_ftq_idx}, {rob_uop_29_ftq_idx}, {rob_uop_28_ftq_idx}, {rob_uop_27_ftq_idx}, {rob_uop_26_ftq_idx}, {rob_uop_25_ftq_idx}, {rob_uop_24_ftq_idx}, {rob_uop_23_ftq_idx}, {rob_uop_22_ftq_idx}, {rob_uop_21_ftq_idx}, {rob_uop_20_ftq_idx}, {rob_uop_19_ftq_idx}, {rob_uop_18_ftq_idx}, {rob_uop_17_ftq_idx}, {rob_uop_16_ftq_idx}, {rob_uop_15_ftq_idx}, {rob_uop_14_ftq_idx}, {rob_uop_13_ftq_idx}, {rob_uop_12_ftq_idx}, {rob_uop_11_ftq_idx}, {rob_uop_10_ftq_idx}, {rob_uop_9_ftq_idx}, {rob_uop_8_ftq_idx}, {rob_uop_7_ftq_idx}, {rob_uop_6_ftq_idx}, {rob_uop_5_ftq_idx}, {rob_uop_4_ftq_idx}, {rob_uop_3_ftq_idx}, {rob_uop_2_ftq_idx}, {rob_uop_1_ftq_idx}, {rob_uop_0_ftq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ftq_idx_0 = _GEN_42[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_43 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_edge_inst_0 = _GEN_43[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_44 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_pc_lob_0 = _GEN_44[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_45 = {{rob_uop_31_taken}, {rob_uop_30_taken}, {rob_uop_29_taken}, {rob_uop_28_taken}, {rob_uop_27_taken}, {rob_uop_26_taken}, {rob_uop_25_taken}, {rob_uop_24_taken}, {rob_uop_23_taken}, {rob_uop_22_taken}, {rob_uop_21_taken}, {rob_uop_20_taken}, {rob_uop_19_taken}, {rob_uop_18_taken}, {rob_uop_17_taken}, {rob_uop_16_taken}, {rob_uop_15_taken}, {rob_uop_14_taken}, {rob_uop_13_taken}, {rob_uop_12_taken}, {rob_uop_11_taken}, {rob_uop_10_taken}, {rob_uop_9_taken}, {rob_uop_8_taken}, {rob_uop_7_taken}, {rob_uop_6_taken}, {rob_uop_5_taken}, {rob_uop_4_taken}, {rob_uop_3_taken}, {rob_uop_2_taken}, {rob_uop_1_taken}, {rob_uop_0_taken}}; // @[rob.scala:311:28, :415:25]
wire [31:0][19:0] _GEN_46 = {{rob_uop_31_imm_packed}, {rob_uop_30_imm_packed}, {rob_uop_29_imm_packed}, {rob_uop_28_imm_packed}, {rob_uop_27_imm_packed}, {rob_uop_26_imm_packed}, {rob_uop_25_imm_packed}, {rob_uop_24_imm_packed}, {rob_uop_23_imm_packed}, {rob_uop_22_imm_packed}, {rob_uop_21_imm_packed}, {rob_uop_20_imm_packed}, {rob_uop_19_imm_packed}, {rob_uop_18_imm_packed}, {rob_uop_17_imm_packed}, {rob_uop_16_imm_packed}, {rob_uop_15_imm_packed}, {rob_uop_14_imm_packed}, {rob_uop_13_imm_packed}, {rob_uop_12_imm_packed}, {rob_uop_11_imm_packed}, {rob_uop_10_imm_packed}, {rob_uop_9_imm_packed}, {rob_uop_8_imm_packed}, {rob_uop_7_imm_packed}, {rob_uop_6_imm_packed}, {rob_uop_5_imm_packed}, {rob_uop_4_imm_packed}, {rob_uop_3_imm_packed}, {rob_uop_2_imm_packed}, {rob_uop_1_imm_packed}, {rob_uop_0_imm_packed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_imm_packed_0 = _GEN_46[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][11:0] _GEN_47 = {{rob_uop_31_csr_addr}, {rob_uop_30_csr_addr}, {rob_uop_29_csr_addr}, {rob_uop_28_csr_addr}, {rob_uop_27_csr_addr}, {rob_uop_26_csr_addr}, {rob_uop_25_csr_addr}, {rob_uop_24_csr_addr}, {rob_uop_23_csr_addr}, {rob_uop_22_csr_addr}, {rob_uop_21_csr_addr}, {rob_uop_20_csr_addr}, {rob_uop_19_csr_addr}, {rob_uop_18_csr_addr}, {rob_uop_17_csr_addr}, {rob_uop_16_csr_addr}, {rob_uop_15_csr_addr}, {rob_uop_14_csr_addr}, {rob_uop_13_csr_addr}, {rob_uop_12_csr_addr}, {rob_uop_11_csr_addr}, {rob_uop_10_csr_addr}, {rob_uop_9_csr_addr}, {rob_uop_8_csr_addr}, {rob_uop_7_csr_addr}, {rob_uop_6_csr_addr}, {rob_uop_5_csr_addr}, {rob_uop_4_csr_addr}, {rob_uop_3_csr_addr}, {rob_uop_2_csr_addr}, {rob_uop_1_csr_addr}, {rob_uop_0_csr_addr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_csr_addr_0 = _GEN_47[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_48 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_rob_idx_0 = _GEN_48[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_49 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldq_idx_0 = _GEN_49[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_50 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_stq_idx_0 = _GEN_50[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_51 = {{rob_uop_31_rxq_idx}, {rob_uop_30_rxq_idx}, {rob_uop_29_rxq_idx}, {rob_uop_28_rxq_idx}, {rob_uop_27_rxq_idx}, {rob_uop_26_rxq_idx}, {rob_uop_25_rxq_idx}, {rob_uop_24_rxq_idx}, {rob_uop_23_rxq_idx}, {rob_uop_22_rxq_idx}, {rob_uop_21_rxq_idx}, {rob_uop_20_rxq_idx}, {rob_uop_19_rxq_idx}, {rob_uop_18_rxq_idx}, {rob_uop_17_rxq_idx}, {rob_uop_16_rxq_idx}, {rob_uop_15_rxq_idx}, {rob_uop_14_rxq_idx}, {rob_uop_13_rxq_idx}, {rob_uop_12_rxq_idx}, {rob_uop_11_rxq_idx}, {rob_uop_10_rxq_idx}, {rob_uop_9_rxq_idx}, {rob_uop_8_rxq_idx}, {rob_uop_7_rxq_idx}, {rob_uop_6_rxq_idx}, {rob_uop_5_rxq_idx}, {rob_uop_4_rxq_idx}, {rob_uop_3_rxq_idx}, {rob_uop_2_rxq_idx}, {rob_uop_1_rxq_idx}, {rob_uop_0_rxq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_rxq_idx_0 = _GEN_51[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_52 = {{rob_uop_31_pdst}, {rob_uop_30_pdst}, {rob_uop_29_pdst}, {rob_uop_28_pdst}, {rob_uop_27_pdst}, {rob_uop_26_pdst}, {rob_uop_25_pdst}, {rob_uop_24_pdst}, {rob_uop_23_pdst}, {rob_uop_22_pdst}, {rob_uop_21_pdst}, {rob_uop_20_pdst}, {rob_uop_19_pdst}, {rob_uop_18_pdst}, {rob_uop_17_pdst}, {rob_uop_16_pdst}, {rob_uop_15_pdst}, {rob_uop_14_pdst}, {rob_uop_13_pdst}, {rob_uop_12_pdst}, {rob_uop_11_pdst}, {rob_uop_10_pdst}, {rob_uop_9_pdst}, {rob_uop_8_pdst}, {rob_uop_7_pdst}, {rob_uop_6_pdst}, {rob_uop_5_pdst}, {rob_uop_4_pdst}, {rob_uop_3_pdst}, {rob_uop_2_pdst}, {rob_uop_1_pdst}, {rob_uop_0_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_pdst_0 = _GEN_52[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_53 = {{rob_uop_31_prs1}, {rob_uop_30_prs1}, {rob_uop_29_prs1}, {rob_uop_28_prs1}, {rob_uop_27_prs1}, {rob_uop_26_prs1}, {rob_uop_25_prs1}, {rob_uop_24_prs1}, {rob_uop_23_prs1}, {rob_uop_22_prs1}, {rob_uop_21_prs1}, {rob_uop_20_prs1}, {rob_uop_19_prs1}, {rob_uop_18_prs1}, {rob_uop_17_prs1}, {rob_uop_16_prs1}, {rob_uop_15_prs1}, {rob_uop_14_prs1}, {rob_uop_13_prs1}, {rob_uop_12_prs1}, {rob_uop_11_prs1}, {rob_uop_10_prs1}, {rob_uop_9_prs1}, {rob_uop_8_prs1}, {rob_uop_7_prs1}, {rob_uop_6_prs1}, {rob_uop_5_prs1}, {rob_uop_4_prs1}, {rob_uop_3_prs1}, {rob_uop_2_prs1}, {rob_uop_1_prs1}, {rob_uop_0_prs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs1_0 = _GEN_53[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_54 = {{rob_uop_31_prs2}, {rob_uop_30_prs2}, {rob_uop_29_prs2}, {rob_uop_28_prs2}, {rob_uop_27_prs2}, {rob_uop_26_prs2}, {rob_uop_25_prs2}, {rob_uop_24_prs2}, {rob_uop_23_prs2}, {rob_uop_22_prs2}, {rob_uop_21_prs2}, {rob_uop_20_prs2}, {rob_uop_19_prs2}, {rob_uop_18_prs2}, {rob_uop_17_prs2}, {rob_uop_16_prs2}, {rob_uop_15_prs2}, {rob_uop_14_prs2}, {rob_uop_13_prs2}, {rob_uop_12_prs2}, {rob_uop_11_prs2}, {rob_uop_10_prs2}, {rob_uop_9_prs2}, {rob_uop_8_prs2}, {rob_uop_7_prs2}, {rob_uop_6_prs2}, {rob_uop_5_prs2}, {rob_uop_4_prs2}, {rob_uop_3_prs2}, {rob_uop_2_prs2}, {rob_uop_1_prs2}, {rob_uop_0_prs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs2_0 = _GEN_54[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_55 = {{rob_uop_31_prs3}, {rob_uop_30_prs3}, {rob_uop_29_prs3}, {rob_uop_28_prs3}, {rob_uop_27_prs3}, {rob_uop_26_prs3}, {rob_uop_25_prs3}, {rob_uop_24_prs3}, {rob_uop_23_prs3}, {rob_uop_22_prs3}, {rob_uop_21_prs3}, {rob_uop_20_prs3}, {rob_uop_19_prs3}, {rob_uop_18_prs3}, {rob_uop_17_prs3}, {rob_uop_16_prs3}, {rob_uop_15_prs3}, {rob_uop_14_prs3}, {rob_uop_13_prs3}, {rob_uop_12_prs3}, {rob_uop_11_prs3}, {rob_uop_10_prs3}, {rob_uop_9_prs3}, {rob_uop_8_prs3}, {rob_uop_7_prs3}, {rob_uop_6_prs3}, {rob_uop_5_prs3}, {rob_uop_4_prs3}, {rob_uop_3_prs3}, {rob_uop_2_prs3}, {rob_uop_1_prs3}, {rob_uop_0_prs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs3_0 = _GEN_55[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_56 = {{rob_uop_31_prs1_busy}, {rob_uop_30_prs1_busy}, {rob_uop_29_prs1_busy}, {rob_uop_28_prs1_busy}, {rob_uop_27_prs1_busy}, {rob_uop_26_prs1_busy}, {rob_uop_25_prs1_busy}, {rob_uop_24_prs1_busy}, {rob_uop_23_prs1_busy}, {rob_uop_22_prs1_busy}, {rob_uop_21_prs1_busy}, {rob_uop_20_prs1_busy}, {rob_uop_19_prs1_busy}, {rob_uop_18_prs1_busy}, {rob_uop_17_prs1_busy}, {rob_uop_16_prs1_busy}, {rob_uop_15_prs1_busy}, {rob_uop_14_prs1_busy}, {rob_uop_13_prs1_busy}, {rob_uop_12_prs1_busy}, {rob_uop_11_prs1_busy}, {rob_uop_10_prs1_busy}, {rob_uop_9_prs1_busy}, {rob_uop_8_prs1_busy}, {rob_uop_7_prs1_busy}, {rob_uop_6_prs1_busy}, {rob_uop_5_prs1_busy}, {rob_uop_4_prs1_busy}, {rob_uop_3_prs1_busy}, {rob_uop_2_prs1_busy}, {rob_uop_1_prs1_busy}, {rob_uop_0_prs1_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs1_busy_0 = _GEN_56[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_57 = {{rob_uop_31_prs2_busy}, {rob_uop_30_prs2_busy}, {rob_uop_29_prs2_busy}, {rob_uop_28_prs2_busy}, {rob_uop_27_prs2_busy}, {rob_uop_26_prs2_busy}, {rob_uop_25_prs2_busy}, {rob_uop_24_prs2_busy}, {rob_uop_23_prs2_busy}, {rob_uop_22_prs2_busy}, {rob_uop_21_prs2_busy}, {rob_uop_20_prs2_busy}, {rob_uop_19_prs2_busy}, {rob_uop_18_prs2_busy}, {rob_uop_17_prs2_busy}, {rob_uop_16_prs2_busy}, {rob_uop_15_prs2_busy}, {rob_uop_14_prs2_busy}, {rob_uop_13_prs2_busy}, {rob_uop_12_prs2_busy}, {rob_uop_11_prs2_busy}, {rob_uop_10_prs2_busy}, {rob_uop_9_prs2_busy}, {rob_uop_8_prs2_busy}, {rob_uop_7_prs2_busy}, {rob_uop_6_prs2_busy}, {rob_uop_5_prs2_busy}, {rob_uop_4_prs2_busy}, {rob_uop_3_prs2_busy}, {rob_uop_2_prs2_busy}, {rob_uop_1_prs2_busy}, {rob_uop_0_prs2_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs2_busy_0 = _GEN_57[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_58 = {{rob_uop_31_prs3_busy}, {rob_uop_30_prs3_busy}, {rob_uop_29_prs3_busy}, {rob_uop_28_prs3_busy}, {rob_uop_27_prs3_busy}, {rob_uop_26_prs3_busy}, {rob_uop_25_prs3_busy}, {rob_uop_24_prs3_busy}, {rob_uop_23_prs3_busy}, {rob_uop_22_prs3_busy}, {rob_uop_21_prs3_busy}, {rob_uop_20_prs3_busy}, {rob_uop_19_prs3_busy}, {rob_uop_18_prs3_busy}, {rob_uop_17_prs3_busy}, {rob_uop_16_prs3_busy}, {rob_uop_15_prs3_busy}, {rob_uop_14_prs3_busy}, {rob_uop_13_prs3_busy}, {rob_uop_12_prs3_busy}, {rob_uop_11_prs3_busy}, {rob_uop_10_prs3_busy}, {rob_uop_9_prs3_busy}, {rob_uop_8_prs3_busy}, {rob_uop_7_prs3_busy}, {rob_uop_6_prs3_busy}, {rob_uop_5_prs3_busy}, {rob_uop_4_prs3_busy}, {rob_uop_3_prs3_busy}, {rob_uop_2_prs3_busy}, {rob_uop_1_prs3_busy}, {rob_uop_0_prs3_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_prs3_busy_0 = _GEN_58[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_59 = {{rob_uop_31_stale_pdst}, {rob_uop_30_stale_pdst}, {rob_uop_29_stale_pdst}, {rob_uop_28_stale_pdst}, {rob_uop_27_stale_pdst}, {rob_uop_26_stale_pdst}, {rob_uop_25_stale_pdst}, {rob_uop_24_stale_pdst}, {rob_uop_23_stale_pdst}, {rob_uop_22_stale_pdst}, {rob_uop_21_stale_pdst}, {rob_uop_20_stale_pdst}, {rob_uop_19_stale_pdst}, {rob_uop_18_stale_pdst}, {rob_uop_17_stale_pdst}, {rob_uop_16_stale_pdst}, {rob_uop_15_stale_pdst}, {rob_uop_14_stale_pdst}, {rob_uop_13_stale_pdst}, {rob_uop_12_stale_pdst}, {rob_uop_11_stale_pdst}, {rob_uop_10_stale_pdst}, {rob_uop_9_stale_pdst}, {rob_uop_8_stale_pdst}, {rob_uop_7_stale_pdst}, {rob_uop_6_stale_pdst}, {rob_uop_5_stale_pdst}, {rob_uop_4_stale_pdst}, {rob_uop_3_stale_pdst}, {rob_uop_2_stale_pdst}, {rob_uop_1_stale_pdst}, {rob_uop_0_stale_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_stale_pdst_0 = _GEN_59[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_60 = {{rob_uop_31_exception}, {rob_uop_30_exception}, {rob_uop_29_exception}, {rob_uop_28_exception}, {rob_uop_27_exception}, {rob_uop_26_exception}, {rob_uop_25_exception}, {rob_uop_24_exception}, {rob_uop_23_exception}, {rob_uop_22_exception}, {rob_uop_21_exception}, {rob_uop_20_exception}, {rob_uop_19_exception}, {rob_uop_18_exception}, {rob_uop_17_exception}, {rob_uop_16_exception}, {rob_uop_15_exception}, {rob_uop_14_exception}, {rob_uop_13_exception}, {rob_uop_12_exception}, {rob_uop_11_exception}, {rob_uop_10_exception}, {rob_uop_9_exception}, {rob_uop_8_exception}, {rob_uop_7_exception}, {rob_uop_6_exception}, {rob_uop_5_exception}, {rob_uop_4_exception}, {rob_uop_3_exception}, {rob_uop_2_exception}, {rob_uop_1_exception}, {rob_uop_0_exception}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_exception_0 = _GEN_60[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][63:0] _GEN_61 = {{rob_uop_31_exc_cause}, {rob_uop_30_exc_cause}, {rob_uop_29_exc_cause}, {rob_uop_28_exc_cause}, {rob_uop_27_exc_cause}, {rob_uop_26_exc_cause}, {rob_uop_25_exc_cause}, {rob_uop_24_exc_cause}, {rob_uop_23_exc_cause}, {rob_uop_22_exc_cause}, {rob_uop_21_exc_cause}, {rob_uop_20_exc_cause}, {rob_uop_19_exc_cause}, {rob_uop_18_exc_cause}, {rob_uop_17_exc_cause}, {rob_uop_16_exc_cause}, {rob_uop_15_exc_cause}, {rob_uop_14_exc_cause}, {rob_uop_13_exc_cause}, {rob_uop_12_exc_cause}, {rob_uop_11_exc_cause}, {rob_uop_10_exc_cause}, {rob_uop_9_exc_cause}, {rob_uop_8_exc_cause}, {rob_uop_7_exc_cause}, {rob_uop_6_exc_cause}, {rob_uop_5_exc_cause}, {rob_uop_4_exc_cause}, {rob_uop_3_exc_cause}, {rob_uop_2_exc_cause}, {rob_uop_1_exc_cause}, {rob_uop_0_exc_cause}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_exc_cause_0 = _GEN_61[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_62 = {{rob_uop_31_bypassable}, {rob_uop_30_bypassable}, {rob_uop_29_bypassable}, {rob_uop_28_bypassable}, {rob_uop_27_bypassable}, {rob_uop_26_bypassable}, {rob_uop_25_bypassable}, {rob_uop_24_bypassable}, {rob_uop_23_bypassable}, {rob_uop_22_bypassable}, {rob_uop_21_bypassable}, {rob_uop_20_bypassable}, {rob_uop_19_bypassable}, {rob_uop_18_bypassable}, {rob_uop_17_bypassable}, {rob_uop_16_bypassable}, {rob_uop_15_bypassable}, {rob_uop_14_bypassable}, {rob_uop_13_bypassable}, {rob_uop_12_bypassable}, {rob_uop_11_bypassable}, {rob_uop_10_bypassable}, {rob_uop_9_bypassable}, {rob_uop_8_bypassable}, {rob_uop_7_bypassable}, {rob_uop_6_bypassable}, {rob_uop_5_bypassable}, {rob_uop_4_bypassable}, {rob_uop_3_bypassable}, {rob_uop_2_bypassable}, {rob_uop_1_bypassable}, {rob_uop_0_bypassable}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bypassable_0 = _GEN_62[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_63 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_cmd_0 = _GEN_63[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_64 = {{rob_uop_31_mem_size}, {rob_uop_30_mem_size}, {rob_uop_29_mem_size}, {rob_uop_28_mem_size}, {rob_uop_27_mem_size}, {rob_uop_26_mem_size}, {rob_uop_25_mem_size}, {rob_uop_24_mem_size}, {rob_uop_23_mem_size}, {rob_uop_22_mem_size}, {rob_uop_21_mem_size}, {rob_uop_20_mem_size}, {rob_uop_19_mem_size}, {rob_uop_18_mem_size}, {rob_uop_17_mem_size}, {rob_uop_16_mem_size}, {rob_uop_15_mem_size}, {rob_uop_14_mem_size}, {rob_uop_13_mem_size}, {rob_uop_12_mem_size}, {rob_uop_11_mem_size}, {rob_uop_10_mem_size}, {rob_uop_9_mem_size}, {rob_uop_8_mem_size}, {rob_uop_7_mem_size}, {rob_uop_6_mem_size}, {rob_uop_5_mem_size}, {rob_uop_4_mem_size}, {rob_uop_3_mem_size}, {rob_uop_2_mem_size}, {rob_uop_1_mem_size}, {rob_uop_0_mem_size}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_size_0 = _GEN_64[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_65 = {{rob_uop_31_mem_signed}, {rob_uop_30_mem_signed}, {rob_uop_29_mem_signed}, {rob_uop_28_mem_signed}, {rob_uop_27_mem_signed}, {rob_uop_26_mem_signed}, {rob_uop_25_mem_signed}, {rob_uop_24_mem_signed}, {rob_uop_23_mem_signed}, {rob_uop_22_mem_signed}, {rob_uop_21_mem_signed}, {rob_uop_20_mem_signed}, {rob_uop_19_mem_signed}, {rob_uop_18_mem_signed}, {rob_uop_17_mem_signed}, {rob_uop_16_mem_signed}, {rob_uop_15_mem_signed}, {rob_uop_14_mem_signed}, {rob_uop_13_mem_signed}, {rob_uop_12_mem_signed}, {rob_uop_11_mem_signed}, {rob_uop_10_mem_signed}, {rob_uop_9_mem_signed}, {rob_uop_8_mem_signed}, {rob_uop_7_mem_signed}, {rob_uop_6_mem_signed}, {rob_uop_5_mem_signed}, {rob_uop_4_mem_signed}, {rob_uop_3_mem_signed}, {rob_uop_2_mem_signed}, {rob_uop_1_mem_signed}, {rob_uop_0_mem_signed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_mem_signed_0 = _GEN_65[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_66 = {{rob_uop_31_is_fence}, {rob_uop_30_is_fence}, {rob_uop_29_is_fence}, {rob_uop_28_is_fence}, {rob_uop_27_is_fence}, {rob_uop_26_is_fence}, {rob_uop_25_is_fence}, {rob_uop_24_is_fence}, {rob_uop_23_is_fence}, {rob_uop_22_is_fence}, {rob_uop_21_is_fence}, {rob_uop_20_is_fence}, {rob_uop_19_is_fence}, {rob_uop_18_is_fence}, {rob_uop_17_is_fence}, {rob_uop_16_is_fence}, {rob_uop_15_is_fence}, {rob_uop_14_is_fence}, {rob_uop_13_is_fence}, {rob_uop_12_is_fence}, {rob_uop_11_is_fence}, {rob_uop_10_is_fence}, {rob_uop_9_is_fence}, {rob_uop_8_is_fence}, {rob_uop_7_is_fence}, {rob_uop_6_is_fence}, {rob_uop_5_is_fence}, {rob_uop_4_is_fence}, {rob_uop_3_is_fence}, {rob_uop_2_is_fence}, {rob_uop_1_is_fence}, {rob_uop_0_is_fence}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_fence_0 = _GEN_66[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_67 = {{rob_uop_31_is_fencei}, {rob_uop_30_is_fencei}, {rob_uop_29_is_fencei}, {rob_uop_28_is_fencei}, {rob_uop_27_is_fencei}, {rob_uop_26_is_fencei}, {rob_uop_25_is_fencei}, {rob_uop_24_is_fencei}, {rob_uop_23_is_fencei}, {rob_uop_22_is_fencei}, {rob_uop_21_is_fencei}, {rob_uop_20_is_fencei}, {rob_uop_19_is_fencei}, {rob_uop_18_is_fencei}, {rob_uop_17_is_fencei}, {rob_uop_16_is_fencei}, {rob_uop_15_is_fencei}, {rob_uop_14_is_fencei}, {rob_uop_13_is_fencei}, {rob_uop_12_is_fencei}, {rob_uop_11_is_fencei}, {rob_uop_10_is_fencei}, {rob_uop_9_is_fencei}, {rob_uop_8_is_fencei}, {rob_uop_7_is_fencei}, {rob_uop_6_is_fencei}, {rob_uop_5_is_fencei}, {rob_uop_4_is_fencei}, {rob_uop_3_is_fencei}, {rob_uop_2_is_fencei}, {rob_uop_1_is_fencei}, {rob_uop_0_is_fencei}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_fencei_0 = _GEN_67[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_68 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_amo_0 = _GEN_68[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_69 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uses_ldq_0 = _GEN_69[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_70 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_uses_stq_0 = _GEN_70[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_71 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_sys_pc2epc_0 = _GEN_71[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_72 = {{rob_uop_31_is_unique}, {rob_uop_30_is_unique}, {rob_uop_29_is_unique}, {rob_uop_28_is_unique}, {rob_uop_27_is_unique}, {rob_uop_26_is_unique}, {rob_uop_25_is_unique}, {rob_uop_24_is_unique}, {rob_uop_23_is_unique}, {rob_uop_22_is_unique}, {rob_uop_21_is_unique}, {rob_uop_20_is_unique}, {rob_uop_19_is_unique}, {rob_uop_18_is_unique}, {rob_uop_17_is_unique}, {rob_uop_16_is_unique}, {rob_uop_15_is_unique}, {rob_uop_14_is_unique}, {rob_uop_13_is_unique}, {rob_uop_12_is_unique}, {rob_uop_11_is_unique}, {rob_uop_10_is_unique}, {rob_uop_9_is_unique}, {rob_uop_8_is_unique}, {rob_uop_7_is_unique}, {rob_uop_6_is_unique}, {rob_uop_5_is_unique}, {rob_uop_4_is_unique}, {rob_uop_3_is_unique}, {rob_uop_2_is_unique}, {rob_uop_1_is_unique}, {rob_uop_0_is_unique}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_is_unique_0 = _GEN_72[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_73 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_flush_on_commit_0 = _GEN_73[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_74 = {{rob_uop_31_ldst_is_rs1}, {rob_uop_30_ldst_is_rs1}, {rob_uop_29_ldst_is_rs1}, {rob_uop_28_ldst_is_rs1}, {rob_uop_27_ldst_is_rs1}, {rob_uop_26_ldst_is_rs1}, {rob_uop_25_ldst_is_rs1}, {rob_uop_24_ldst_is_rs1}, {rob_uop_23_ldst_is_rs1}, {rob_uop_22_ldst_is_rs1}, {rob_uop_21_ldst_is_rs1}, {rob_uop_20_ldst_is_rs1}, {rob_uop_19_ldst_is_rs1}, {rob_uop_18_ldst_is_rs1}, {rob_uop_17_ldst_is_rs1}, {rob_uop_16_ldst_is_rs1}, {rob_uop_15_ldst_is_rs1}, {rob_uop_14_ldst_is_rs1}, {rob_uop_13_ldst_is_rs1}, {rob_uop_12_ldst_is_rs1}, {rob_uop_11_ldst_is_rs1}, {rob_uop_10_ldst_is_rs1}, {rob_uop_9_ldst_is_rs1}, {rob_uop_8_ldst_is_rs1}, {rob_uop_7_ldst_is_rs1}, {rob_uop_6_ldst_is_rs1}, {rob_uop_5_ldst_is_rs1}, {rob_uop_4_ldst_is_rs1}, {rob_uop_3_ldst_is_rs1}, {rob_uop_2_ldst_is_rs1}, {rob_uop_1_ldst_is_rs1}, {rob_uop_0_ldst_is_rs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_is_rs1_0 = _GEN_74[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_75 = {{rob_uop_31_ldst}, {rob_uop_30_ldst}, {rob_uop_29_ldst}, {rob_uop_28_ldst}, {rob_uop_27_ldst}, {rob_uop_26_ldst}, {rob_uop_25_ldst}, {rob_uop_24_ldst}, {rob_uop_23_ldst}, {rob_uop_22_ldst}, {rob_uop_21_ldst}, {rob_uop_20_ldst}, {rob_uop_19_ldst}, {rob_uop_18_ldst}, {rob_uop_17_ldst}, {rob_uop_16_ldst}, {rob_uop_15_ldst}, {rob_uop_14_ldst}, {rob_uop_13_ldst}, {rob_uop_12_ldst}, {rob_uop_11_ldst}, {rob_uop_10_ldst}, {rob_uop_9_ldst}, {rob_uop_8_ldst}, {rob_uop_7_ldst}, {rob_uop_6_ldst}, {rob_uop_5_ldst}, {rob_uop_4_ldst}, {rob_uop_3_ldst}, {rob_uop_2_ldst}, {rob_uop_1_ldst}, {rob_uop_0_ldst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_0 = _GEN_75[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_76 = {{rob_uop_31_lrs1}, {rob_uop_30_lrs1}, {rob_uop_29_lrs1}, {rob_uop_28_lrs1}, {rob_uop_27_lrs1}, {rob_uop_26_lrs1}, {rob_uop_25_lrs1}, {rob_uop_24_lrs1}, {rob_uop_23_lrs1}, {rob_uop_22_lrs1}, {rob_uop_21_lrs1}, {rob_uop_20_lrs1}, {rob_uop_19_lrs1}, {rob_uop_18_lrs1}, {rob_uop_17_lrs1}, {rob_uop_16_lrs1}, {rob_uop_15_lrs1}, {rob_uop_14_lrs1}, {rob_uop_13_lrs1}, {rob_uop_12_lrs1}, {rob_uop_11_lrs1}, {rob_uop_10_lrs1}, {rob_uop_9_lrs1}, {rob_uop_8_lrs1}, {rob_uop_7_lrs1}, {rob_uop_6_lrs1}, {rob_uop_5_lrs1}, {rob_uop_4_lrs1}, {rob_uop_3_lrs1}, {rob_uop_2_lrs1}, {rob_uop_1_lrs1}, {rob_uop_0_lrs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs1_0 = _GEN_76[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_77 = {{rob_uop_31_lrs2}, {rob_uop_30_lrs2}, {rob_uop_29_lrs2}, {rob_uop_28_lrs2}, {rob_uop_27_lrs2}, {rob_uop_26_lrs2}, {rob_uop_25_lrs2}, {rob_uop_24_lrs2}, {rob_uop_23_lrs2}, {rob_uop_22_lrs2}, {rob_uop_21_lrs2}, {rob_uop_20_lrs2}, {rob_uop_19_lrs2}, {rob_uop_18_lrs2}, {rob_uop_17_lrs2}, {rob_uop_16_lrs2}, {rob_uop_15_lrs2}, {rob_uop_14_lrs2}, {rob_uop_13_lrs2}, {rob_uop_12_lrs2}, {rob_uop_11_lrs2}, {rob_uop_10_lrs2}, {rob_uop_9_lrs2}, {rob_uop_8_lrs2}, {rob_uop_7_lrs2}, {rob_uop_6_lrs2}, {rob_uop_5_lrs2}, {rob_uop_4_lrs2}, {rob_uop_3_lrs2}, {rob_uop_2_lrs2}, {rob_uop_1_lrs2}, {rob_uop_0_lrs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs2_0 = _GEN_77[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_78 = {{rob_uop_31_lrs3}, {rob_uop_30_lrs3}, {rob_uop_29_lrs3}, {rob_uop_28_lrs3}, {rob_uop_27_lrs3}, {rob_uop_26_lrs3}, {rob_uop_25_lrs3}, {rob_uop_24_lrs3}, {rob_uop_23_lrs3}, {rob_uop_22_lrs3}, {rob_uop_21_lrs3}, {rob_uop_20_lrs3}, {rob_uop_19_lrs3}, {rob_uop_18_lrs3}, {rob_uop_17_lrs3}, {rob_uop_16_lrs3}, {rob_uop_15_lrs3}, {rob_uop_14_lrs3}, {rob_uop_13_lrs3}, {rob_uop_12_lrs3}, {rob_uop_11_lrs3}, {rob_uop_10_lrs3}, {rob_uop_9_lrs3}, {rob_uop_8_lrs3}, {rob_uop_7_lrs3}, {rob_uop_6_lrs3}, {rob_uop_5_lrs3}, {rob_uop_4_lrs3}, {rob_uop_3_lrs3}, {rob_uop_2_lrs3}, {rob_uop_1_lrs3}, {rob_uop_0_lrs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs3_0 = _GEN_78[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_79 = {{rob_uop_31_ldst_val}, {rob_uop_30_ldst_val}, {rob_uop_29_ldst_val}, {rob_uop_28_ldst_val}, {rob_uop_27_ldst_val}, {rob_uop_26_ldst_val}, {rob_uop_25_ldst_val}, {rob_uop_24_ldst_val}, {rob_uop_23_ldst_val}, {rob_uop_22_ldst_val}, {rob_uop_21_ldst_val}, {rob_uop_20_ldst_val}, {rob_uop_19_ldst_val}, {rob_uop_18_ldst_val}, {rob_uop_17_ldst_val}, {rob_uop_16_ldst_val}, {rob_uop_15_ldst_val}, {rob_uop_14_ldst_val}, {rob_uop_13_ldst_val}, {rob_uop_12_ldst_val}, {rob_uop_11_ldst_val}, {rob_uop_10_ldst_val}, {rob_uop_9_ldst_val}, {rob_uop_8_ldst_val}, {rob_uop_7_ldst_val}, {rob_uop_6_ldst_val}, {rob_uop_5_ldst_val}, {rob_uop_4_ldst_val}, {rob_uop_3_ldst_val}, {rob_uop_2_ldst_val}, {rob_uop_1_ldst_val}, {rob_uop_0_ldst_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_ldst_val_0 = _GEN_79[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_80 = {{rob_uop_31_dst_rtype}, {rob_uop_30_dst_rtype}, {rob_uop_29_dst_rtype}, {rob_uop_28_dst_rtype}, {rob_uop_27_dst_rtype}, {rob_uop_26_dst_rtype}, {rob_uop_25_dst_rtype}, {rob_uop_24_dst_rtype}, {rob_uop_23_dst_rtype}, {rob_uop_22_dst_rtype}, {rob_uop_21_dst_rtype}, {rob_uop_20_dst_rtype}, {rob_uop_19_dst_rtype}, {rob_uop_18_dst_rtype}, {rob_uop_17_dst_rtype}, {rob_uop_16_dst_rtype}, {rob_uop_15_dst_rtype}, {rob_uop_14_dst_rtype}, {rob_uop_13_dst_rtype}, {rob_uop_12_dst_rtype}, {rob_uop_11_dst_rtype}, {rob_uop_10_dst_rtype}, {rob_uop_9_dst_rtype}, {rob_uop_8_dst_rtype}, {rob_uop_7_dst_rtype}, {rob_uop_6_dst_rtype}, {rob_uop_5_dst_rtype}, {rob_uop_4_dst_rtype}, {rob_uop_3_dst_rtype}, {rob_uop_2_dst_rtype}, {rob_uop_1_dst_rtype}, {rob_uop_0_dst_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_dst_rtype_0 = _GEN_80[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_81 = {{rob_uop_31_lrs1_rtype}, {rob_uop_30_lrs1_rtype}, {rob_uop_29_lrs1_rtype}, {rob_uop_28_lrs1_rtype}, {rob_uop_27_lrs1_rtype}, {rob_uop_26_lrs1_rtype}, {rob_uop_25_lrs1_rtype}, {rob_uop_24_lrs1_rtype}, {rob_uop_23_lrs1_rtype}, {rob_uop_22_lrs1_rtype}, {rob_uop_21_lrs1_rtype}, {rob_uop_20_lrs1_rtype}, {rob_uop_19_lrs1_rtype}, {rob_uop_18_lrs1_rtype}, {rob_uop_17_lrs1_rtype}, {rob_uop_16_lrs1_rtype}, {rob_uop_15_lrs1_rtype}, {rob_uop_14_lrs1_rtype}, {rob_uop_13_lrs1_rtype}, {rob_uop_12_lrs1_rtype}, {rob_uop_11_lrs1_rtype}, {rob_uop_10_lrs1_rtype}, {rob_uop_9_lrs1_rtype}, {rob_uop_8_lrs1_rtype}, {rob_uop_7_lrs1_rtype}, {rob_uop_6_lrs1_rtype}, {rob_uop_5_lrs1_rtype}, {rob_uop_4_lrs1_rtype}, {rob_uop_3_lrs1_rtype}, {rob_uop_2_lrs1_rtype}, {rob_uop_1_lrs1_rtype}, {rob_uop_0_lrs1_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs1_rtype_0 = _GEN_81[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_82 = {{rob_uop_31_lrs2_rtype}, {rob_uop_30_lrs2_rtype}, {rob_uop_29_lrs2_rtype}, {rob_uop_28_lrs2_rtype}, {rob_uop_27_lrs2_rtype}, {rob_uop_26_lrs2_rtype}, {rob_uop_25_lrs2_rtype}, {rob_uop_24_lrs2_rtype}, {rob_uop_23_lrs2_rtype}, {rob_uop_22_lrs2_rtype}, {rob_uop_21_lrs2_rtype}, {rob_uop_20_lrs2_rtype}, {rob_uop_19_lrs2_rtype}, {rob_uop_18_lrs2_rtype}, {rob_uop_17_lrs2_rtype}, {rob_uop_16_lrs2_rtype}, {rob_uop_15_lrs2_rtype}, {rob_uop_14_lrs2_rtype}, {rob_uop_13_lrs2_rtype}, {rob_uop_12_lrs2_rtype}, {rob_uop_11_lrs2_rtype}, {rob_uop_10_lrs2_rtype}, {rob_uop_9_lrs2_rtype}, {rob_uop_8_lrs2_rtype}, {rob_uop_7_lrs2_rtype}, {rob_uop_6_lrs2_rtype}, {rob_uop_5_lrs2_rtype}, {rob_uop_4_lrs2_rtype}, {rob_uop_3_lrs2_rtype}, {rob_uop_2_lrs2_rtype}, {rob_uop_1_lrs2_rtype}, {rob_uop_0_lrs2_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_lrs2_rtype_0 = _GEN_82[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_83 = {{rob_uop_31_frs3_en}, {rob_uop_30_frs3_en}, {rob_uop_29_frs3_en}, {rob_uop_28_frs3_en}, {rob_uop_27_frs3_en}, {rob_uop_26_frs3_en}, {rob_uop_25_frs3_en}, {rob_uop_24_frs3_en}, {rob_uop_23_frs3_en}, {rob_uop_22_frs3_en}, {rob_uop_21_frs3_en}, {rob_uop_20_frs3_en}, {rob_uop_19_frs3_en}, {rob_uop_18_frs3_en}, {rob_uop_17_frs3_en}, {rob_uop_16_frs3_en}, {rob_uop_15_frs3_en}, {rob_uop_14_frs3_en}, {rob_uop_13_frs3_en}, {rob_uop_12_frs3_en}, {rob_uop_11_frs3_en}, {rob_uop_10_frs3_en}, {rob_uop_9_frs3_en}, {rob_uop_8_frs3_en}, {rob_uop_7_frs3_en}, {rob_uop_6_frs3_en}, {rob_uop_5_frs3_en}, {rob_uop_4_frs3_en}, {rob_uop_3_frs3_en}, {rob_uop_2_frs3_en}, {rob_uop_1_frs3_en}, {rob_uop_0_frs3_en}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_frs3_en_0 = _GEN_83[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_84 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fp_val_0 = _GEN_84[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_85 = {{rob_uop_31_fp_single}, {rob_uop_30_fp_single}, {rob_uop_29_fp_single}, {rob_uop_28_fp_single}, {rob_uop_27_fp_single}, {rob_uop_26_fp_single}, {rob_uop_25_fp_single}, {rob_uop_24_fp_single}, {rob_uop_23_fp_single}, {rob_uop_22_fp_single}, {rob_uop_21_fp_single}, {rob_uop_20_fp_single}, {rob_uop_19_fp_single}, {rob_uop_18_fp_single}, {rob_uop_17_fp_single}, {rob_uop_16_fp_single}, {rob_uop_15_fp_single}, {rob_uop_14_fp_single}, {rob_uop_13_fp_single}, {rob_uop_12_fp_single}, {rob_uop_11_fp_single}, {rob_uop_10_fp_single}, {rob_uop_9_fp_single}, {rob_uop_8_fp_single}, {rob_uop_7_fp_single}, {rob_uop_6_fp_single}, {rob_uop_5_fp_single}, {rob_uop_4_fp_single}, {rob_uop_3_fp_single}, {rob_uop_2_fp_single}, {rob_uop_1_fp_single}, {rob_uop_0_fp_single}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_fp_single_0 = _GEN_85[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_86 = {{rob_uop_31_xcpt_pf_if}, {rob_uop_30_xcpt_pf_if}, {rob_uop_29_xcpt_pf_if}, {rob_uop_28_xcpt_pf_if}, {rob_uop_27_xcpt_pf_if}, {rob_uop_26_xcpt_pf_if}, {rob_uop_25_xcpt_pf_if}, {rob_uop_24_xcpt_pf_if}, {rob_uop_23_xcpt_pf_if}, {rob_uop_22_xcpt_pf_if}, {rob_uop_21_xcpt_pf_if}, {rob_uop_20_xcpt_pf_if}, {rob_uop_19_xcpt_pf_if}, {rob_uop_18_xcpt_pf_if}, {rob_uop_17_xcpt_pf_if}, {rob_uop_16_xcpt_pf_if}, {rob_uop_15_xcpt_pf_if}, {rob_uop_14_xcpt_pf_if}, {rob_uop_13_xcpt_pf_if}, {rob_uop_12_xcpt_pf_if}, {rob_uop_11_xcpt_pf_if}, {rob_uop_10_xcpt_pf_if}, {rob_uop_9_xcpt_pf_if}, {rob_uop_8_xcpt_pf_if}, {rob_uop_7_xcpt_pf_if}, {rob_uop_6_xcpt_pf_if}, {rob_uop_5_xcpt_pf_if}, {rob_uop_4_xcpt_pf_if}, {rob_uop_3_xcpt_pf_if}, {rob_uop_2_xcpt_pf_if}, {rob_uop_1_xcpt_pf_if}, {rob_uop_0_xcpt_pf_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_pf_if_0 = _GEN_86[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_87 = {{rob_uop_31_xcpt_ae_if}, {rob_uop_30_xcpt_ae_if}, {rob_uop_29_xcpt_ae_if}, {rob_uop_28_xcpt_ae_if}, {rob_uop_27_xcpt_ae_if}, {rob_uop_26_xcpt_ae_if}, {rob_uop_25_xcpt_ae_if}, {rob_uop_24_xcpt_ae_if}, {rob_uop_23_xcpt_ae_if}, {rob_uop_22_xcpt_ae_if}, {rob_uop_21_xcpt_ae_if}, {rob_uop_20_xcpt_ae_if}, {rob_uop_19_xcpt_ae_if}, {rob_uop_18_xcpt_ae_if}, {rob_uop_17_xcpt_ae_if}, {rob_uop_16_xcpt_ae_if}, {rob_uop_15_xcpt_ae_if}, {rob_uop_14_xcpt_ae_if}, {rob_uop_13_xcpt_ae_if}, {rob_uop_12_xcpt_ae_if}, {rob_uop_11_xcpt_ae_if}, {rob_uop_10_xcpt_ae_if}, {rob_uop_9_xcpt_ae_if}, {rob_uop_8_xcpt_ae_if}, {rob_uop_7_xcpt_ae_if}, {rob_uop_6_xcpt_ae_if}, {rob_uop_5_xcpt_ae_if}, {rob_uop_4_xcpt_ae_if}, {rob_uop_3_xcpt_ae_if}, {rob_uop_2_xcpt_ae_if}, {rob_uop_1_xcpt_ae_if}, {rob_uop_0_xcpt_ae_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_ae_if_0 = _GEN_87[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_88 = {{rob_uop_31_xcpt_ma_if}, {rob_uop_30_xcpt_ma_if}, {rob_uop_29_xcpt_ma_if}, {rob_uop_28_xcpt_ma_if}, {rob_uop_27_xcpt_ma_if}, {rob_uop_26_xcpt_ma_if}, {rob_uop_25_xcpt_ma_if}, {rob_uop_24_xcpt_ma_if}, {rob_uop_23_xcpt_ma_if}, {rob_uop_22_xcpt_ma_if}, {rob_uop_21_xcpt_ma_if}, {rob_uop_20_xcpt_ma_if}, {rob_uop_19_xcpt_ma_if}, {rob_uop_18_xcpt_ma_if}, {rob_uop_17_xcpt_ma_if}, {rob_uop_16_xcpt_ma_if}, {rob_uop_15_xcpt_ma_if}, {rob_uop_14_xcpt_ma_if}, {rob_uop_13_xcpt_ma_if}, {rob_uop_12_xcpt_ma_if}, {rob_uop_11_xcpt_ma_if}, {rob_uop_10_xcpt_ma_if}, {rob_uop_9_xcpt_ma_if}, {rob_uop_8_xcpt_ma_if}, {rob_uop_7_xcpt_ma_if}, {rob_uop_6_xcpt_ma_if}, {rob_uop_5_xcpt_ma_if}, {rob_uop_4_xcpt_ma_if}, {rob_uop_3_xcpt_ma_if}, {rob_uop_2_xcpt_ma_if}, {rob_uop_1_xcpt_ma_if}, {rob_uop_0_xcpt_ma_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_xcpt_ma_if_0 = _GEN_88[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_89 = {{rob_uop_31_bp_debug_if}, {rob_uop_30_bp_debug_if}, {rob_uop_29_bp_debug_if}, {rob_uop_28_bp_debug_if}, {rob_uop_27_bp_debug_if}, {rob_uop_26_bp_debug_if}, {rob_uop_25_bp_debug_if}, {rob_uop_24_bp_debug_if}, {rob_uop_23_bp_debug_if}, {rob_uop_22_bp_debug_if}, {rob_uop_21_bp_debug_if}, {rob_uop_20_bp_debug_if}, {rob_uop_19_bp_debug_if}, {rob_uop_18_bp_debug_if}, {rob_uop_17_bp_debug_if}, {rob_uop_16_bp_debug_if}, {rob_uop_15_bp_debug_if}, {rob_uop_14_bp_debug_if}, {rob_uop_13_bp_debug_if}, {rob_uop_12_bp_debug_if}, {rob_uop_11_bp_debug_if}, {rob_uop_10_bp_debug_if}, {rob_uop_9_bp_debug_if}, {rob_uop_8_bp_debug_if}, {rob_uop_7_bp_debug_if}, {rob_uop_6_bp_debug_if}, {rob_uop_5_bp_debug_if}, {rob_uop_4_bp_debug_if}, {rob_uop_3_bp_debug_if}, {rob_uop_2_bp_debug_if}, {rob_uop_1_bp_debug_if}, {rob_uop_0_bp_debug_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bp_debug_if_0 = _GEN_89[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_90 = {{rob_uop_31_bp_xcpt_if}, {rob_uop_30_bp_xcpt_if}, {rob_uop_29_bp_xcpt_if}, {rob_uop_28_bp_xcpt_if}, {rob_uop_27_bp_xcpt_if}, {rob_uop_26_bp_xcpt_if}, {rob_uop_25_bp_xcpt_if}, {rob_uop_24_bp_xcpt_if}, {rob_uop_23_bp_xcpt_if}, {rob_uop_22_bp_xcpt_if}, {rob_uop_21_bp_xcpt_if}, {rob_uop_20_bp_xcpt_if}, {rob_uop_19_bp_xcpt_if}, {rob_uop_18_bp_xcpt_if}, {rob_uop_17_bp_xcpt_if}, {rob_uop_16_bp_xcpt_if}, {rob_uop_15_bp_xcpt_if}, {rob_uop_14_bp_xcpt_if}, {rob_uop_13_bp_xcpt_if}, {rob_uop_12_bp_xcpt_if}, {rob_uop_11_bp_xcpt_if}, {rob_uop_10_bp_xcpt_if}, {rob_uop_9_bp_xcpt_if}, {rob_uop_8_bp_xcpt_if}, {rob_uop_7_bp_xcpt_if}, {rob_uop_6_bp_xcpt_if}, {rob_uop_5_bp_xcpt_if}, {rob_uop_4_bp_xcpt_if}, {rob_uop_3_bp_xcpt_if}, {rob_uop_2_bp_xcpt_if}, {rob_uop_1_bp_xcpt_if}, {rob_uop_0_bp_xcpt_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_bp_xcpt_if_0 = _GEN_90[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_91 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}}; // @[rob.scala:311:28, :415:25]
wire [31:0][1:0] _GEN_92 = {{rob_uop_31_debug_tsrc}, {rob_uop_30_debug_tsrc}, {rob_uop_29_debug_tsrc}, {rob_uop_28_debug_tsrc}, {rob_uop_27_debug_tsrc}, {rob_uop_26_debug_tsrc}, {rob_uop_25_debug_tsrc}, {rob_uop_24_debug_tsrc}, {rob_uop_23_debug_tsrc}, {rob_uop_22_debug_tsrc}, {rob_uop_21_debug_tsrc}, {rob_uop_20_debug_tsrc}, {rob_uop_19_debug_tsrc}, {rob_uop_18_debug_tsrc}, {rob_uop_17_debug_tsrc}, {rob_uop_16_debug_tsrc}, {rob_uop_15_debug_tsrc}, {rob_uop_14_debug_tsrc}, {rob_uop_13_debug_tsrc}, {rob_uop_12_debug_tsrc}, {rob_uop_11_debug_tsrc}, {rob_uop_10_debug_tsrc}, {rob_uop_9_debug_tsrc}, {rob_uop_8_debug_tsrc}, {rob_uop_7_debug_tsrc}, {rob_uop_6_debug_tsrc}, {rob_uop_5_debug_tsrc}, {rob_uop_4_debug_tsrc}, {rob_uop_3_debug_tsrc}, {rob_uop_2_debug_tsrc}, {rob_uop_1_debug_tsrc}, {rob_uop_0_debug_tsrc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_0_debug_tsrc_0 = _GEN_92[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [6:0] _rob_tail_T_3 = {2'h0, io_brupdate_b2_uop_rob_idx_0[6:2]}; // @[rob.scala:211:7, :267:25]
wire _T_114 = io_brupdate_b2_mispredict_0 & ~(|(io_brupdate_b2_uop_rob_idx_0[1:0])) & io_brupdate_b2_uop_rob_idx_0[6:2] == com_idx; // @[rob.scala:211:7, :235:20, :267:25, :271:36, :305:53, :420:37, :421:57, :422:45]
assign io_commit_uops_0_debug_fsrc_0 = _T_114 ? 2'h3 : _GEN_91[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :423:36]
assign io_commit_uops_0_taken_0 = _T_114 ? io_brupdate_b2_taken_0 : _GEN_45[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :424:36]
wire _rbk_row_T_1 = ~full; // @[rob.scala:239:26, :429:47]
wire rbk_row = _rbk_row_T & _rbk_row_T_1; // @[rob.scala:429:{29,44,47}]
wire _io_commit_rbk_valids_0_T = rbk_row & _GEN_0[com_idx]; // @[rob.scala:235:20, :324:31, :429:44, :431:40]
assign _io_commit_rbk_valids_0_T_2 = _io_commit_rbk_valids_0_T; // @[rob.scala:431:{40,60}]
assign io_commit_rbk_valids_0_0 = _io_commit_rbk_valids_0_T_2; // @[rob.scala:211:7, :431:60]
wire [15:0] _rob_uop_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_0_br_mask_T_1 = rob_uop_0_br_mask & _rob_uop_0_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_1_br_mask_T_1 = rob_uop_1_br_mask & _rob_uop_1_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_2_br_mask_T_1 = rob_uop_2_br_mask & _rob_uop_2_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_3_br_mask_T_1 = rob_uop_3_br_mask & _rob_uop_3_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_4_br_mask_T_1 = rob_uop_4_br_mask & _rob_uop_4_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_5_br_mask_T_1 = rob_uop_5_br_mask & _rob_uop_5_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_6_br_mask_T_1 = rob_uop_6_br_mask & _rob_uop_6_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_7_br_mask_T_1 = rob_uop_7_br_mask & _rob_uop_7_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_8_br_mask_T_1 = rob_uop_8_br_mask & _rob_uop_8_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_9_br_mask_T_1 = rob_uop_9_br_mask & _rob_uop_9_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_10_br_mask_T_1 = rob_uop_10_br_mask & _rob_uop_10_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_11_br_mask_T_1 = rob_uop_11_br_mask & _rob_uop_11_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_12_br_mask_T_1 = rob_uop_12_br_mask & _rob_uop_12_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_13_br_mask_T_1 = rob_uop_13_br_mask & _rob_uop_13_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_14_br_mask_T_1 = rob_uop_14_br_mask & _rob_uop_14_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_15_br_mask_T_1 = rob_uop_15_br_mask & _rob_uop_15_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_16_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_16_br_mask_T_1 = rob_uop_16_br_mask & _rob_uop_16_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_17_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_17_br_mask_T_1 = rob_uop_17_br_mask & _rob_uop_17_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_18_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_18_br_mask_T_1 = rob_uop_18_br_mask & _rob_uop_18_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_19_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_19_br_mask_T_1 = rob_uop_19_br_mask & _rob_uop_19_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_20_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_20_br_mask_T_1 = rob_uop_20_br_mask & _rob_uop_20_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_21_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_21_br_mask_T_1 = rob_uop_21_br_mask & _rob_uop_21_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_22_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_22_br_mask_T_1 = rob_uop_22_br_mask & _rob_uop_22_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_23_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_23_br_mask_T_1 = rob_uop_23_br_mask & _rob_uop_23_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_24_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_24_br_mask_T_1 = rob_uop_24_br_mask & _rob_uop_24_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_25_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_25_br_mask_T_1 = rob_uop_25_br_mask & _rob_uop_25_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_26_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_26_br_mask_T_1 = rob_uop_26_br_mask & _rob_uop_26_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_27_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_27_br_mask_T_1 = rob_uop_27_br_mask & _rob_uop_27_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_28_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_28_br_mask_T_1 = rob_uop_28_br_mask & _rob_uop_28_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_29_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_29_br_mask_T_1 = rob_uop_29_br_mask & _rob_uop_29_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_30_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_30_br_mask_T_1 = rob_uop_30_br_mask & _rob_uop_30_br_mask_T; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_31_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_31_br_mask_T_1 = rob_uop_31_br_mask & _rob_uop_31_br_mask_T; // @[util.scala:89:{21,23}]
wire [31:0][4:0] _GEN_93 = {{rob_fflags_0_31}, {rob_fflags_0_30}, {rob_fflags_0_29}, {rob_fflags_0_28}, {rob_fflags_0_27}, {rob_fflags_0_26}, {rob_fflags_0_25}, {rob_fflags_0_24}, {rob_fflags_0_23}, {rob_fflags_0_22}, {rob_fflags_0_21}, {rob_fflags_0_20}, {rob_fflags_0_19}, {rob_fflags_0_18}, {rob_fflags_0_17}, {rob_fflags_0_16}, {rob_fflags_0_15}, {rob_fflags_0_14}, {rob_fflags_0_13}, {rob_fflags_0_12}, {rob_fflags_0_11}, {rob_fflags_0_10}, {rob_fflags_0_9}, {rob_fflags_0_8}, {rob_fflags_0_7}, {rob_fflags_0_6}, {rob_fflags_0_5}, {rob_fflags_0_4}, {rob_fflags_0_3}, {rob_fflags_0_2}, {rob_fflags_0_1}, {rob_fflags_0_0}}; // @[rob.scala:302:46, :487:26]
assign rob_head_fflags_0 = _GEN_93[rob_head]; // @[rob.scala:223:29, :251:33, :487:26]
assign rob_head_uses_ldq_0 = _GEN_69[rob_head]; // @[rob.scala:223:29, :250:33, :415:25, :488:26]
assign rob_head_uses_stq_0 = _GEN_70[rob_head]; // @[rob.scala:223:29, :249:33, :415:25, :488:26]
wire _rob_unsafe_masked_0_T = rob_unsafe_0 | rob_exception_0; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_0_T_1 = rob_val_0 & _rob_unsafe_masked_0_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_0 = _rob_unsafe_masked_0_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_4_T = rob_unsafe_1 | rob_exception_1; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_4_T_1 = rob_val_1 & _rob_unsafe_masked_4_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_4 = _rob_unsafe_masked_4_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_8_T = rob_unsafe_2 | rob_exception_2; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_8_T_1 = rob_val_2 & _rob_unsafe_masked_8_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_8 = _rob_unsafe_masked_8_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_12_T = rob_unsafe_3 | rob_exception_3; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_12_T_1 = rob_val_3 & _rob_unsafe_masked_12_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_12 = _rob_unsafe_masked_12_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_16_T = rob_unsafe_4 | rob_exception_4; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_16_T_1 = rob_val_4 & _rob_unsafe_masked_16_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_16 = _rob_unsafe_masked_16_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_20_T = rob_unsafe_5 | rob_exception_5; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_20_T_1 = rob_val_5 & _rob_unsafe_masked_20_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_20 = _rob_unsafe_masked_20_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_24_T = rob_unsafe_6 | rob_exception_6; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_24_T_1 = rob_val_6 & _rob_unsafe_masked_24_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_24 = _rob_unsafe_masked_24_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_28_T = rob_unsafe_7 | rob_exception_7; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_28_T_1 = rob_val_7 & _rob_unsafe_masked_28_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_28 = _rob_unsafe_masked_28_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_32_T = rob_unsafe_8 | rob_exception_8; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_32_T_1 = rob_val_8 & _rob_unsafe_masked_32_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_32 = _rob_unsafe_masked_32_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_36_T = rob_unsafe_9 | rob_exception_9; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_36_T_1 = rob_val_9 & _rob_unsafe_masked_36_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_36 = _rob_unsafe_masked_36_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_40_T = rob_unsafe_10 | rob_exception_10; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_40_T_1 = rob_val_10 & _rob_unsafe_masked_40_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_40 = _rob_unsafe_masked_40_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_44_T = rob_unsafe_11 | rob_exception_11; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_44_T_1 = rob_val_11 & _rob_unsafe_masked_44_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_44 = _rob_unsafe_masked_44_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_48_T = rob_unsafe_12 | rob_exception_12; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_48_T_1 = rob_val_12 & _rob_unsafe_masked_48_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_48 = _rob_unsafe_masked_48_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_52_T = rob_unsafe_13 | rob_exception_13; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_52_T_1 = rob_val_13 & _rob_unsafe_masked_52_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_52 = _rob_unsafe_masked_52_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_56_T = rob_unsafe_14 | rob_exception_14; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_56_T_1 = rob_val_14 & _rob_unsafe_masked_56_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_56 = _rob_unsafe_masked_56_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_60_T = rob_unsafe_15 | rob_exception_15; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_60_T_1 = rob_val_15 & _rob_unsafe_masked_60_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_60 = _rob_unsafe_masked_60_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_64_T = rob_unsafe_16 | rob_exception_16; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_64_T_1 = rob_val_16 & _rob_unsafe_masked_64_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_64 = _rob_unsafe_masked_64_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_68_T = rob_unsafe_17 | rob_exception_17; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_68_T_1 = rob_val_17 & _rob_unsafe_masked_68_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_68 = _rob_unsafe_masked_68_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_72_T = rob_unsafe_18 | rob_exception_18; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_72_T_1 = rob_val_18 & _rob_unsafe_masked_72_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_72 = _rob_unsafe_masked_72_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_76_T = rob_unsafe_19 | rob_exception_19; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_76_T_1 = rob_val_19 & _rob_unsafe_masked_76_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_76 = _rob_unsafe_masked_76_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_80_T = rob_unsafe_20 | rob_exception_20; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_80_T_1 = rob_val_20 & _rob_unsafe_masked_80_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_80 = _rob_unsafe_masked_80_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_84_T = rob_unsafe_21 | rob_exception_21; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_84_T_1 = rob_val_21 & _rob_unsafe_masked_84_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_84 = _rob_unsafe_masked_84_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_88_T = rob_unsafe_22 | rob_exception_22; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_88_T_1 = rob_val_22 & _rob_unsafe_masked_88_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_88 = _rob_unsafe_masked_88_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_92_T = rob_unsafe_23 | rob_exception_23; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_92_T_1 = rob_val_23 & _rob_unsafe_masked_92_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_92 = _rob_unsafe_masked_92_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_96_T = rob_unsafe_24 | rob_exception_24; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_96_T_1 = rob_val_24 & _rob_unsafe_masked_96_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_96 = _rob_unsafe_masked_96_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_100_T = rob_unsafe_25 | rob_exception_25; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_100_T_1 = rob_val_25 & _rob_unsafe_masked_100_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_100 = _rob_unsafe_masked_100_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_104_T = rob_unsafe_26 | rob_exception_26; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_104_T_1 = rob_val_26 & _rob_unsafe_masked_104_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_104 = _rob_unsafe_masked_104_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_108_T = rob_unsafe_27 | rob_exception_27; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_108_T_1 = rob_val_27 & _rob_unsafe_masked_108_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_108 = _rob_unsafe_masked_108_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_112_T = rob_unsafe_28 | rob_exception_28; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_112_T_1 = rob_val_28 & _rob_unsafe_masked_112_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_112 = _rob_unsafe_masked_112_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_116_T = rob_unsafe_29 | rob_exception_29; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_116_T_1 = rob_val_29 & _rob_unsafe_masked_116_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_116 = _rob_unsafe_masked_116_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_120_T = rob_unsafe_30 | rob_exception_30; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_120_T_1 = rob_val_30 & _rob_unsafe_masked_120_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_120 = _rob_unsafe_masked_120_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_124_T = rob_unsafe_31 | rob_exception_31; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_124_T_1 = rob_val_31 & _rob_unsafe_masked_124_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_124 = _rob_unsafe_masked_124_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_pnr_unsafe_0_T = _GEN_12[rob_pnr] | _GEN_14[rob_pnr]; // @[rob.scala:231:29, :394:15, :402:49, :497:67]
assign _rob_pnr_unsafe_0_T_1 = _GEN_0[rob_pnr] & _rob_pnr_unsafe_0_T; // @[rob.scala:231:29, :324:31, :497:{43,67}]
assign rob_pnr_unsafe_0 = _rob_pnr_unsafe_0_T_1; // @[rob.scala:246:33, :497:43]
wire [4:0] _temp_uop_T_1 = _temp_uop_T[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_3 = _temp_uop_T_2[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_5 = _temp_uop_T_4[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_7 = _temp_uop_T_6[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_9 = _temp_uop_T_8[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_11 = _temp_uop_T_10[4:0]; // @[rob.scala:267:25]
reg rob_val_1_0; // @[rob.scala:308:32]
reg rob_val_1_1; // @[rob.scala:308:32]
reg rob_val_1_2; // @[rob.scala:308:32]
reg rob_val_1_3; // @[rob.scala:308:32]
reg rob_val_1_4; // @[rob.scala:308:32]
reg rob_val_1_5; // @[rob.scala:308:32]
reg rob_val_1_6; // @[rob.scala:308:32]
reg rob_val_1_7; // @[rob.scala:308:32]
reg rob_val_1_8; // @[rob.scala:308:32]
reg rob_val_1_9; // @[rob.scala:308:32]
reg rob_val_1_10; // @[rob.scala:308:32]
reg rob_val_1_11; // @[rob.scala:308:32]
reg rob_val_1_12; // @[rob.scala:308:32]
reg rob_val_1_13; // @[rob.scala:308:32]
reg rob_val_1_14; // @[rob.scala:308:32]
reg rob_val_1_15; // @[rob.scala:308:32]
reg rob_val_1_16; // @[rob.scala:308:32]
reg rob_val_1_17; // @[rob.scala:308:32]
reg rob_val_1_18; // @[rob.scala:308:32]
reg rob_val_1_19; // @[rob.scala:308:32]
reg rob_val_1_20; // @[rob.scala:308:32]
reg rob_val_1_21; // @[rob.scala:308:32]
reg rob_val_1_22; // @[rob.scala:308:32]
reg rob_val_1_23; // @[rob.scala:308:32]
reg rob_val_1_24; // @[rob.scala:308:32]
reg rob_val_1_25; // @[rob.scala:308:32]
reg rob_val_1_26; // @[rob.scala:308:32]
reg rob_val_1_27; // @[rob.scala:308:32]
reg rob_val_1_28; // @[rob.scala:308:32]
reg rob_val_1_29; // @[rob.scala:308:32]
reg rob_val_1_30; // @[rob.scala:308:32]
reg rob_val_1_31; // @[rob.scala:308:32]
reg rob_bsy_1_0; // @[rob.scala:309:28]
reg rob_bsy_1_1; // @[rob.scala:309:28]
reg rob_bsy_1_2; // @[rob.scala:309:28]
reg rob_bsy_1_3; // @[rob.scala:309:28]
reg rob_bsy_1_4; // @[rob.scala:309:28]
reg rob_bsy_1_5; // @[rob.scala:309:28]
reg rob_bsy_1_6; // @[rob.scala:309:28]
reg rob_bsy_1_7; // @[rob.scala:309:28]
reg rob_bsy_1_8; // @[rob.scala:309:28]
reg rob_bsy_1_9; // @[rob.scala:309:28]
reg rob_bsy_1_10; // @[rob.scala:309:28]
reg rob_bsy_1_11; // @[rob.scala:309:28]
reg rob_bsy_1_12; // @[rob.scala:309:28]
reg rob_bsy_1_13; // @[rob.scala:309:28]
reg rob_bsy_1_14; // @[rob.scala:309:28]
reg rob_bsy_1_15; // @[rob.scala:309:28]
reg rob_bsy_1_16; // @[rob.scala:309:28]
reg rob_bsy_1_17; // @[rob.scala:309:28]
reg rob_bsy_1_18; // @[rob.scala:309:28]
reg rob_bsy_1_19; // @[rob.scala:309:28]
reg rob_bsy_1_20; // @[rob.scala:309:28]
reg rob_bsy_1_21; // @[rob.scala:309:28]
reg rob_bsy_1_22; // @[rob.scala:309:28]
reg rob_bsy_1_23; // @[rob.scala:309:28]
reg rob_bsy_1_24; // @[rob.scala:309:28]
reg rob_bsy_1_25; // @[rob.scala:309:28]
reg rob_bsy_1_26; // @[rob.scala:309:28]
reg rob_bsy_1_27; // @[rob.scala:309:28]
reg rob_bsy_1_28; // @[rob.scala:309:28]
reg rob_bsy_1_29; // @[rob.scala:309:28]
reg rob_bsy_1_30; // @[rob.scala:309:28]
reg rob_bsy_1_31; // @[rob.scala:309:28]
reg rob_unsafe_1_0; // @[rob.scala:310:28]
reg rob_unsafe_1_1; // @[rob.scala:310:28]
reg rob_unsafe_1_2; // @[rob.scala:310:28]
reg rob_unsafe_1_3; // @[rob.scala:310:28]
reg rob_unsafe_1_4; // @[rob.scala:310:28]
reg rob_unsafe_1_5; // @[rob.scala:310:28]
reg rob_unsafe_1_6; // @[rob.scala:310:28]
reg rob_unsafe_1_7; // @[rob.scala:310:28]
reg rob_unsafe_1_8; // @[rob.scala:310:28]
reg rob_unsafe_1_9; // @[rob.scala:310:28]
reg rob_unsafe_1_10; // @[rob.scala:310:28]
reg rob_unsafe_1_11; // @[rob.scala:310:28]
reg rob_unsafe_1_12; // @[rob.scala:310:28]
reg rob_unsafe_1_13; // @[rob.scala:310:28]
reg rob_unsafe_1_14; // @[rob.scala:310:28]
reg rob_unsafe_1_15; // @[rob.scala:310:28]
reg rob_unsafe_1_16; // @[rob.scala:310:28]
reg rob_unsafe_1_17; // @[rob.scala:310:28]
reg rob_unsafe_1_18; // @[rob.scala:310:28]
reg rob_unsafe_1_19; // @[rob.scala:310:28]
reg rob_unsafe_1_20; // @[rob.scala:310:28]
reg rob_unsafe_1_21; // @[rob.scala:310:28]
reg rob_unsafe_1_22; // @[rob.scala:310:28]
reg rob_unsafe_1_23; // @[rob.scala:310:28]
reg rob_unsafe_1_24; // @[rob.scala:310:28]
reg rob_unsafe_1_25; // @[rob.scala:310:28]
reg rob_unsafe_1_26; // @[rob.scala:310:28]
reg rob_unsafe_1_27; // @[rob.scala:310:28]
reg rob_unsafe_1_28; // @[rob.scala:310:28]
reg rob_unsafe_1_29; // @[rob.scala:310:28]
reg rob_unsafe_1_30; // @[rob.scala:310:28]
reg rob_unsafe_1_31; // @[rob.scala:310:28]
reg [6:0] rob_uop_1_0_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_0_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_0_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_0_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_0_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_0_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_0_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_0_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_0_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_0_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_0_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_0_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_0_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_0_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_0_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_0_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_0_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_0_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_0_is_br; // @[rob.scala:311:28]
reg rob_uop_1_0_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_0_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_0_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_0_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_0_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_0_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_0_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_0_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_0_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_0_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_0_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_0_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_0_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_prs3; // @[rob.scala:311:28]
reg rob_uop_1_0_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_0_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_0_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_0_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_0_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_0_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_0_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_0_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_0_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_0_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_0_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_0_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_0_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_0_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_0_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_0_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_0_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_0_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_0_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_0_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_0_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_0_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_0_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_0_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_0_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_0_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_0_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_0_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_0_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_0_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_0_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_0_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_1_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_1_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_1_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_1_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_1_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_1_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_1_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_1_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_1_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_1_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_1_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_1_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_1_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_1_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_1_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_1_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_1_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_1_is_br; // @[rob.scala:311:28]
reg rob_uop_1_1_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_1_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_1_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_1_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_1_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_1_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_1_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_1_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_1_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_1_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_1_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_1_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_1_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_prs3; // @[rob.scala:311:28]
reg rob_uop_1_1_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_1_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_1_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_1_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_1_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_1_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_1_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_1_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_1_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_1_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_1_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_1_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_1_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_1_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_1_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_1_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_1_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_1_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_1_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_1_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_1_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_1_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_1_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_1_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_1_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_1_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_1_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_1_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_1_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_1_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_1_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_1_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_2_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_2_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_2_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_2_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_2_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_2_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_2_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_2_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_2_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_2_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_2_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_2_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_2_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_2_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_2_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_2_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_2_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_2_is_br; // @[rob.scala:311:28]
reg rob_uop_1_2_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_2_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_2_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_2_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_2_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_2_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_2_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_2_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_2_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_2_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_2_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_2_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_2_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_prs3; // @[rob.scala:311:28]
reg rob_uop_1_2_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_2_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_2_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_2_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_2_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_2_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_2_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_2_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_2_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_2_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_2_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_2_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_2_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_2_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_2_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_2_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_2_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_2_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_2_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_2_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_2_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_2_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_2_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_2_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_2_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_2_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_2_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_2_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_2_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_2_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_2_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_2_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_3_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_3_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_3_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_3_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_3_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_3_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_3_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_3_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_3_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_3_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_3_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_3_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_3_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_3_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_3_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_3_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_3_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_3_is_br; // @[rob.scala:311:28]
reg rob_uop_1_3_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_3_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_3_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_3_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_3_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_3_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_3_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_3_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_3_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_3_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_3_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_3_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_3_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_prs3; // @[rob.scala:311:28]
reg rob_uop_1_3_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_3_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_3_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_3_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_3_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_3_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_3_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_3_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_3_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_3_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_3_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_3_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_3_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_3_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_3_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_3_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_3_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_3_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_3_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_3_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_3_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_3_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_3_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_3_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_3_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_3_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_3_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_3_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_3_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_3_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_3_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_3_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_4_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_4_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_4_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_4_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_4_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_4_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_4_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_4_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_4_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_4_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_4_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_4_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_4_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_4_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_4_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_4_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_4_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_4_is_br; // @[rob.scala:311:28]
reg rob_uop_1_4_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_4_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_4_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_4_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_4_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_4_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_4_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_4_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_4_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_4_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_4_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_4_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_4_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_prs3; // @[rob.scala:311:28]
reg rob_uop_1_4_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_4_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_4_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_4_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_4_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_4_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_4_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_4_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_4_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_4_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_4_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_4_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_4_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_4_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_4_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_4_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_4_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_4_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_4_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_4_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_4_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_4_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_4_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_4_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_4_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_4_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_4_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_4_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_4_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_4_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_4_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_4_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_5_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_5_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_5_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_5_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_5_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_5_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_5_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_5_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_5_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_5_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_5_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_5_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_5_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_5_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_5_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_5_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_5_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_5_is_br; // @[rob.scala:311:28]
reg rob_uop_1_5_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_5_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_5_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_5_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_5_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_5_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_5_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_5_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_5_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_5_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_5_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_5_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_5_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_prs3; // @[rob.scala:311:28]
reg rob_uop_1_5_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_5_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_5_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_5_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_5_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_5_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_5_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_5_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_5_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_5_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_5_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_5_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_5_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_5_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_5_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_5_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_5_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_5_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_5_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_5_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_5_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_5_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_5_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_5_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_5_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_5_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_5_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_5_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_5_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_5_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_5_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_5_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_6_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_6_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_6_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_6_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_6_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_6_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_6_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_6_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_6_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_6_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_6_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_6_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_6_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_6_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_6_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_6_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_6_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_6_is_br; // @[rob.scala:311:28]
reg rob_uop_1_6_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_6_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_6_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_6_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_6_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_6_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_6_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_6_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_6_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_6_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_6_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_6_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_6_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_prs3; // @[rob.scala:311:28]
reg rob_uop_1_6_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_6_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_6_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_6_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_6_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_6_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_6_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_6_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_6_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_6_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_6_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_6_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_6_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_6_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_6_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_6_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_6_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_6_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_6_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_6_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_6_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_6_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_6_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_6_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_6_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_6_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_6_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_6_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_6_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_6_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_6_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_6_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_7_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_7_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_7_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_7_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_7_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_7_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_7_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_7_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_7_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_7_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_7_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_7_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_7_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_7_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_7_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_7_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_7_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_7_is_br; // @[rob.scala:311:28]
reg rob_uop_1_7_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_7_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_7_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_7_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_7_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_7_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_7_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_7_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_7_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_7_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_7_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_7_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_7_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_prs3; // @[rob.scala:311:28]
reg rob_uop_1_7_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_7_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_7_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_7_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_7_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_7_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_7_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_7_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_7_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_7_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_7_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_7_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_7_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_7_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_7_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_7_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_7_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_7_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_7_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_7_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_7_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_7_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_7_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_7_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_7_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_7_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_7_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_7_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_7_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_7_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_7_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_7_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_8_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_8_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_8_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_8_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_8_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_8_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_8_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_8_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_8_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_8_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_8_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_8_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_8_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_8_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_8_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_8_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_8_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_8_is_br; // @[rob.scala:311:28]
reg rob_uop_1_8_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_8_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_8_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_8_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_8_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_8_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_8_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_8_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_8_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_8_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_8_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_8_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_8_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_prs3; // @[rob.scala:311:28]
reg rob_uop_1_8_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_8_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_8_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_8_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_8_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_8_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_8_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_8_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_8_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_8_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_8_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_8_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_8_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_8_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_8_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_8_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_8_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_8_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_8_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_8_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_8_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_8_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_8_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_8_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_8_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_8_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_8_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_8_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_8_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_8_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_8_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_8_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_9_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_9_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_9_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_9_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_9_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_9_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_9_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_9_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_9_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_9_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_9_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_9_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_9_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_9_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_9_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_9_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_9_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_9_is_br; // @[rob.scala:311:28]
reg rob_uop_1_9_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_9_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_9_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_9_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_9_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_9_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_9_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_9_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_9_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_9_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_9_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_9_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_9_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_prs3; // @[rob.scala:311:28]
reg rob_uop_1_9_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_9_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_9_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_9_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_9_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_9_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_9_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_9_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_9_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_9_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_9_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_9_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_9_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_9_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_9_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_9_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_9_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_9_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_9_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_9_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_9_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_9_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_9_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_9_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_9_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_9_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_9_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_9_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_9_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_9_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_9_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_9_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_10_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_10_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_10_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_10_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_10_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_10_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_10_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_10_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_10_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_10_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_10_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_10_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_10_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_10_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_10_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_10_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_10_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_10_is_br; // @[rob.scala:311:28]
reg rob_uop_1_10_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_10_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_10_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_10_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_10_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_10_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_10_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_10_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_10_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_10_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_10_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_10_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_10_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_prs3; // @[rob.scala:311:28]
reg rob_uop_1_10_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_10_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_10_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_10_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_10_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_10_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_10_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_10_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_10_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_10_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_10_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_10_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_10_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_10_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_10_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_10_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_10_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_10_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_10_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_10_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_10_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_10_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_10_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_10_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_10_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_10_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_10_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_10_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_10_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_10_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_10_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_10_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_11_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_11_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_11_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_11_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_11_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_11_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_11_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_11_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_11_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_11_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_11_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_11_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_11_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_11_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_11_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_11_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_11_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_11_is_br; // @[rob.scala:311:28]
reg rob_uop_1_11_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_11_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_11_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_11_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_11_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_11_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_11_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_11_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_11_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_11_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_11_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_11_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_11_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_prs3; // @[rob.scala:311:28]
reg rob_uop_1_11_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_11_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_11_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_11_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_11_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_11_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_11_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_11_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_11_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_11_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_11_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_11_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_11_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_11_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_11_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_11_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_11_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_11_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_11_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_11_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_11_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_11_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_11_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_11_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_11_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_11_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_11_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_11_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_11_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_11_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_11_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_11_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_12_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_12_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_12_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_12_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_12_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_12_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_12_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_12_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_12_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_12_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_12_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_12_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_12_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_12_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_12_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_12_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_12_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_12_is_br; // @[rob.scala:311:28]
reg rob_uop_1_12_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_12_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_12_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_12_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_12_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_12_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_12_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_12_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_12_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_12_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_12_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_12_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_12_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_prs3; // @[rob.scala:311:28]
reg rob_uop_1_12_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_12_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_12_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_12_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_12_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_12_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_12_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_12_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_12_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_12_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_12_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_12_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_12_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_12_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_12_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_12_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_12_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_12_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_12_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_12_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_12_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_12_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_12_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_12_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_12_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_12_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_12_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_12_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_12_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_12_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_12_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_12_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_13_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_13_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_13_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_13_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_13_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_13_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_13_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_13_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_13_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_13_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_13_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_13_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_13_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_13_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_13_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_13_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_13_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_13_is_br; // @[rob.scala:311:28]
reg rob_uop_1_13_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_13_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_13_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_13_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_13_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_13_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_13_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_13_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_13_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_13_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_13_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_13_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_13_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_prs3; // @[rob.scala:311:28]
reg rob_uop_1_13_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_13_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_13_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_13_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_13_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_13_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_13_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_13_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_13_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_13_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_13_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_13_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_13_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_13_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_13_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_13_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_13_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_13_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_13_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_13_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_13_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_13_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_13_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_13_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_13_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_13_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_13_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_13_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_13_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_13_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_13_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_13_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_14_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_14_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_14_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_14_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_14_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_14_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_14_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_14_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_14_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_14_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_14_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_14_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_14_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_14_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_14_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_14_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_14_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_14_is_br; // @[rob.scala:311:28]
reg rob_uop_1_14_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_14_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_14_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_14_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_14_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_14_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_14_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_14_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_14_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_14_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_14_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_14_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_14_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_prs3; // @[rob.scala:311:28]
reg rob_uop_1_14_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_14_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_14_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_14_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_14_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_14_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_14_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_14_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_14_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_14_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_14_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_14_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_14_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_14_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_14_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_14_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_14_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_14_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_14_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_14_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_14_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_14_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_14_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_14_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_14_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_14_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_14_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_14_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_14_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_14_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_14_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_14_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_15_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_15_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_15_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_15_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_15_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_15_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_15_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_15_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_15_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_15_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_15_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_15_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_15_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_15_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_15_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_15_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_15_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_15_is_br; // @[rob.scala:311:28]
reg rob_uop_1_15_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_15_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_15_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_15_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_15_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_15_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_15_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_15_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_15_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_15_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_15_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_15_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_15_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_prs3; // @[rob.scala:311:28]
reg rob_uop_1_15_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_15_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_15_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_15_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_15_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_15_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_15_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_15_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_15_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_15_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_15_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_15_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_15_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_15_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_15_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_15_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_15_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_15_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_15_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_15_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_15_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_15_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_15_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_15_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_15_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_15_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_15_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_15_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_15_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_15_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_15_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_15_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_16_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_16_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_16_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_16_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_16_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_16_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_16_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_16_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_16_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_16_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_16_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_16_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_16_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_16_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_16_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_16_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_16_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_16_is_br; // @[rob.scala:311:28]
reg rob_uop_1_16_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_16_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_16_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_16_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_16_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_16_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_16_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_16_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_16_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_16_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_16_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_16_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_16_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_prs3; // @[rob.scala:311:28]
reg rob_uop_1_16_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_16_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_16_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_16_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_16_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_16_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_16_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_16_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_16_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_16_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_16_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_16_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_16_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_16_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_16_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_16_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_16_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_16_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_16_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_16_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_16_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_16_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_16_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_16_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_16_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_16_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_16_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_16_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_16_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_16_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_16_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_16_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_17_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_17_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_17_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_17_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_17_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_17_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_17_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_17_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_17_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_17_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_17_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_17_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_17_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_17_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_17_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_17_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_17_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_17_is_br; // @[rob.scala:311:28]
reg rob_uop_1_17_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_17_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_17_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_17_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_17_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_17_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_17_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_17_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_17_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_17_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_17_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_17_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_17_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_prs3; // @[rob.scala:311:28]
reg rob_uop_1_17_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_17_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_17_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_17_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_17_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_17_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_17_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_17_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_17_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_17_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_17_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_17_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_17_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_17_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_17_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_17_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_17_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_17_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_17_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_17_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_17_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_17_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_17_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_17_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_17_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_17_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_17_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_17_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_17_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_17_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_17_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_17_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_18_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_18_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_18_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_18_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_18_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_18_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_18_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_18_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_18_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_18_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_18_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_18_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_18_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_18_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_18_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_18_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_18_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_18_is_br; // @[rob.scala:311:28]
reg rob_uop_1_18_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_18_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_18_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_18_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_18_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_18_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_18_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_18_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_18_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_18_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_18_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_18_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_18_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_prs3; // @[rob.scala:311:28]
reg rob_uop_1_18_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_18_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_18_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_18_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_18_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_18_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_18_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_18_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_18_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_18_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_18_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_18_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_18_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_18_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_18_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_18_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_18_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_18_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_18_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_18_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_18_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_18_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_18_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_18_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_18_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_18_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_18_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_18_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_18_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_18_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_18_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_18_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_19_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_19_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_19_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_19_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_19_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_19_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_19_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_19_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_19_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_19_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_19_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_19_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_19_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_19_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_19_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_19_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_19_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_19_is_br; // @[rob.scala:311:28]
reg rob_uop_1_19_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_19_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_19_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_19_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_19_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_19_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_19_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_19_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_19_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_19_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_19_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_19_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_19_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_prs3; // @[rob.scala:311:28]
reg rob_uop_1_19_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_19_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_19_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_19_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_19_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_19_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_19_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_19_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_19_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_19_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_19_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_19_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_19_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_19_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_19_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_19_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_19_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_19_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_19_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_19_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_19_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_19_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_19_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_19_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_19_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_19_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_19_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_19_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_19_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_19_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_19_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_19_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_20_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_20_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_20_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_20_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_20_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_20_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_20_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_20_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_20_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_20_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_20_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_20_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_20_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_20_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_20_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_20_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_20_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_20_is_br; // @[rob.scala:311:28]
reg rob_uop_1_20_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_20_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_20_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_20_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_20_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_20_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_20_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_20_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_20_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_20_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_20_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_20_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_20_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_prs3; // @[rob.scala:311:28]
reg rob_uop_1_20_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_20_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_20_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_20_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_20_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_20_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_20_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_20_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_20_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_20_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_20_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_20_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_20_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_20_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_20_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_20_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_20_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_20_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_20_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_20_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_20_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_20_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_20_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_20_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_20_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_20_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_20_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_20_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_20_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_20_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_20_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_20_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_21_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_21_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_21_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_21_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_21_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_21_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_21_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_21_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_21_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_21_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_21_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_21_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_21_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_21_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_21_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_21_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_21_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_21_is_br; // @[rob.scala:311:28]
reg rob_uop_1_21_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_21_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_21_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_21_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_21_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_21_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_21_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_21_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_21_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_21_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_21_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_21_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_21_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_prs3; // @[rob.scala:311:28]
reg rob_uop_1_21_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_21_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_21_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_21_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_21_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_21_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_21_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_21_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_21_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_21_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_21_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_21_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_21_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_21_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_21_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_21_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_21_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_21_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_21_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_21_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_21_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_21_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_21_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_21_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_21_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_21_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_21_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_21_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_21_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_21_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_21_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_21_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_22_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_22_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_22_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_22_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_22_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_22_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_22_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_22_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_22_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_22_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_22_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_22_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_22_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_22_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_22_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_22_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_22_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_22_is_br; // @[rob.scala:311:28]
reg rob_uop_1_22_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_22_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_22_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_22_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_22_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_22_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_22_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_22_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_22_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_22_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_22_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_22_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_22_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_prs3; // @[rob.scala:311:28]
reg rob_uop_1_22_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_22_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_22_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_22_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_22_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_22_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_22_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_22_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_22_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_22_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_22_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_22_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_22_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_22_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_22_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_22_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_22_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_22_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_22_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_22_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_22_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_22_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_22_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_22_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_22_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_22_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_22_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_22_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_22_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_22_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_22_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_22_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_23_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_23_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_23_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_23_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_23_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_23_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_23_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_23_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_23_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_23_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_23_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_23_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_23_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_23_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_23_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_23_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_23_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_23_is_br; // @[rob.scala:311:28]
reg rob_uop_1_23_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_23_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_23_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_23_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_23_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_23_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_23_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_23_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_23_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_23_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_23_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_23_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_23_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_prs3; // @[rob.scala:311:28]
reg rob_uop_1_23_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_23_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_23_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_23_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_23_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_23_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_23_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_23_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_23_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_23_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_23_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_23_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_23_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_23_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_23_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_23_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_23_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_23_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_23_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_23_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_23_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_23_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_23_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_23_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_23_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_23_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_23_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_23_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_23_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_23_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_23_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_23_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_24_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_24_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_24_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_24_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_24_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_24_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_24_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_24_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_24_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_24_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_24_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_24_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_24_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_24_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_24_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_24_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_24_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_24_is_br; // @[rob.scala:311:28]
reg rob_uop_1_24_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_24_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_24_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_24_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_24_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_24_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_24_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_24_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_24_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_24_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_24_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_24_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_24_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_prs3; // @[rob.scala:311:28]
reg rob_uop_1_24_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_24_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_24_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_24_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_24_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_24_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_24_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_24_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_24_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_24_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_24_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_24_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_24_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_24_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_24_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_24_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_24_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_24_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_24_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_24_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_24_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_24_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_24_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_24_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_24_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_24_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_24_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_24_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_24_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_24_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_24_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_24_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_25_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_25_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_25_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_25_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_25_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_25_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_25_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_25_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_25_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_25_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_25_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_25_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_25_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_25_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_25_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_25_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_25_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_25_is_br; // @[rob.scala:311:28]
reg rob_uop_1_25_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_25_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_25_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_25_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_25_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_25_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_25_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_25_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_25_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_25_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_25_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_25_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_25_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_prs3; // @[rob.scala:311:28]
reg rob_uop_1_25_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_25_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_25_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_25_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_25_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_25_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_25_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_25_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_25_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_25_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_25_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_25_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_25_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_25_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_25_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_25_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_25_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_25_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_25_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_25_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_25_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_25_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_25_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_25_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_25_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_25_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_25_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_25_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_25_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_25_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_25_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_25_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_26_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_26_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_26_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_26_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_26_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_26_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_26_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_26_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_26_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_26_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_26_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_26_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_26_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_26_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_26_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_26_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_26_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_26_is_br; // @[rob.scala:311:28]
reg rob_uop_1_26_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_26_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_26_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_26_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_26_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_26_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_26_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_26_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_26_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_26_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_26_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_26_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_26_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_prs3; // @[rob.scala:311:28]
reg rob_uop_1_26_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_26_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_26_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_26_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_26_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_26_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_26_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_26_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_26_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_26_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_26_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_26_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_26_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_26_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_26_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_26_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_26_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_26_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_26_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_26_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_26_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_26_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_26_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_26_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_26_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_26_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_26_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_26_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_26_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_26_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_26_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_26_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_27_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_27_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_27_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_27_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_27_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_27_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_27_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_27_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_27_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_27_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_27_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_27_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_27_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_27_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_27_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_27_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_27_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_27_is_br; // @[rob.scala:311:28]
reg rob_uop_1_27_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_27_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_27_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_27_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_27_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_27_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_27_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_27_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_27_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_27_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_27_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_27_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_27_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_prs3; // @[rob.scala:311:28]
reg rob_uop_1_27_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_27_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_27_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_27_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_27_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_27_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_27_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_27_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_27_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_27_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_27_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_27_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_27_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_27_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_27_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_27_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_27_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_27_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_27_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_27_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_27_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_27_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_27_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_27_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_27_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_27_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_27_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_27_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_27_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_27_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_27_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_27_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_28_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_28_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_28_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_28_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_28_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_28_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_28_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_28_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_28_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_28_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_28_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_28_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_28_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_28_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_28_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_28_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_28_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_28_is_br; // @[rob.scala:311:28]
reg rob_uop_1_28_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_28_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_28_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_28_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_28_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_28_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_28_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_28_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_28_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_28_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_28_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_28_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_28_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_prs3; // @[rob.scala:311:28]
reg rob_uop_1_28_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_28_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_28_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_28_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_28_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_28_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_28_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_28_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_28_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_28_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_28_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_28_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_28_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_28_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_28_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_28_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_28_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_28_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_28_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_28_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_28_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_28_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_28_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_28_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_28_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_28_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_28_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_28_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_28_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_28_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_28_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_28_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_29_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_29_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_29_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_29_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_29_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_29_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_29_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_29_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_29_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_29_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_29_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_29_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_29_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_29_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_29_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_29_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_29_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_29_is_br; // @[rob.scala:311:28]
reg rob_uop_1_29_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_29_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_29_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_29_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_29_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_29_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_29_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_29_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_29_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_29_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_29_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_29_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_29_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_prs3; // @[rob.scala:311:28]
reg rob_uop_1_29_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_29_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_29_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_29_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_29_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_29_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_29_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_29_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_29_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_29_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_29_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_29_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_29_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_29_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_29_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_29_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_29_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_29_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_29_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_29_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_29_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_29_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_29_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_29_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_29_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_29_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_29_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_29_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_29_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_29_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_29_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_29_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_30_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_30_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_30_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_30_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_30_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_30_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_30_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_30_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_30_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_30_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_30_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_30_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_30_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_30_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_30_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_30_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_30_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_30_is_br; // @[rob.scala:311:28]
reg rob_uop_1_30_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_30_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_30_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_30_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_30_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_30_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_30_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_30_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_30_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_30_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_30_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_30_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_30_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_prs3; // @[rob.scala:311:28]
reg rob_uop_1_30_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_30_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_30_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_30_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_30_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_30_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_30_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_30_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_30_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_30_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_30_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_30_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_30_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_30_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_30_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_30_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_30_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_30_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_30_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_30_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_30_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_30_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_30_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_30_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_30_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_30_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_30_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_30_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_30_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_30_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_30_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_30_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_31_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_1_31_debug_inst; // @[rob.scala:311:28]
reg rob_uop_1_31_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_1_31_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_31_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_1_31_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_31_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_31_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_31_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_31_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_1_31_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_1_31_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_1_31_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_1_31_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_1_31_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_iw_state; // @[rob.scala:311:28]
reg rob_uop_1_31_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_31_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_1_31_is_br; // @[rob.scala:311:28]
reg rob_uop_1_31_is_jalr; // @[rob.scala:311:28]
reg rob_uop_1_31_is_jal; // @[rob.scala:311:28]
reg rob_uop_1_31_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_1_31_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_1_31_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_31_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_1_31_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_31_pc_lob; // @[rob.scala:311:28]
reg rob_uop_1_31_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_1_31_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_1_31_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_31_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_31_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_prs3; // @[rob.scala:311:28]
reg rob_uop_1_31_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_1_31_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_1_31_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_1_31_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_1_31_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_1_31_exc_cause; // @[rob.scala:311:28]
reg rob_uop_1_31_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_1_31_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_mem_size; // @[rob.scala:311:28]
reg rob_uop_1_31_mem_signed; // @[rob.scala:311:28]
reg rob_uop_1_31_is_fence; // @[rob.scala:311:28]
reg rob_uop_1_31_is_fencei; // @[rob.scala:311:28]
reg rob_uop_1_31_is_amo; // @[rob.scala:311:28]
reg rob_uop_1_31_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_1_31_uses_stq; // @[rob.scala:311:28]
reg rob_uop_1_31_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_1_31_is_unique; // @[rob.scala:311:28]
reg rob_uop_1_31_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_1_31_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_31_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_31_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_31_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_1_31_lrs3; // @[rob.scala:311:28]
reg rob_uop_1_31_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_1_31_frs3_en; // @[rob.scala:311:28]
reg rob_uop_1_31_fp_val; // @[rob.scala:311:28]
reg rob_uop_1_31_fp_single; // @[rob.scala:311:28]
reg rob_uop_1_31_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_1_31_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_1_31_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_1_31_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_1_31_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_1_31_debug_tsrc; // @[rob.scala:311:28]
reg rob_exception_1_0; // @[rob.scala:312:28]
reg rob_exception_1_1; // @[rob.scala:312:28]
reg rob_exception_1_2; // @[rob.scala:312:28]
reg rob_exception_1_3; // @[rob.scala:312:28]
reg rob_exception_1_4; // @[rob.scala:312:28]
reg rob_exception_1_5; // @[rob.scala:312:28]
reg rob_exception_1_6; // @[rob.scala:312:28]
reg rob_exception_1_7; // @[rob.scala:312:28]
reg rob_exception_1_8; // @[rob.scala:312:28]
reg rob_exception_1_9; // @[rob.scala:312:28]
reg rob_exception_1_10; // @[rob.scala:312:28]
reg rob_exception_1_11; // @[rob.scala:312:28]
reg rob_exception_1_12; // @[rob.scala:312:28]
reg rob_exception_1_13; // @[rob.scala:312:28]
reg rob_exception_1_14; // @[rob.scala:312:28]
reg rob_exception_1_15; // @[rob.scala:312:28]
reg rob_exception_1_16; // @[rob.scala:312:28]
reg rob_exception_1_17; // @[rob.scala:312:28]
reg rob_exception_1_18; // @[rob.scala:312:28]
reg rob_exception_1_19; // @[rob.scala:312:28]
reg rob_exception_1_20; // @[rob.scala:312:28]
reg rob_exception_1_21; // @[rob.scala:312:28]
reg rob_exception_1_22; // @[rob.scala:312:28]
reg rob_exception_1_23; // @[rob.scala:312:28]
reg rob_exception_1_24; // @[rob.scala:312:28]
reg rob_exception_1_25; // @[rob.scala:312:28]
reg rob_exception_1_26; // @[rob.scala:312:28]
reg rob_exception_1_27; // @[rob.scala:312:28]
reg rob_exception_1_28; // @[rob.scala:312:28]
reg rob_exception_1_29; // @[rob.scala:312:28]
reg rob_exception_1_30; // @[rob.scala:312:28]
reg rob_exception_1_31; // @[rob.scala:312:28]
reg rob_predicated_1_0; // @[rob.scala:313:29]
reg rob_predicated_1_1; // @[rob.scala:313:29]
reg rob_predicated_1_2; // @[rob.scala:313:29]
reg rob_predicated_1_3; // @[rob.scala:313:29]
reg rob_predicated_1_4; // @[rob.scala:313:29]
reg rob_predicated_1_5; // @[rob.scala:313:29]
reg rob_predicated_1_6; // @[rob.scala:313:29]
reg rob_predicated_1_7; // @[rob.scala:313:29]
reg rob_predicated_1_8; // @[rob.scala:313:29]
reg rob_predicated_1_9; // @[rob.scala:313:29]
reg rob_predicated_1_10; // @[rob.scala:313:29]
reg rob_predicated_1_11; // @[rob.scala:313:29]
reg rob_predicated_1_12; // @[rob.scala:313:29]
reg rob_predicated_1_13; // @[rob.scala:313:29]
reg rob_predicated_1_14; // @[rob.scala:313:29]
reg rob_predicated_1_15; // @[rob.scala:313:29]
reg rob_predicated_1_16; // @[rob.scala:313:29]
reg rob_predicated_1_17; // @[rob.scala:313:29]
reg rob_predicated_1_18; // @[rob.scala:313:29]
reg rob_predicated_1_19; // @[rob.scala:313:29]
reg rob_predicated_1_20; // @[rob.scala:313:29]
reg rob_predicated_1_21; // @[rob.scala:313:29]
reg rob_predicated_1_22; // @[rob.scala:313:29]
reg rob_predicated_1_23; // @[rob.scala:313:29]
reg rob_predicated_1_24; // @[rob.scala:313:29]
reg rob_predicated_1_25; // @[rob.scala:313:29]
reg rob_predicated_1_26; // @[rob.scala:313:29]
reg rob_predicated_1_27; // @[rob.scala:313:29]
reg rob_predicated_1_28; // @[rob.scala:313:29]
reg rob_predicated_1_29; // @[rob.scala:313:29]
reg rob_predicated_1_30; // @[rob.scala:313:29]
reg rob_predicated_1_31; // @[rob.scala:313:29]
wire [31:0] _GEN_94 = {{rob_val_1_31}, {rob_val_1_30}, {rob_val_1_29}, {rob_val_1_28}, {rob_val_1_27}, {rob_val_1_26}, {rob_val_1_25}, {rob_val_1_24}, {rob_val_1_23}, {rob_val_1_22}, {rob_val_1_21}, {rob_val_1_20}, {rob_val_1_19}, {rob_val_1_18}, {rob_val_1_17}, {rob_val_1_16}, {rob_val_1_15}, {rob_val_1_14}, {rob_val_1_13}, {rob_val_1_12}, {rob_val_1_11}, {rob_val_1_10}, {rob_val_1_9}, {rob_val_1_8}, {rob_val_1_7}, {rob_val_1_6}, {rob_val_1_5}, {rob_val_1_4}, {rob_val_1_3}, {rob_val_1_2}, {rob_val_1_1}, {rob_val_1_0}}; // @[rob.scala:308:32, :324:31]
assign rob_tail_vals_1 = _GEN_94[rob_tail]; // @[rob.scala:227:29, :248:33, :324:31]
wire _rob_bsy_T_2 = io_enq_uops_1_is_fence_0 | io_enq_uops_1_is_fencei_0; // @[rob.scala:211:7, :325:60]
wire _rob_bsy_T_3 = ~_rob_bsy_T_2; // @[rob.scala:325:{34,60}]
wire _rob_unsafe_T_5 = ~io_enq_uops_1_is_fence_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_6 = io_enq_uops_1_uses_stq_0 & _rob_unsafe_T_5; // @[rob.scala:211:7]
wire _rob_unsafe_T_7 = io_enq_uops_1_uses_ldq_0 | _rob_unsafe_T_6; // @[rob.scala:211:7]
wire _rob_unsafe_T_8 = _rob_unsafe_T_7 | io_enq_uops_1_is_br_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_9 = _rob_unsafe_T_8 | io_enq_uops_1_is_jalr_0; // @[rob.scala:211:7]
wire _T_468 = io_lsu_clr_bsy_0_valid_0 & io_lsu_clr_bsy_0_bits_0[1:0] == 2'h1; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire [31:0] _GEN_95 = {{rob_bsy_1_31}, {rob_bsy_1_30}, {rob_bsy_1_29}, {rob_bsy_1_28}, {rob_bsy_1_27}, {rob_bsy_1_26}, {rob_bsy_1_25}, {rob_bsy_1_24}, {rob_bsy_1_23}, {rob_bsy_1_22}, {rob_bsy_1_21}, {rob_bsy_1_20}, {rob_bsy_1_19}, {rob_bsy_1_18}, {rob_bsy_1_17}, {rob_bsy_1_16}, {rob_bsy_1_15}, {rob_bsy_1_14}, {rob_bsy_1_13}, {rob_bsy_1_12}, {rob_bsy_1_11}, {rob_bsy_1_10}, {rob_bsy_1_9}, {rob_bsy_1_8}, {rob_bsy_1_7}, {rob_bsy_1_6}, {rob_bsy_1_5}, {rob_bsy_1_4}, {rob_bsy_1_3}, {rob_bsy_1_2}, {rob_bsy_1_1}, {rob_bsy_1_0}}; // @[rob.scala:309:28, :366:31]
wire _T_483 = io_lsu_clr_bsy_1_valid_0 & io_lsu_clr_bsy_1_bits_0[1:0] == 2'h1; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire _T_512 = io_lxcpt_valid_0 & io_lxcpt_bits_uop_rob_idx_0[1:0] == 2'h1; // @[rob.scala:211:7, :271:36, :305:53, :390:26]
wire _GEN_96 = _T_512 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:211:7, :390:26, :392:{33,66}, :394:15]
wire [31:0] _GEN_97 = {{rob_unsafe_1_31}, {rob_unsafe_1_30}, {rob_unsafe_1_29}, {rob_unsafe_1_28}, {rob_unsafe_1_27}, {rob_unsafe_1_26}, {rob_unsafe_1_25}, {rob_unsafe_1_24}, {rob_unsafe_1_23}, {rob_unsafe_1_22}, {rob_unsafe_1_21}, {rob_unsafe_1_20}, {rob_unsafe_1_19}, {rob_unsafe_1_18}, {rob_unsafe_1_17}, {rob_unsafe_1_16}, {rob_unsafe_1_15}, {rob_unsafe_1_14}, {rob_unsafe_1_13}, {rob_unsafe_1_12}, {rob_unsafe_1_11}, {rob_unsafe_1_10}, {rob_unsafe_1_9}, {rob_unsafe_1_8}, {rob_unsafe_1_7}, {rob_unsafe_1_6}, {rob_unsafe_1_5}, {rob_unsafe_1_4}, {rob_unsafe_1_3}, {rob_unsafe_1_2}, {rob_unsafe_1_1}, {rob_unsafe_1_0}}; // @[rob.scala:310:28, :394:15]
wire _GEN_98 = _GEN_97[io_lxcpt_bits_uop_rob_idx_0[6:2]]; // @[rob.scala:211:7, :267:25, :394:15]
assign rob_head_vals_1 = _GEN_94[rob_head]; // @[rob.scala:223:29, :247:33, :324:31, :402:49]
wire [31:0] _GEN_99 = {{rob_exception_1_31}, {rob_exception_1_30}, {rob_exception_1_29}, {rob_exception_1_28}, {rob_exception_1_27}, {rob_exception_1_26}, {rob_exception_1_25}, {rob_exception_1_24}, {rob_exception_1_23}, {rob_exception_1_22}, {rob_exception_1_21}, {rob_exception_1_20}, {rob_exception_1_19}, {rob_exception_1_18}, {rob_exception_1_17}, {rob_exception_1_16}, {rob_exception_1_15}, {rob_exception_1_14}, {rob_exception_1_13}, {rob_exception_1_12}, {rob_exception_1_11}, {rob_exception_1_10}, {rob_exception_1_9}, {rob_exception_1_8}, {rob_exception_1_7}, {rob_exception_1_6}, {rob_exception_1_5}, {rob_exception_1_4}, {rob_exception_1_3}, {rob_exception_1_2}, {rob_exception_1_1}, {rob_exception_1_0}}; // @[rob.scala:312:28, :402:49]
assign _can_throw_exception_1_T = rob_head_vals_1 & _GEN_99[rob_head]; // @[rob.scala:223:29, :247:33, :402:49]
assign can_throw_exception_1 = _can_throw_exception_1_T; // @[rob.scala:244:33, :402:49]
wire _can_commit_1_T = ~_GEN_95[rob_head]; // @[rob.scala:223:29, :366:31, :408:43]
wire _can_commit_1_T_1 = rob_head_vals_1 & _can_commit_1_T; // @[rob.scala:247:33, :408:{40,43}]
wire _can_commit_1_T_2 = ~io_csr_stall_0; // @[rob.scala:211:7, :408:67]
assign _can_commit_1_T_3 = _can_commit_1_T_1 & _can_commit_1_T_2; // @[rob.scala:408:{40,64,67}]
assign can_commit_1 = _can_commit_1_T_3; // @[rob.scala:243:33, :408:64]
wire [31:0] _GEN_100 = {{rob_predicated_1_31}, {rob_predicated_1_30}, {rob_predicated_1_29}, {rob_predicated_1_28}, {rob_predicated_1_27}, {rob_predicated_1_26}, {rob_predicated_1_25}, {rob_predicated_1_24}, {rob_predicated_1_23}, {rob_predicated_1_22}, {rob_predicated_1_21}, {rob_predicated_1_20}, {rob_predicated_1_19}, {rob_predicated_1_18}, {rob_predicated_1_17}, {rob_predicated_1_16}, {rob_predicated_1_15}, {rob_predicated_1_14}, {rob_predicated_1_13}, {rob_predicated_1_12}, {rob_predicated_1_11}, {rob_predicated_1_10}, {rob_predicated_1_9}, {rob_predicated_1_8}, {rob_predicated_1_7}, {rob_predicated_1_6}, {rob_predicated_1_5}, {rob_predicated_1_4}, {rob_predicated_1_3}, {rob_predicated_1_2}, {rob_predicated_1_1}, {rob_predicated_1_0}}; // @[rob.scala:313:29, :414:51]
wire _io_commit_arch_valids_1_T = ~_GEN_100[com_idx]; // @[rob.scala:235:20, :414:51]
assign _io_commit_arch_valids_1_T_1 = will_commit_1 & _io_commit_arch_valids_1_T; // @[rob.scala:242:33, :414:{48,51}]
assign io_commit_arch_valids_1_0 = _io_commit_arch_valids_1_T_1; // @[rob.scala:211:7, :414:48]
wire [31:0][6:0] _GEN_101 = {{rob_uop_1_31_uopc}, {rob_uop_1_30_uopc}, {rob_uop_1_29_uopc}, {rob_uop_1_28_uopc}, {rob_uop_1_27_uopc}, {rob_uop_1_26_uopc}, {rob_uop_1_25_uopc}, {rob_uop_1_24_uopc}, {rob_uop_1_23_uopc}, {rob_uop_1_22_uopc}, {rob_uop_1_21_uopc}, {rob_uop_1_20_uopc}, {rob_uop_1_19_uopc}, {rob_uop_1_18_uopc}, {rob_uop_1_17_uopc}, {rob_uop_1_16_uopc}, {rob_uop_1_15_uopc}, {rob_uop_1_14_uopc}, {rob_uop_1_13_uopc}, {rob_uop_1_12_uopc}, {rob_uop_1_11_uopc}, {rob_uop_1_10_uopc}, {rob_uop_1_9_uopc}, {rob_uop_1_8_uopc}, {rob_uop_1_7_uopc}, {rob_uop_1_6_uopc}, {rob_uop_1_5_uopc}, {rob_uop_1_4_uopc}, {rob_uop_1_3_uopc}, {rob_uop_1_2_uopc}, {rob_uop_1_1_uopc}, {rob_uop_1_0_uopc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_uopc_0 = _GEN_101[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_102 = {{rob_uop_1_31_inst}, {rob_uop_1_30_inst}, {rob_uop_1_29_inst}, {rob_uop_1_28_inst}, {rob_uop_1_27_inst}, {rob_uop_1_26_inst}, {rob_uop_1_25_inst}, {rob_uop_1_24_inst}, {rob_uop_1_23_inst}, {rob_uop_1_22_inst}, {rob_uop_1_21_inst}, {rob_uop_1_20_inst}, {rob_uop_1_19_inst}, {rob_uop_1_18_inst}, {rob_uop_1_17_inst}, {rob_uop_1_16_inst}, {rob_uop_1_15_inst}, {rob_uop_1_14_inst}, {rob_uop_1_13_inst}, {rob_uop_1_12_inst}, {rob_uop_1_11_inst}, {rob_uop_1_10_inst}, {rob_uop_1_9_inst}, {rob_uop_1_8_inst}, {rob_uop_1_7_inst}, {rob_uop_1_6_inst}, {rob_uop_1_5_inst}, {rob_uop_1_4_inst}, {rob_uop_1_3_inst}, {rob_uop_1_2_inst}, {rob_uop_1_1_inst}, {rob_uop_1_0_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_inst_0 = _GEN_102[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_103 = {{rob_uop_1_31_debug_inst}, {rob_uop_1_30_debug_inst}, {rob_uop_1_29_debug_inst}, {rob_uop_1_28_debug_inst}, {rob_uop_1_27_debug_inst}, {rob_uop_1_26_debug_inst}, {rob_uop_1_25_debug_inst}, {rob_uop_1_24_debug_inst}, {rob_uop_1_23_debug_inst}, {rob_uop_1_22_debug_inst}, {rob_uop_1_21_debug_inst}, {rob_uop_1_20_debug_inst}, {rob_uop_1_19_debug_inst}, {rob_uop_1_18_debug_inst}, {rob_uop_1_17_debug_inst}, {rob_uop_1_16_debug_inst}, {rob_uop_1_15_debug_inst}, {rob_uop_1_14_debug_inst}, {rob_uop_1_13_debug_inst}, {rob_uop_1_12_debug_inst}, {rob_uop_1_11_debug_inst}, {rob_uop_1_10_debug_inst}, {rob_uop_1_9_debug_inst}, {rob_uop_1_8_debug_inst}, {rob_uop_1_7_debug_inst}, {rob_uop_1_6_debug_inst}, {rob_uop_1_5_debug_inst}, {rob_uop_1_4_debug_inst}, {rob_uop_1_3_debug_inst}, {rob_uop_1_2_debug_inst}, {rob_uop_1_1_debug_inst}, {rob_uop_1_0_debug_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_debug_inst_0 = _GEN_103[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_104 = {{rob_uop_1_31_is_rvc}, {rob_uop_1_30_is_rvc}, {rob_uop_1_29_is_rvc}, {rob_uop_1_28_is_rvc}, {rob_uop_1_27_is_rvc}, {rob_uop_1_26_is_rvc}, {rob_uop_1_25_is_rvc}, {rob_uop_1_24_is_rvc}, {rob_uop_1_23_is_rvc}, {rob_uop_1_22_is_rvc}, {rob_uop_1_21_is_rvc}, {rob_uop_1_20_is_rvc}, {rob_uop_1_19_is_rvc}, {rob_uop_1_18_is_rvc}, {rob_uop_1_17_is_rvc}, {rob_uop_1_16_is_rvc}, {rob_uop_1_15_is_rvc}, {rob_uop_1_14_is_rvc}, {rob_uop_1_13_is_rvc}, {rob_uop_1_12_is_rvc}, {rob_uop_1_11_is_rvc}, {rob_uop_1_10_is_rvc}, {rob_uop_1_9_is_rvc}, {rob_uop_1_8_is_rvc}, {rob_uop_1_7_is_rvc}, {rob_uop_1_6_is_rvc}, {rob_uop_1_5_is_rvc}, {rob_uop_1_4_is_rvc}, {rob_uop_1_3_is_rvc}, {rob_uop_1_2_is_rvc}, {rob_uop_1_1_is_rvc}, {rob_uop_1_0_is_rvc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_rvc_0 = _GEN_104[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][39:0] _GEN_105 = {{rob_uop_1_31_debug_pc}, {rob_uop_1_30_debug_pc}, {rob_uop_1_29_debug_pc}, {rob_uop_1_28_debug_pc}, {rob_uop_1_27_debug_pc}, {rob_uop_1_26_debug_pc}, {rob_uop_1_25_debug_pc}, {rob_uop_1_24_debug_pc}, {rob_uop_1_23_debug_pc}, {rob_uop_1_22_debug_pc}, {rob_uop_1_21_debug_pc}, {rob_uop_1_20_debug_pc}, {rob_uop_1_19_debug_pc}, {rob_uop_1_18_debug_pc}, {rob_uop_1_17_debug_pc}, {rob_uop_1_16_debug_pc}, {rob_uop_1_15_debug_pc}, {rob_uop_1_14_debug_pc}, {rob_uop_1_13_debug_pc}, {rob_uop_1_12_debug_pc}, {rob_uop_1_11_debug_pc}, {rob_uop_1_10_debug_pc}, {rob_uop_1_9_debug_pc}, {rob_uop_1_8_debug_pc}, {rob_uop_1_7_debug_pc}, {rob_uop_1_6_debug_pc}, {rob_uop_1_5_debug_pc}, {rob_uop_1_4_debug_pc}, {rob_uop_1_3_debug_pc}, {rob_uop_1_2_debug_pc}, {rob_uop_1_1_debug_pc}, {rob_uop_1_0_debug_pc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_debug_pc_0 = _GEN_105[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_106 = {{rob_uop_1_31_iq_type}, {rob_uop_1_30_iq_type}, {rob_uop_1_29_iq_type}, {rob_uop_1_28_iq_type}, {rob_uop_1_27_iq_type}, {rob_uop_1_26_iq_type}, {rob_uop_1_25_iq_type}, {rob_uop_1_24_iq_type}, {rob_uop_1_23_iq_type}, {rob_uop_1_22_iq_type}, {rob_uop_1_21_iq_type}, {rob_uop_1_20_iq_type}, {rob_uop_1_19_iq_type}, {rob_uop_1_18_iq_type}, {rob_uop_1_17_iq_type}, {rob_uop_1_16_iq_type}, {rob_uop_1_15_iq_type}, {rob_uop_1_14_iq_type}, {rob_uop_1_13_iq_type}, {rob_uop_1_12_iq_type}, {rob_uop_1_11_iq_type}, {rob_uop_1_10_iq_type}, {rob_uop_1_9_iq_type}, {rob_uop_1_8_iq_type}, {rob_uop_1_7_iq_type}, {rob_uop_1_6_iq_type}, {rob_uop_1_5_iq_type}, {rob_uop_1_4_iq_type}, {rob_uop_1_3_iq_type}, {rob_uop_1_2_iq_type}, {rob_uop_1_1_iq_type}, {rob_uop_1_0_iq_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_iq_type_0 = _GEN_106[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][9:0] _GEN_107 = {{rob_uop_1_31_fu_code}, {rob_uop_1_30_fu_code}, {rob_uop_1_29_fu_code}, {rob_uop_1_28_fu_code}, {rob_uop_1_27_fu_code}, {rob_uop_1_26_fu_code}, {rob_uop_1_25_fu_code}, {rob_uop_1_24_fu_code}, {rob_uop_1_23_fu_code}, {rob_uop_1_22_fu_code}, {rob_uop_1_21_fu_code}, {rob_uop_1_20_fu_code}, {rob_uop_1_19_fu_code}, {rob_uop_1_18_fu_code}, {rob_uop_1_17_fu_code}, {rob_uop_1_16_fu_code}, {rob_uop_1_15_fu_code}, {rob_uop_1_14_fu_code}, {rob_uop_1_13_fu_code}, {rob_uop_1_12_fu_code}, {rob_uop_1_11_fu_code}, {rob_uop_1_10_fu_code}, {rob_uop_1_9_fu_code}, {rob_uop_1_8_fu_code}, {rob_uop_1_7_fu_code}, {rob_uop_1_6_fu_code}, {rob_uop_1_5_fu_code}, {rob_uop_1_4_fu_code}, {rob_uop_1_3_fu_code}, {rob_uop_1_2_fu_code}, {rob_uop_1_1_fu_code}, {rob_uop_1_0_fu_code}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_fu_code_0 = _GEN_107[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_108 = {{rob_uop_1_31_ctrl_br_type}, {rob_uop_1_30_ctrl_br_type}, {rob_uop_1_29_ctrl_br_type}, {rob_uop_1_28_ctrl_br_type}, {rob_uop_1_27_ctrl_br_type}, {rob_uop_1_26_ctrl_br_type}, {rob_uop_1_25_ctrl_br_type}, {rob_uop_1_24_ctrl_br_type}, {rob_uop_1_23_ctrl_br_type}, {rob_uop_1_22_ctrl_br_type}, {rob_uop_1_21_ctrl_br_type}, {rob_uop_1_20_ctrl_br_type}, {rob_uop_1_19_ctrl_br_type}, {rob_uop_1_18_ctrl_br_type}, {rob_uop_1_17_ctrl_br_type}, {rob_uop_1_16_ctrl_br_type}, {rob_uop_1_15_ctrl_br_type}, {rob_uop_1_14_ctrl_br_type}, {rob_uop_1_13_ctrl_br_type}, {rob_uop_1_12_ctrl_br_type}, {rob_uop_1_11_ctrl_br_type}, {rob_uop_1_10_ctrl_br_type}, {rob_uop_1_9_ctrl_br_type}, {rob_uop_1_8_ctrl_br_type}, {rob_uop_1_7_ctrl_br_type}, {rob_uop_1_6_ctrl_br_type}, {rob_uop_1_5_ctrl_br_type}, {rob_uop_1_4_ctrl_br_type}, {rob_uop_1_3_ctrl_br_type}, {rob_uop_1_2_ctrl_br_type}, {rob_uop_1_1_ctrl_br_type}, {rob_uop_1_0_ctrl_br_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_br_type_0 = _GEN_108[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_109 = {{rob_uop_1_31_ctrl_op1_sel}, {rob_uop_1_30_ctrl_op1_sel}, {rob_uop_1_29_ctrl_op1_sel}, {rob_uop_1_28_ctrl_op1_sel}, {rob_uop_1_27_ctrl_op1_sel}, {rob_uop_1_26_ctrl_op1_sel}, {rob_uop_1_25_ctrl_op1_sel}, {rob_uop_1_24_ctrl_op1_sel}, {rob_uop_1_23_ctrl_op1_sel}, {rob_uop_1_22_ctrl_op1_sel}, {rob_uop_1_21_ctrl_op1_sel}, {rob_uop_1_20_ctrl_op1_sel}, {rob_uop_1_19_ctrl_op1_sel}, {rob_uop_1_18_ctrl_op1_sel}, {rob_uop_1_17_ctrl_op1_sel}, {rob_uop_1_16_ctrl_op1_sel}, {rob_uop_1_15_ctrl_op1_sel}, {rob_uop_1_14_ctrl_op1_sel}, {rob_uop_1_13_ctrl_op1_sel}, {rob_uop_1_12_ctrl_op1_sel}, {rob_uop_1_11_ctrl_op1_sel}, {rob_uop_1_10_ctrl_op1_sel}, {rob_uop_1_9_ctrl_op1_sel}, {rob_uop_1_8_ctrl_op1_sel}, {rob_uop_1_7_ctrl_op1_sel}, {rob_uop_1_6_ctrl_op1_sel}, {rob_uop_1_5_ctrl_op1_sel}, {rob_uop_1_4_ctrl_op1_sel}, {rob_uop_1_3_ctrl_op1_sel}, {rob_uop_1_2_ctrl_op1_sel}, {rob_uop_1_1_ctrl_op1_sel}, {rob_uop_1_0_ctrl_op1_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_op1_sel_0 = _GEN_109[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_110 = {{rob_uop_1_31_ctrl_op2_sel}, {rob_uop_1_30_ctrl_op2_sel}, {rob_uop_1_29_ctrl_op2_sel}, {rob_uop_1_28_ctrl_op2_sel}, {rob_uop_1_27_ctrl_op2_sel}, {rob_uop_1_26_ctrl_op2_sel}, {rob_uop_1_25_ctrl_op2_sel}, {rob_uop_1_24_ctrl_op2_sel}, {rob_uop_1_23_ctrl_op2_sel}, {rob_uop_1_22_ctrl_op2_sel}, {rob_uop_1_21_ctrl_op2_sel}, {rob_uop_1_20_ctrl_op2_sel}, {rob_uop_1_19_ctrl_op2_sel}, {rob_uop_1_18_ctrl_op2_sel}, {rob_uop_1_17_ctrl_op2_sel}, {rob_uop_1_16_ctrl_op2_sel}, {rob_uop_1_15_ctrl_op2_sel}, {rob_uop_1_14_ctrl_op2_sel}, {rob_uop_1_13_ctrl_op2_sel}, {rob_uop_1_12_ctrl_op2_sel}, {rob_uop_1_11_ctrl_op2_sel}, {rob_uop_1_10_ctrl_op2_sel}, {rob_uop_1_9_ctrl_op2_sel}, {rob_uop_1_8_ctrl_op2_sel}, {rob_uop_1_7_ctrl_op2_sel}, {rob_uop_1_6_ctrl_op2_sel}, {rob_uop_1_5_ctrl_op2_sel}, {rob_uop_1_4_ctrl_op2_sel}, {rob_uop_1_3_ctrl_op2_sel}, {rob_uop_1_2_ctrl_op2_sel}, {rob_uop_1_1_ctrl_op2_sel}, {rob_uop_1_0_ctrl_op2_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_op2_sel_0 = _GEN_110[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_111 = {{rob_uop_1_31_ctrl_imm_sel}, {rob_uop_1_30_ctrl_imm_sel}, {rob_uop_1_29_ctrl_imm_sel}, {rob_uop_1_28_ctrl_imm_sel}, {rob_uop_1_27_ctrl_imm_sel}, {rob_uop_1_26_ctrl_imm_sel}, {rob_uop_1_25_ctrl_imm_sel}, {rob_uop_1_24_ctrl_imm_sel}, {rob_uop_1_23_ctrl_imm_sel}, {rob_uop_1_22_ctrl_imm_sel}, {rob_uop_1_21_ctrl_imm_sel}, {rob_uop_1_20_ctrl_imm_sel}, {rob_uop_1_19_ctrl_imm_sel}, {rob_uop_1_18_ctrl_imm_sel}, {rob_uop_1_17_ctrl_imm_sel}, {rob_uop_1_16_ctrl_imm_sel}, {rob_uop_1_15_ctrl_imm_sel}, {rob_uop_1_14_ctrl_imm_sel}, {rob_uop_1_13_ctrl_imm_sel}, {rob_uop_1_12_ctrl_imm_sel}, {rob_uop_1_11_ctrl_imm_sel}, {rob_uop_1_10_ctrl_imm_sel}, {rob_uop_1_9_ctrl_imm_sel}, {rob_uop_1_8_ctrl_imm_sel}, {rob_uop_1_7_ctrl_imm_sel}, {rob_uop_1_6_ctrl_imm_sel}, {rob_uop_1_5_ctrl_imm_sel}, {rob_uop_1_4_ctrl_imm_sel}, {rob_uop_1_3_ctrl_imm_sel}, {rob_uop_1_2_ctrl_imm_sel}, {rob_uop_1_1_ctrl_imm_sel}, {rob_uop_1_0_ctrl_imm_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_imm_sel_0 = _GEN_111[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_112 = {{rob_uop_1_31_ctrl_op_fcn}, {rob_uop_1_30_ctrl_op_fcn}, {rob_uop_1_29_ctrl_op_fcn}, {rob_uop_1_28_ctrl_op_fcn}, {rob_uop_1_27_ctrl_op_fcn}, {rob_uop_1_26_ctrl_op_fcn}, {rob_uop_1_25_ctrl_op_fcn}, {rob_uop_1_24_ctrl_op_fcn}, {rob_uop_1_23_ctrl_op_fcn}, {rob_uop_1_22_ctrl_op_fcn}, {rob_uop_1_21_ctrl_op_fcn}, {rob_uop_1_20_ctrl_op_fcn}, {rob_uop_1_19_ctrl_op_fcn}, {rob_uop_1_18_ctrl_op_fcn}, {rob_uop_1_17_ctrl_op_fcn}, {rob_uop_1_16_ctrl_op_fcn}, {rob_uop_1_15_ctrl_op_fcn}, {rob_uop_1_14_ctrl_op_fcn}, {rob_uop_1_13_ctrl_op_fcn}, {rob_uop_1_12_ctrl_op_fcn}, {rob_uop_1_11_ctrl_op_fcn}, {rob_uop_1_10_ctrl_op_fcn}, {rob_uop_1_9_ctrl_op_fcn}, {rob_uop_1_8_ctrl_op_fcn}, {rob_uop_1_7_ctrl_op_fcn}, {rob_uop_1_6_ctrl_op_fcn}, {rob_uop_1_5_ctrl_op_fcn}, {rob_uop_1_4_ctrl_op_fcn}, {rob_uop_1_3_ctrl_op_fcn}, {rob_uop_1_2_ctrl_op_fcn}, {rob_uop_1_1_ctrl_op_fcn}, {rob_uop_1_0_ctrl_op_fcn}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_op_fcn_0 = _GEN_112[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_113 = {{rob_uop_1_31_ctrl_fcn_dw}, {rob_uop_1_30_ctrl_fcn_dw}, {rob_uop_1_29_ctrl_fcn_dw}, {rob_uop_1_28_ctrl_fcn_dw}, {rob_uop_1_27_ctrl_fcn_dw}, {rob_uop_1_26_ctrl_fcn_dw}, {rob_uop_1_25_ctrl_fcn_dw}, {rob_uop_1_24_ctrl_fcn_dw}, {rob_uop_1_23_ctrl_fcn_dw}, {rob_uop_1_22_ctrl_fcn_dw}, {rob_uop_1_21_ctrl_fcn_dw}, {rob_uop_1_20_ctrl_fcn_dw}, {rob_uop_1_19_ctrl_fcn_dw}, {rob_uop_1_18_ctrl_fcn_dw}, {rob_uop_1_17_ctrl_fcn_dw}, {rob_uop_1_16_ctrl_fcn_dw}, {rob_uop_1_15_ctrl_fcn_dw}, {rob_uop_1_14_ctrl_fcn_dw}, {rob_uop_1_13_ctrl_fcn_dw}, {rob_uop_1_12_ctrl_fcn_dw}, {rob_uop_1_11_ctrl_fcn_dw}, {rob_uop_1_10_ctrl_fcn_dw}, {rob_uop_1_9_ctrl_fcn_dw}, {rob_uop_1_8_ctrl_fcn_dw}, {rob_uop_1_7_ctrl_fcn_dw}, {rob_uop_1_6_ctrl_fcn_dw}, {rob_uop_1_5_ctrl_fcn_dw}, {rob_uop_1_4_ctrl_fcn_dw}, {rob_uop_1_3_ctrl_fcn_dw}, {rob_uop_1_2_ctrl_fcn_dw}, {rob_uop_1_1_ctrl_fcn_dw}, {rob_uop_1_0_ctrl_fcn_dw}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_fcn_dw_0 = _GEN_113[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_114 = {{rob_uop_1_31_ctrl_csr_cmd}, {rob_uop_1_30_ctrl_csr_cmd}, {rob_uop_1_29_ctrl_csr_cmd}, {rob_uop_1_28_ctrl_csr_cmd}, {rob_uop_1_27_ctrl_csr_cmd}, {rob_uop_1_26_ctrl_csr_cmd}, {rob_uop_1_25_ctrl_csr_cmd}, {rob_uop_1_24_ctrl_csr_cmd}, {rob_uop_1_23_ctrl_csr_cmd}, {rob_uop_1_22_ctrl_csr_cmd}, {rob_uop_1_21_ctrl_csr_cmd}, {rob_uop_1_20_ctrl_csr_cmd}, {rob_uop_1_19_ctrl_csr_cmd}, {rob_uop_1_18_ctrl_csr_cmd}, {rob_uop_1_17_ctrl_csr_cmd}, {rob_uop_1_16_ctrl_csr_cmd}, {rob_uop_1_15_ctrl_csr_cmd}, {rob_uop_1_14_ctrl_csr_cmd}, {rob_uop_1_13_ctrl_csr_cmd}, {rob_uop_1_12_ctrl_csr_cmd}, {rob_uop_1_11_ctrl_csr_cmd}, {rob_uop_1_10_ctrl_csr_cmd}, {rob_uop_1_9_ctrl_csr_cmd}, {rob_uop_1_8_ctrl_csr_cmd}, {rob_uop_1_7_ctrl_csr_cmd}, {rob_uop_1_6_ctrl_csr_cmd}, {rob_uop_1_5_ctrl_csr_cmd}, {rob_uop_1_4_ctrl_csr_cmd}, {rob_uop_1_3_ctrl_csr_cmd}, {rob_uop_1_2_ctrl_csr_cmd}, {rob_uop_1_1_ctrl_csr_cmd}, {rob_uop_1_0_ctrl_csr_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_csr_cmd_0 = _GEN_114[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_115 = {{rob_uop_1_31_ctrl_is_load}, {rob_uop_1_30_ctrl_is_load}, {rob_uop_1_29_ctrl_is_load}, {rob_uop_1_28_ctrl_is_load}, {rob_uop_1_27_ctrl_is_load}, {rob_uop_1_26_ctrl_is_load}, {rob_uop_1_25_ctrl_is_load}, {rob_uop_1_24_ctrl_is_load}, {rob_uop_1_23_ctrl_is_load}, {rob_uop_1_22_ctrl_is_load}, {rob_uop_1_21_ctrl_is_load}, {rob_uop_1_20_ctrl_is_load}, {rob_uop_1_19_ctrl_is_load}, {rob_uop_1_18_ctrl_is_load}, {rob_uop_1_17_ctrl_is_load}, {rob_uop_1_16_ctrl_is_load}, {rob_uop_1_15_ctrl_is_load}, {rob_uop_1_14_ctrl_is_load}, {rob_uop_1_13_ctrl_is_load}, {rob_uop_1_12_ctrl_is_load}, {rob_uop_1_11_ctrl_is_load}, {rob_uop_1_10_ctrl_is_load}, {rob_uop_1_9_ctrl_is_load}, {rob_uop_1_8_ctrl_is_load}, {rob_uop_1_7_ctrl_is_load}, {rob_uop_1_6_ctrl_is_load}, {rob_uop_1_5_ctrl_is_load}, {rob_uop_1_4_ctrl_is_load}, {rob_uop_1_3_ctrl_is_load}, {rob_uop_1_2_ctrl_is_load}, {rob_uop_1_1_ctrl_is_load}, {rob_uop_1_0_ctrl_is_load}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_is_load_0 = _GEN_115[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_116 = {{rob_uop_1_31_ctrl_is_sta}, {rob_uop_1_30_ctrl_is_sta}, {rob_uop_1_29_ctrl_is_sta}, {rob_uop_1_28_ctrl_is_sta}, {rob_uop_1_27_ctrl_is_sta}, {rob_uop_1_26_ctrl_is_sta}, {rob_uop_1_25_ctrl_is_sta}, {rob_uop_1_24_ctrl_is_sta}, {rob_uop_1_23_ctrl_is_sta}, {rob_uop_1_22_ctrl_is_sta}, {rob_uop_1_21_ctrl_is_sta}, {rob_uop_1_20_ctrl_is_sta}, {rob_uop_1_19_ctrl_is_sta}, {rob_uop_1_18_ctrl_is_sta}, {rob_uop_1_17_ctrl_is_sta}, {rob_uop_1_16_ctrl_is_sta}, {rob_uop_1_15_ctrl_is_sta}, {rob_uop_1_14_ctrl_is_sta}, {rob_uop_1_13_ctrl_is_sta}, {rob_uop_1_12_ctrl_is_sta}, {rob_uop_1_11_ctrl_is_sta}, {rob_uop_1_10_ctrl_is_sta}, {rob_uop_1_9_ctrl_is_sta}, {rob_uop_1_8_ctrl_is_sta}, {rob_uop_1_7_ctrl_is_sta}, {rob_uop_1_6_ctrl_is_sta}, {rob_uop_1_5_ctrl_is_sta}, {rob_uop_1_4_ctrl_is_sta}, {rob_uop_1_3_ctrl_is_sta}, {rob_uop_1_2_ctrl_is_sta}, {rob_uop_1_1_ctrl_is_sta}, {rob_uop_1_0_ctrl_is_sta}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_is_sta_0 = _GEN_116[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_117 = {{rob_uop_1_31_ctrl_is_std}, {rob_uop_1_30_ctrl_is_std}, {rob_uop_1_29_ctrl_is_std}, {rob_uop_1_28_ctrl_is_std}, {rob_uop_1_27_ctrl_is_std}, {rob_uop_1_26_ctrl_is_std}, {rob_uop_1_25_ctrl_is_std}, {rob_uop_1_24_ctrl_is_std}, {rob_uop_1_23_ctrl_is_std}, {rob_uop_1_22_ctrl_is_std}, {rob_uop_1_21_ctrl_is_std}, {rob_uop_1_20_ctrl_is_std}, {rob_uop_1_19_ctrl_is_std}, {rob_uop_1_18_ctrl_is_std}, {rob_uop_1_17_ctrl_is_std}, {rob_uop_1_16_ctrl_is_std}, {rob_uop_1_15_ctrl_is_std}, {rob_uop_1_14_ctrl_is_std}, {rob_uop_1_13_ctrl_is_std}, {rob_uop_1_12_ctrl_is_std}, {rob_uop_1_11_ctrl_is_std}, {rob_uop_1_10_ctrl_is_std}, {rob_uop_1_9_ctrl_is_std}, {rob_uop_1_8_ctrl_is_std}, {rob_uop_1_7_ctrl_is_std}, {rob_uop_1_6_ctrl_is_std}, {rob_uop_1_5_ctrl_is_std}, {rob_uop_1_4_ctrl_is_std}, {rob_uop_1_3_ctrl_is_std}, {rob_uop_1_2_ctrl_is_std}, {rob_uop_1_1_ctrl_is_std}, {rob_uop_1_0_ctrl_is_std}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ctrl_is_std_0 = _GEN_117[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_118 = {{rob_uop_1_31_iw_state}, {rob_uop_1_30_iw_state}, {rob_uop_1_29_iw_state}, {rob_uop_1_28_iw_state}, {rob_uop_1_27_iw_state}, {rob_uop_1_26_iw_state}, {rob_uop_1_25_iw_state}, {rob_uop_1_24_iw_state}, {rob_uop_1_23_iw_state}, {rob_uop_1_22_iw_state}, {rob_uop_1_21_iw_state}, {rob_uop_1_20_iw_state}, {rob_uop_1_19_iw_state}, {rob_uop_1_18_iw_state}, {rob_uop_1_17_iw_state}, {rob_uop_1_16_iw_state}, {rob_uop_1_15_iw_state}, {rob_uop_1_14_iw_state}, {rob_uop_1_13_iw_state}, {rob_uop_1_12_iw_state}, {rob_uop_1_11_iw_state}, {rob_uop_1_10_iw_state}, {rob_uop_1_9_iw_state}, {rob_uop_1_8_iw_state}, {rob_uop_1_7_iw_state}, {rob_uop_1_6_iw_state}, {rob_uop_1_5_iw_state}, {rob_uop_1_4_iw_state}, {rob_uop_1_3_iw_state}, {rob_uop_1_2_iw_state}, {rob_uop_1_1_iw_state}, {rob_uop_1_0_iw_state}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_iw_state_0 = _GEN_118[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_119 = {{rob_uop_1_31_iw_p1_poisoned}, {rob_uop_1_30_iw_p1_poisoned}, {rob_uop_1_29_iw_p1_poisoned}, {rob_uop_1_28_iw_p1_poisoned}, {rob_uop_1_27_iw_p1_poisoned}, {rob_uop_1_26_iw_p1_poisoned}, {rob_uop_1_25_iw_p1_poisoned}, {rob_uop_1_24_iw_p1_poisoned}, {rob_uop_1_23_iw_p1_poisoned}, {rob_uop_1_22_iw_p1_poisoned}, {rob_uop_1_21_iw_p1_poisoned}, {rob_uop_1_20_iw_p1_poisoned}, {rob_uop_1_19_iw_p1_poisoned}, {rob_uop_1_18_iw_p1_poisoned}, {rob_uop_1_17_iw_p1_poisoned}, {rob_uop_1_16_iw_p1_poisoned}, {rob_uop_1_15_iw_p1_poisoned}, {rob_uop_1_14_iw_p1_poisoned}, {rob_uop_1_13_iw_p1_poisoned}, {rob_uop_1_12_iw_p1_poisoned}, {rob_uop_1_11_iw_p1_poisoned}, {rob_uop_1_10_iw_p1_poisoned}, {rob_uop_1_9_iw_p1_poisoned}, {rob_uop_1_8_iw_p1_poisoned}, {rob_uop_1_7_iw_p1_poisoned}, {rob_uop_1_6_iw_p1_poisoned}, {rob_uop_1_5_iw_p1_poisoned}, {rob_uop_1_4_iw_p1_poisoned}, {rob_uop_1_3_iw_p1_poisoned}, {rob_uop_1_2_iw_p1_poisoned}, {rob_uop_1_1_iw_p1_poisoned}, {rob_uop_1_0_iw_p1_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_iw_p1_poisoned_0 = _GEN_119[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_120 = {{rob_uop_1_31_iw_p2_poisoned}, {rob_uop_1_30_iw_p2_poisoned}, {rob_uop_1_29_iw_p2_poisoned}, {rob_uop_1_28_iw_p2_poisoned}, {rob_uop_1_27_iw_p2_poisoned}, {rob_uop_1_26_iw_p2_poisoned}, {rob_uop_1_25_iw_p2_poisoned}, {rob_uop_1_24_iw_p2_poisoned}, {rob_uop_1_23_iw_p2_poisoned}, {rob_uop_1_22_iw_p2_poisoned}, {rob_uop_1_21_iw_p2_poisoned}, {rob_uop_1_20_iw_p2_poisoned}, {rob_uop_1_19_iw_p2_poisoned}, {rob_uop_1_18_iw_p2_poisoned}, {rob_uop_1_17_iw_p2_poisoned}, {rob_uop_1_16_iw_p2_poisoned}, {rob_uop_1_15_iw_p2_poisoned}, {rob_uop_1_14_iw_p2_poisoned}, {rob_uop_1_13_iw_p2_poisoned}, {rob_uop_1_12_iw_p2_poisoned}, {rob_uop_1_11_iw_p2_poisoned}, {rob_uop_1_10_iw_p2_poisoned}, {rob_uop_1_9_iw_p2_poisoned}, {rob_uop_1_8_iw_p2_poisoned}, {rob_uop_1_7_iw_p2_poisoned}, {rob_uop_1_6_iw_p2_poisoned}, {rob_uop_1_5_iw_p2_poisoned}, {rob_uop_1_4_iw_p2_poisoned}, {rob_uop_1_3_iw_p2_poisoned}, {rob_uop_1_2_iw_p2_poisoned}, {rob_uop_1_1_iw_p2_poisoned}, {rob_uop_1_0_iw_p2_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_iw_p2_poisoned_0 = _GEN_120[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_121 = {{rob_uop_1_31_is_br}, {rob_uop_1_30_is_br}, {rob_uop_1_29_is_br}, {rob_uop_1_28_is_br}, {rob_uop_1_27_is_br}, {rob_uop_1_26_is_br}, {rob_uop_1_25_is_br}, {rob_uop_1_24_is_br}, {rob_uop_1_23_is_br}, {rob_uop_1_22_is_br}, {rob_uop_1_21_is_br}, {rob_uop_1_20_is_br}, {rob_uop_1_19_is_br}, {rob_uop_1_18_is_br}, {rob_uop_1_17_is_br}, {rob_uop_1_16_is_br}, {rob_uop_1_15_is_br}, {rob_uop_1_14_is_br}, {rob_uop_1_13_is_br}, {rob_uop_1_12_is_br}, {rob_uop_1_11_is_br}, {rob_uop_1_10_is_br}, {rob_uop_1_9_is_br}, {rob_uop_1_8_is_br}, {rob_uop_1_7_is_br}, {rob_uop_1_6_is_br}, {rob_uop_1_5_is_br}, {rob_uop_1_4_is_br}, {rob_uop_1_3_is_br}, {rob_uop_1_2_is_br}, {rob_uop_1_1_is_br}, {rob_uop_1_0_is_br}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_br_0 = _GEN_121[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_122 = {{rob_uop_1_31_is_jalr}, {rob_uop_1_30_is_jalr}, {rob_uop_1_29_is_jalr}, {rob_uop_1_28_is_jalr}, {rob_uop_1_27_is_jalr}, {rob_uop_1_26_is_jalr}, {rob_uop_1_25_is_jalr}, {rob_uop_1_24_is_jalr}, {rob_uop_1_23_is_jalr}, {rob_uop_1_22_is_jalr}, {rob_uop_1_21_is_jalr}, {rob_uop_1_20_is_jalr}, {rob_uop_1_19_is_jalr}, {rob_uop_1_18_is_jalr}, {rob_uop_1_17_is_jalr}, {rob_uop_1_16_is_jalr}, {rob_uop_1_15_is_jalr}, {rob_uop_1_14_is_jalr}, {rob_uop_1_13_is_jalr}, {rob_uop_1_12_is_jalr}, {rob_uop_1_11_is_jalr}, {rob_uop_1_10_is_jalr}, {rob_uop_1_9_is_jalr}, {rob_uop_1_8_is_jalr}, {rob_uop_1_7_is_jalr}, {rob_uop_1_6_is_jalr}, {rob_uop_1_5_is_jalr}, {rob_uop_1_4_is_jalr}, {rob_uop_1_3_is_jalr}, {rob_uop_1_2_is_jalr}, {rob_uop_1_1_is_jalr}, {rob_uop_1_0_is_jalr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_jalr_0 = _GEN_122[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_123 = {{rob_uop_1_31_is_jal}, {rob_uop_1_30_is_jal}, {rob_uop_1_29_is_jal}, {rob_uop_1_28_is_jal}, {rob_uop_1_27_is_jal}, {rob_uop_1_26_is_jal}, {rob_uop_1_25_is_jal}, {rob_uop_1_24_is_jal}, {rob_uop_1_23_is_jal}, {rob_uop_1_22_is_jal}, {rob_uop_1_21_is_jal}, {rob_uop_1_20_is_jal}, {rob_uop_1_19_is_jal}, {rob_uop_1_18_is_jal}, {rob_uop_1_17_is_jal}, {rob_uop_1_16_is_jal}, {rob_uop_1_15_is_jal}, {rob_uop_1_14_is_jal}, {rob_uop_1_13_is_jal}, {rob_uop_1_12_is_jal}, {rob_uop_1_11_is_jal}, {rob_uop_1_10_is_jal}, {rob_uop_1_9_is_jal}, {rob_uop_1_8_is_jal}, {rob_uop_1_7_is_jal}, {rob_uop_1_6_is_jal}, {rob_uop_1_5_is_jal}, {rob_uop_1_4_is_jal}, {rob_uop_1_3_is_jal}, {rob_uop_1_2_is_jal}, {rob_uop_1_1_is_jal}, {rob_uop_1_0_is_jal}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_jal_0 = _GEN_123[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_124 = {{rob_uop_1_31_is_sfb}, {rob_uop_1_30_is_sfb}, {rob_uop_1_29_is_sfb}, {rob_uop_1_28_is_sfb}, {rob_uop_1_27_is_sfb}, {rob_uop_1_26_is_sfb}, {rob_uop_1_25_is_sfb}, {rob_uop_1_24_is_sfb}, {rob_uop_1_23_is_sfb}, {rob_uop_1_22_is_sfb}, {rob_uop_1_21_is_sfb}, {rob_uop_1_20_is_sfb}, {rob_uop_1_19_is_sfb}, {rob_uop_1_18_is_sfb}, {rob_uop_1_17_is_sfb}, {rob_uop_1_16_is_sfb}, {rob_uop_1_15_is_sfb}, {rob_uop_1_14_is_sfb}, {rob_uop_1_13_is_sfb}, {rob_uop_1_12_is_sfb}, {rob_uop_1_11_is_sfb}, {rob_uop_1_10_is_sfb}, {rob_uop_1_9_is_sfb}, {rob_uop_1_8_is_sfb}, {rob_uop_1_7_is_sfb}, {rob_uop_1_6_is_sfb}, {rob_uop_1_5_is_sfb}, {rob_uop_1_4_is_sfb}, {rob_uop_1_3_is_sfb}, {rob_uop_1_2_is_sfb}, {rob_uop_1_1_is_sfb}, {rob_uop_1_0_is_sfb}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_sfb_0 = _GEN_124[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][15:0] _GEN_125 = {{rob_uop_1_31_br_mask}, {rob_uop_1_30_br_mask}, {rob_uop_1_29_br_mask}, {rob_uop_1_28_br_mask}, {rob_uop_1_27_br_mask}, {rob_uop_1_26_br_mask}, {rob_uop_1_25_br_mask}, {rob_uop_1_24_br_mask}, {rob_uop_1_23_br_mask}, {rob_uop_1_22_br_mask}, {rob_uop_1_21_br_mask}, {rob_uop_1_20_br_mask}, {rob_uop_1_19_br_mask}, {rob_uop_1_18_br_mask}, {rob_uop_1_17_br_mask}, {rob_uop_1_16_br_mask}, {rob_uop_1_15_br_mask}, {rob_uop_1_14_br_mask}, {rob_uop_1_13_br_mask}, {rob_uop_1_12_br_mask}, {rob_uop_1_11_br_mask}, {rob_uop_1_10_br_mask}, {rob_uop_1_9_br_mask}, {rob_uop_1_8_br_mask}, {rob_uop_1_7_br_mask}, {rob_uop_1_6_br_mask}, {rob_uop_1_5_br_mask}, {rob_uop_1_4_br_mask}, {rob_uop_1_3_br_mask}, {rob_uop_1_2_br_mask}, {rob_uop_1_1_br_mask}, {rob_uop_1_0_br_mask}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_br_mask_0 = _GEN_125[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_126 = {{rob_uop_1_31_br_tag}, {rob_uop_1_30_br_tag}, {rob_uop_1_29_br_tag}, {rob_uop_1_28_br_tag}, {rob_uop_1_27_br_tag}, {rob_uop_1_26_br_tag}, {rob_uop_1_25_br_tag}, {rob_uop_1_24_br_tag}, {rob_uop_1_23_br_tag}, {rob_uop_1_22_br_tag}, {rob_uop_1_21_br_tag}, {rob_uop_1_20_br_tag}, {rob_uop_1_19_br_tag}, {rob_uop_1_18_br_tag}, {rob_uop_1_17_br_tag}, {rob_uop_1_16_br_tag}, {rob_uop_1_15_br_tag}, {rob_uop_1_14_br_tag}, {rob_uop_1_13_br_tag}, {rob_uop_1_12_br_tag}, {rob_uop_1_11_br_tag}, {rob_uop_1_10_br_tag}, {rob_uop_1_9_br_tag}, {rob_uop_1_8_br_tag}, {rob_uop_1_7_br_tag}, {rob_uop_1_6_br_tag}, {rob_uop_1_5_br_tag}, {rob_uop_1_4_br_tag}, {rob_uop_1_3_br_tag}, {rob_uop_1_2_br_tag}, {rob_uop_1_1_br_tag}, {rob_uop_1_0_br_tag}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_br_tag_0 = _GEN_126[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_127 = {{rob_uop_1_31_ftq_idx}, {rob_uop_1_30_ftq_idx}, {rob_uop_1_29_ftq_idx}, {rob_uop_1_28_ftq_idx}, {rob_uop_1_27_ftq_idx}, {rob_uop_1_26_ftq_idx}, {rob_uop_1_25_ftq_idx}, {rob_uop_1_24_ftq_idx}, {rob_uop_1_23_ftq_idx}, {rob_uop_1_22_ftq_idx}, {rob_uop_1_21_ftq_idx}, {rob_uop_1_20_ftq_idx}, {rob_uop_1_19_ftq_idx}, {rob_uop_1_18_ftq_idx}, {rob_uop_1_17_ftq_idx}, {rob_uop_1_16_ftq_idx}, {rob_uop_1_15_ftq_idx}, {rob_uop_1_14_ftq_idx}, {rob_uop_1_13_ftq_idx}, {rob_uop_1_12_ftq_idx}, {rob_uop_1_11_ftq_idx}, {rob_uop_1_10_ftq_idx}, {rob_uop_1_9_ftq_idx}, {rob_uop_1_8_ftq_idx}, {rob_uop_1_7_ftq_idx}, {rob_uop_1_6_ftq_idx}, {rob_uop_1_5_ftq_idx}, {rob_uop_1_4_ftq_idx}, {rob_uop_1_3_ftq_idx}, {rob_uop_1_2_ftq_idx}, {rob_uop_1_1_ftq_idx}, {rob_uop_1_0_ftq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ftq_idx_0 = _GEN_127[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_128 = {{rob_uop_1_31_edge_inst}, {rob_uop_1_30_edge_inst}, {rob_uop_1_29_edge_inst}, {rob_uop_1_28_edge_inst}, {rob_uop_1_27_edge_inst}, {rob_uop_1_26_edge_inst}, {rob_uop_1_25_edge_inst}, {rob_uop_1_24_edge_inst}, {rob_uop_1_23_edge_inst}, {rob_uop_1_22_edge_inst}, {rob_uop_1_21_edge_inst}, {rob_uop_1_20_edge_inst}, {rob_uop_1_19_edge_inst}, {rob_uop_1_18_edge_inst}, {rob_uop_1_17_edge_inst}, {rob_uop_1_16_edge_inst}, {rob_uop_1_15_edge_inst}, {rob_uop_1_14_edge_inst}, {rob_uop_1_13_edge_inst}, {rob_uop_1_12_edge_inst}, {rob_uop_1_11_edge_inst}, {rob_uop_1_10_edge_inst}, {rob_uop_1_9_edge_inst}, {rob_uop_1_8_edge_inst}, {rob_uop_1_7_edge_inst}, {rob_uop_1_6_edge_inst}, {rob_uop_1_5_edge_inst}, {rob_uop_1_4_edge_inst}, {rob_uop_1_3_edge_inst}, {rob_uop_1_2_edge_inst}, {rob_uop_1_1_edge_inst}, {rob_uop_1_0_edge_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_edge_inst_0 = _GEN_128[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_129 = {{rob_uop_1_31_pc_lob}, {rob_uop_1_30_pc_lob}, {rob_uop_1_29_pc_lob}, {rob_uop_1_28_pc_lob}, {rob_uop_1_27_pc_lob}, {rob_uop_1_26_pc_lob}, {rob_uop_1_25_pc_lob}, {rob_uop_1_24_pc_lob}, {rob_uop_1_23_pc_lob}, {rob_uop_1_22_pc_lob}, {rob_uop_1_21_pc_lob}, {rob_uop_1_20_pc_lob}, {rob_uop_1_19_pc_lob}, {rob_uop_1_18_pc_lob}, {rob_uop_1_17_pc_lob}, {rob_uop_1_16_pc_lob}, {rob_uop_1_15_pc_lob}, {rob_uop_1_14_pc_lob}, {rob_uop_1_13_pc_lob}, {rob_uop_1_12_pc_lob}, {rob_uop_1_11_pc_lob}, {rob_uop_1_10_pc_lob}, {rob_uop_1_9_pc_lob}, {rob_uop_1_8_pc_lob}, {rob_uop_1_7_pc_lob}, {rob_uop_1_6_pc_lob}, {rob_uop_1_5_pc_lob}, {rob_uop_1_4_pc_lob}, {rob_uop_1_3_pc_lob}, {rob_uop_1_2_pc_lob}, {rob_uop_1_1_pc_lob}, {rob_uop_1_0_pc_lob}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_pc_lob_0 = _GEN_129[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_130 = {{rob_uop_1_31_taken}, {rob_uop_1_30_taken}, {rob_uop_1_29_taken}, {rob_uop_1_28_taken}, {rob_uop_1_27_taken}, {rob_uop_1_26_taken}, {rob_uop_1_25_taken}, {rob_uop_1_24_taken}, {rob_uop_1_23_taken}, {rob_uop_1_22_taken}, {rob_uop_1_21_taken}, {rob_uop_1_20_taken}, {rob_uop_1_19_taken}, {rob_uop_1_18_taken}, {rob_uop_1_17_taken}, {rob_uop_1_16_taken}, {rob_uop_1_15_taken}, {rob_uop_1_14_taken}, {rob_uop_1_13_taken}, {rob_uop_1_12_taken}, {rob_uop_1_11_taken}, {rob_uop_1_10_taken}, {rob_uop_1_9_taken}, {rob_uop_1_8_taken}, {rob_uop_1_7_taken}, {rob_uop_1_6_taken}, {rob_uop_1_5_taken}, {rob_uop_1_4_taken}, {rob_uop_1_3_taken}, {rob_uop_1_2_taken}, {rob_uop_1_1_taken}, {rob_uop_1_0_taken}}; // @[rob.scala:311:28, :415:25]
wire [31:0][19:0] _GEN_131 = {{rob_uop_1_31_imm_packed}, {rob_uop_1_30_imm_packed}, {rob_uop_1_29_imm_packed}, {rob_uop_1_28_imm_packed}, {rob_uop_1_27_imm_packed}, {rob_uop_1_26_imm_packed}, {rob_uop_1_25_imm_packed}, {rob_uop_1_24_imm_packed}, {rob_uop_1_23_imm_packed}, {rob_uop_1_22_imm_packed}, {rob_uop_1_21_imm_packed}, {rob_uop_1_20_imm_packed}, {rob_uop_1_19_imm_packed}, {rob_uop_1_18_imm_packed}, {rob_uop_1_17_imm_packed}, {rob_uop_1_16_imm_packed}, {rob_uop_1_15_imm_packed}, {rob_uop_1_14_imm_packed}, {rob_uop_1_13_imm_packed}, {rob_uop_1_12_imm_packed}, {rob_uop_1_11_imm_packed}, {rob_uop_1_10_imm_packed}, {rob_uop_1_9_imm_packed}, {rob_uop_1_8_imm_packed}, {rob_uop_1_7_imm_packed}, {rob_uop_1_6_imm_packed}, {rob_uop_1_5_imm_packed}, {rob_uop_1_4_imm_packed}, {rob_uop_1_3_imm_packed}, {rob_uop_1_2_imm_packed}, {rob_uop_1_1_imm_packed}, {rob_uop_1_0_imm_packed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_imm_packed_0 = _GEN_131[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][11:0] _GEN_132 = {{rob_uop_1_31_csr_addr}, {rob_uop_1_30_csr_addr}, {rob_uop_1_29_csr_addr}, {rob_uop_1_28_csr_addr}, {rob_uop_1_27_csr_addr}, {rob_uop_1_26_csr_addr}, {rob_uop_1_25_csr_addr}, {rob_uop_1_24_csr_addr}, {rob_uop_1_23_csr_addr}, {rob_uop_1_22_csr_addr}, {rob_uop_1_21_csr_addr}, {rob_uop_1_20_csr_addr}, {rob_uop_1_19_csr_addr}, {rob_uop_1_18_csr_addr}, {rob_uop_1_17_csr_addr}, {rob_uop_1_16_csr_addr}, {rob_uop_1_15_csr_addr}, {rob_uop_1_14_csr_addr}, {rob_uop_1_13_csr_addr}, {rob_uop_1_12_csr_addr}, {rob_uop_1_11_csr_addr}, {rob_uop_1_10_csr_addr}, {rob_uop_1_9_csr_addr}, {rob_uop_1_8_csr_addr}, {rob_uop_1_7_csr_addr}, {rob_uop_1_6_csr_addr}, {rob_uop_1_5_csr_addr}, {rob_uop_1_4_csr_addr}, {rob_uop_1_3_csr_addr}, {rob_uop_1_2_csr_addr}, {rob_uop_1_1_csr_addr}, {rob_uop_1_0_csr_addr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_csr_addr_0 = _GEN_132[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_133 = {{rob_uop_1_31_rob_idx}, {rob_uop_1_30_rob_idx}, {rob_uop_1_29_rob_idx}, {rob_uop_1_28_rob_idx}, {rob_uop_1_27_rob_idx}, {rob_uop_1_26_rob_idx}, {rob_uop_1_25_rob_idx}, {rob_uop_1_24_rob_idx}, {rob_uop_1_23_rob_idx}, {rob_uop_1_22_rob_idx}, {rob_uop_1_21_rob_idx}, {rob_uop_1_20_rob_idx}, {rob_uop_1_19_rob_idx}, {rob_uop_1_18_rob_idx}, {rob_uop_1_17_rob_idx}, {rob_uop_1_16_rob_idx}, {rob_uop_1_15_rob_idx}, {rob_uop_1_14_rob_idx}, {rob_uop_1_13_rob_idx}, {rob_uop_1_12_rob_idx}, {rob_uop_1_11_rob_idx}, {rob_uop_1_10_rob_idx}, {rob_uop_1_9_rob_idx}, {rob_uop_1_8_rob_idx}, {rob_uop_1_7_rob_idx}, {rob_uop_1_6_rob_idx}, {rob_uop_1_5_rob_idx}, {rob_uop_1_4_rob_idx}, {rob_uop_1_3_rob_idx}, {rob_uop_1_2_rob_idx}, {rob_uop_1_1_rob_idx}, {rob_uop_1_0_rob_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_rob_idx_0 = _GEN_133[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_134 = {{rob_uop_1_31_ldq_idx}, {rob_uop_1_30_ldq_idx}, {rob_uop_1_29_ldq_idx}, {rob_uop_1_28_ldq_idx}, {rob_uop_1_27_ldq_idx}, {rob_uop_1_26_ldq_idx}, {rob_uop_1_25_ldq_idx}, {rob_uop_1_24_ldq_idx}, {rob_uop_1_23_ldq_idx}, {rob_uop_1_22_ldq_idx}, {rob_uop_1_21_ldq_idx}, {rob_uop_1_20_ldq_idx}, {rob_uop_1_19_ldq_idx}, {rob_uop_1_18_ldq_idx}, {rob_uop_1_17_ldq_idx}, {rob_uop_1_16_ldq_idx}, {rob_uop_1_15_ldq_idx}, {rob_uop_1_14_ldq_idx}, {rob_uop_1_13_ldq_idx}, {rob_uop_1_12_ldq_idx}, {rob_uop_1_11_ldq_idx}, {rob_uop_1_10_ldq_idx}, {rob_uop_1_9_ldq_idx}, {rob_uop_1_8_ldq_idx}, {rob_uop_1_7_ldq_idx}, {rob_uop_1_6_ldq_idx}, {rob_uop_1_5_ldq_idx}, {rob_uop_1_4_ldq_idx}, {rob_uop_1_3_ldq_idx}, {rob_uop_1_2_ldq_idx}, {rob_uop_1_1_ldq_idx}, {rob_uop_1_0_ldq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ldq_idx_0 = _GEN_134[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_135 = {{rob_uop_1_31_stq_idx}, {rob_uop_1_30_stq_idx}, {rob_uop_1_29_stq_idx}, {rob_uop_1_28_stq_idx}, {rob_uop_1_27_stq_idx}, {rob_uop_1_26_stq_idx}, {rob_uop_1_25_stq_idx}, {rob_uop_1_24_stq_idx}, {rob_uop_1_23_stq_idx}, {rob_uop_1_22_stq_idx}, {rob_uop_1_21_stq_idx}, {rob_uop_1_20_stq_idx}, {rob_uop_1_19_stq_idx}, {rob_uop_1_18_stq_idx}, {rob_uop_1_17_stq_idx}, {rob_uop_1_16_stq_idx}, {rob_uop_1_15_stq_idx}, {rob_uop_1_14_stq_idx}, {rob_uop_1_13_stq_idx}, {rob_uop_1_12_stq_idx}, {rob_uop_1_11_stq_idx}, {rob_uop_1_10_stq_idx}, {rob_uop_1_9_stq_idx}, {rob_uop_1_8_stq_idx}, {rob_uop_1_7_stq_idx}, {rob_uop_1_6_stq_idx}, {rob_uop_1_5_stq_idx}, {rob_uop_1_4_stq_idx}, {rob_uop_1_3_stq_idx}, {rob_uop_1_2_stq_idx}, {rob_uop_1_1_stq_idx}, {rob_uop_1_0_stq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_stq_idx_0 = _GEN_135[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_136 = {{rob_uop_1_31_rxq_idx}, {rob_uop_1_30_rxq_idx}, {rob_uop_1_29_rxq_idx}, {rob_uop_1_28_rxq_idx}, {rob_uop_1_27_rxq_idx}, {rob_uop_1_26_rxq_idx}, {rob_uop_1_25_rxq_idx}, {rob_uop_1_24_rxq_idx}, {rob_uop_1_23_rxq_idx}, {rob_uop_1_22_rxq_idx}, {rob_uop_1_21_rxq_idx}, {rob_uop_1_20_rxq_idx}, {rob_uop_1_19_rxq_idx}, {rob_uop_1_18_rxq_idx}, {rob_uop_1_17_rxq_idx}, {rob_uop_1_16_rxq_idx}, {rob_uop_1_15_rxq_idx}, {rob_uop_1_14_rxq_idx}, {rob_uop_1_13_rxq_idx}, {rob_uop_1_12_rxq_idx}, {rob_uop_1_11_rxq_idx}, {rob_uop_1_10_rxq_idx}, {rob_uop_1_9_rxq_idx}, {rob_uop_1_8_rxq_idx}, {rob_uop_1_7_rxq_idx}, {rob_uop_1_6_rxq_idx}, {rob_uop_1_5_rxq_idx}, {rob_uop_1_4_rxq_idx}, {rob_uop_1_3_rxq_idx}, {rob_uop_1_2_rxq_idx}, {rob_uop_1_1_rxq_idx}, {rob_uop_1_0_rxq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_rxq_idx_0 = _GEN_136[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_137 = {{rob_uop_1_31_pdst}, {rob_uop_1_30_pdst}, {rob_uop_1_29_pdst}, {rob_uop_1_28_pdst}, {rob_uop_1_27_pdst}, {rob_uop_1_26_pdst}, {rob_uop_1_25_pdst}, {rob_uop_1_24_pdst}, {rob_uop_1_23_pdst}, {rob_uop_1_22_pdst}, {rob_uop_1_21_pdst}, {rob_uop_1_20_pdst}, {rob_uop_1_19_pdst}, {rob_uop_1_18_pdst}, {rob_uop_1_17_pdst}, {rob_uop_1_16_pdst}, {rob_uop_1_15_pdst}, {rob_uop_1_14_pdst}, {rob_uop_1_13_pdst}, {rob_uop_1_12_pdst}, {rob_uop_1_11_pdst}, {rob_uop_1_10_pdst}, {rob_uop_1_9_pdst}, {rob_uop_1_8_pdst}, {rob_uop_1_7_pdst}, {rob_uop_1_6_pdst}, {rob_uop_1_5_pdst}, {rob_uop_1_4_pdst}, {rob_uop_1_3_pdst}, {rob_uop_1_2_pdst}, {rob_uop_1_1_pdst}, {rob_uop_1_0_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_pdst_0 = _GEN_137[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_138 = {{rob_uop_1_31_prs1}, {rob_uop_1_30_prs1}, {rob_uop_1_29_prs1}, {rob_uop_1_28_prs1}, {rob_uop_1_27_prs1}, {rob_uop_1_26_prs1}, {rob_uop_1_25_prs1}, {rob_uop_1_24_prs1}, {rob_uop_1_23_prs1}, {rob_uop_1_22_prs1}, {rob_uop_1_21_prs1}, {rob_uop_1_20_prs1}, {rob_uop_1_19_prs1}, {rob_uop_1_18_prs1}, {rob_uop_1_17_prs1}, {rob_uop_1_16_prs1}, {rob_uop_1_15_prs1}, {rob_uop_1_14_prs1}, {rob_uop_1_13_prs1}, {rob_uop_1_12_prs1}, {rob_uop_1_11_prs1}, {rob_uop_1_10_prs1}, {rob_uop_1_9_prs1}, {rob_uop_1_8_prs1}, {rob_uop_1_7_prs1}, {rob_uop_1_6_prs1}, {rob_uop_1_5_prs1}, {rob_uop_1_4_prs1}, {rob_uop_1_3_prs1}, {rob_uop_1_2_prs1}, {rob_uop_1_1_prs1}, {rob_uop_1_0_prs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs1_0 = _GEN_138[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_139 = {{rob_uop_1_31_prs2}, {rob_uop_1_30_prs2}, {rob_uop_1_29_prs2}, {rob_uop_1_28_prs2}, {rob_uop_1_27_prs2}, {rob_uop_1_26_prs2}, {rob_uop_1_25_prs2}, {rob_uop_1_24_prs2}, {rob_uop_1_23_prs2}, {rob_uop_1_22_prs2}, {rob_uop_1_21_prs2}, {rob_uop_1_20_prs2}, {rob_uop_1_19_prs2}, {rob_uop_1_18_prs2}, {rob_uop_1_17_prs2}, {rob_uop_1_16_prs2}, {rob_uop_1_15_prs2}, {rob_uop_1_14_prs2}, {rob_uop_1_13_prs2}, {rob_uop_1_12_prs2}, {rob_uop_1_11_prs2}, {rob_uop_1_10_prs2}, {rob_uop_1_9_prs2}, {rob_uop_1_8_prs2}, {rob_uop_1_7_prs2}, {rob_uop_1_6_prs2}, {rob_uop_1_5_prs2}, {rob_uop_1_4_prs2}, {rob_uop_1_3_prs2}, {rob_uop_1_2_prs2}, {rob_uop_1_1_prs2}, {rob_uop_1_0_prs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs2_0 = _GEN_139[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_140 = {{rob_uop_1_31_prs3}, {rob_uop_1_30_prs3}, {rob_uop_1_29_prs3}, {rob_uop_1_28_prs3}, {rob_uop_1_27_prs3}, {rob_uop_1_26_prs3}, {rob_uop_1_25_prs3}, {rob_uop_1_24_prs3}, {rob_uop_1_23_prs3}, {rob_uop_1_22_prs3}, {rob_uop_1_21_prs3}, {rob_uop_1_20_prs3}, {rob_uop_1_19_prs3}, {rob_uop_1_18_prs3}, {rob_uop_1_17_prs3}, {rob_uop_1_16_prs3}, {rob_uop_1_15_prs3}, {rob_uop_1_14_prs3}, {rob_uop_1_13_prs3}, {rob_uop_1_12_prs3}, {rob_uop_1_11_prs3}, {rob_uop_1_10_prs3}, {rob_uop_1_9_prs3}, {rob_uop_1_8_prs3}, {rob_uop_1_7_prs3}, {rob_uop_1_6_prs3}, {rob_uop_1_5_prs3}, {rob_uop_1_4_prs3}, {rob_uop_1_3_prs3}, {rob_uop_1_2_prs3}, {rob_uop_1_1_prs3}, {rob_uop_1_0_prs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs3_0 = _GEN_140[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_141 = {{rob_uop_1_31_prs1_busy}, {rob_uop_1_30_prs1_busy}, {rob_uop_1_29_prs1_busy}, {rob_uop_1_28_prs1_busy}, {rob_uop_1_27_prs1_busy}, {rob_uop_1_26_prs1_busy}, {rob_uop_1_25_prs1_busy}, {rob_uop_1_24_prs1_busy}, {rob_uop_1_23_prs1_busy}, {rob_uop_1_22_prs1_busy}, {rob_uop_1_21_prs1_busy}, {rob_uop_1_20_prs1_busy}, {rob_uop_1_19_prs1_busy}, {rob_uop_1_18_prs1_busy}, {rob_uop_1_17_prs1_busy}, {rob_uop_1_16_prs1_busy}, {rob_uop_1_15_prs1_busy}, {rob_uop_1_14_prs1_busy}, {rob_uop_1_13_prs1_busy}, {rob_uop_1_12_prs1_busy}, {rob_uop_1_11_prs1_busy}, {rob_uop_1_10_prs1_busy}, {rob_uop_1_9_prs1_busy}, {rob_uop_1_8_prs1_busy}, {rob_uop_1_7_prs1_busy}, {rob_uop_1_6_prs1_busy}, {rob_uop_1_5_prs1_busy}, {rob_uop_1_4_prs1_busy}, {rob_uop_1_3_prs1_busy}, {rob_uop_1_2_prs1_busy}, {rob_uop_1_1_prs1_busy}, {rob_uop_1_0_prs1_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs1_busy_0 = _GEN_141[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_142 = {{rob_uop_1_31_prs2_busy}, {rob_uop_1_30_prs2_busy}, {rob_uop_1_29_prs2_busy}, {rob_uop_1_28_prs2_busy}, {rob_uop_1_27_prs2_busy}, {rob_uop_1_26_prs2_busy}, {rob_uop_1_25_prs2_busy}, {rob_uop_1_24_prs2_busy}, {rob_uop_1_23_prs2_busy}, {rob_uop_1_22_prs2_busy}, {rob_uop_1_21_prs2_busy}, {rob_uop_1_20_prs2_busy}, {rob_uop_1_19_prs2_busy}, {rob_uop_1_18_prs2_busy}, {rob_uop_1_17_prs2_busy}, {rob_uop_1_16_prs2_busy}, {rob_uop_1_15_prs2_busy}, {rob_uop_1_14_prs2_busy}, {rob_uop_1_13_prs2_busy}, {rob_uop_1_12_prs2_busy}, {rob_uop_1_11_prs2_busy}, {rob_uop_1_10_prs2_busy}, {rob_uop_1_9_prs2_busy}, {rob_uop_1_8_prs2_busy}, {rob_uop_1_7_prs2_busy}, {rob_uop_1_6_prs2_busy}, {rob_uop_1_5_prs2_busy}, {rob_uop_1_4_prs2_busy}, {rob_uop_1_3_prs2_busy}, {rob_uop_1_2_prs2_busy}, {rob_uop_1_1_prs2_busy}, {rob_uop_1_0_prs2_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs2_busy_0 = _GEN_142[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_143 = {{rob_uop_1_31_prs3_busy}, {rob_uop_1_30_prs3_busy}, {rob_uop_1_29_prs3_busy}, {rob_uop_1_28_prs3_busy}, {rob_uop_1_27_prs3_busy}, {rob_uop_1_26_prs3_busy}, {rob_uop_1_25_prs3_busy}, {rob_uop_1_24_prs3_busy}, {rob_uop_1_23_prs3_busy}, {rob_uop_1_22_prs3_busy}, {rob_uop_1_21_prs3_busy}, {rob_uop_1_20_prs3_busy}, {rob_uop_1_19_prs3_busy}, {rob_uop_1_18_prs3_busy}, {rob_uop_1_17_prs3_busy}, {rob_uop_1_16_prs3_busy}, {rob_uop_1_15_prs3_busy}, {rob_uop_1_14_prs3_busy}, {rob_uop_1_13_prs3_busy}, {rob_uop_1_12_prs3_busy}, {rob_uop_1_11_prs3_busy}, {rob_uop_1_10_prs3_busy}, {rob_uop_1_9_prs3_busy}, {rob_uop_1_8_prs3_busy}, {rob_uop_1_7_prs3_busy}, {rob_uop_1_6_prs3_busy}, {rob_uop_1_5_prs3_busy}, {rob_uop_1_4_prs3_busy}, {rob_uop_1_3_prs3_busy}, {rob_uop_1_2_prs3_busy}, {rob_uop_1_1_prs3_busy}, {rob_uop_1_0_prs3_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_prs3_busy_0 = _GEN_143[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_144 = {{rob_uop_1_31_stale_pdst}, {rob_uop_1_30_stale_pdst}, {rob_uop_1_29_stale_pdst}, {rob_uop_1_28_stale_pdst}, {rob_uop_1_27_stale_pdst}, {rob_uop_1_26_stale_pdst}, {rob_uop_1_25_stale_pdst}, {rob_uop_1_24_stale_pdst}, {rob_uop_1_23_stale_pdst}, {rob_uop_1_22_stale_pdst}, {rob_uop_1_21_stale_pdst}, {rob_uop_1_20_stale_pdst}, {rob_uop_1_19_stale_pdst}, {rob_uop_1_18_stale_pdst}, {rob_uop_1_17_stale_pdst}, {rob_uop_1_16_stale_pdst}, {rob_uop_1_15_stale_pdst}, {rob_uop_1_14_stale_pdst}, {rob_uop_1_13_stale_pdst}, {rob_uop_1_12_stale_pdst}, {rob_uop_1_11_stale_pdst}, {rob_uop_1_10_stale_pdst}, {rob_uop_1_9_stale_pdst}, {rob_uop_1_8_stale_pdst}, {rob_uop_1_7_stale_pdst}, {rob_uop_1_6_stale_pdst}, {rob_uop_1_5_stale_pdst}, {rob_uop_1_4_stale_pdst}, {rob_uop_1_3_stale_pdst}, {rob_uop_1_2_stale_pdst}, {rob_uop_1_1_stale_pdst}, {rob_uop_1_0_stale_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_stale_pdst_0 = _GEN_144[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_145 = {{rob_uop_1_31_exception}, {rob_uop_1_30_exception}, {rob_uop_1_29_exception}, {rob_uop_1_28_exception}, {rob_uop_1_27_exception}, {rob_uop_1_26_exception}, {rob_uop_1_25_exception}, {rob_uop_1_24_exception}, {rob_uop_1_23_exception}, {rob_uop_1_22_exception}, {rob_uop_1_21_exception}, {rob_uop_1_20_exception}, {rob_uop_1_19_exception}, {rob_uop_1_18_exception}, {rob_uop_1_17_exception}, {rob_uop_1_16_exception}, {rob_uop_1_15_exception}, {rob_uop_1_14_exception}, {rob_uop_1_13_exception}, {rob_uop_1_12_exception}, {rob_uop_1_11_exception}, {rob_uop_1_10_exception}, {rob_uop_1_9_exception}, {rob_uop_1_8_exception}, {rob_uop_1_7_exception}, {rob_uop_1_6_exception}, {rob_uop_1_5_exception}, {rob_uop_1_4_exception}, {rob_uop_1_3_exception}, {rob_uop_1_2_exception}, {rob_uop_1_1_exception}, {rob_uop_1_0_exception}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_exception_0 = _GEN_145[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][63:0] _GEN_146 = {{rob_uop_1_31_exc_cause}, {rob_uop_1_30_exc_cause}, {rob_uop_1_29_exc_cause}, {rob_uop_1_28_exc_cause}, {rob_uop_1_27_exc_cause}, {rob_uop_1_26_exc_cause}, {rob_uop_1_25_exc_cause}, {rob_uop_1_24_exc_cause}, {rob_uop_1_23_exc_cause}, {rob_uop_1_22_exc_cause}, {rob_uop_1_21_exc_cause}, {rob_uop_1_20_exc_cause}, {rob_uop_1_19_exc_cause}, {rob_uop_1_18_exc_cause}, {rob_uop_1_17_exc_cause}, {rob_uop_1_16_exc_cause}, {rob_uop_1_15_exc_cause}, {rob_uop_1_14_exc_cause}, {rob_uop_1_13_exc_cause}, {rob_uop_1_12_exc_cause}, {rob_uop_1_11_exc_cause}, {rob_uop_1_10_exc_cause}, {rob_uop_1_9_exc_cause}, {rob_uop_1_8_exc_cause}, {rob_uop_1_7_exc_cause}, {rob_uop_1_6_exc_cause}, {rob_uop_1_5_exc_cause}, {rob_uop_1_4_exc_cause}, {rob_uop_1_3_exc_cause}, {rob_uop_1_2_exc_cause}, {rob_uop_1_1_exc_cause}, {rob_uop_1_0_exc_cause}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_exc_cause_0 = _GEN_146[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_147 = {{rob_uop_1_31_bypassable}, {rob_uop_1_30_bypassable}, {rob_uop_1_29_bypassable}, {rob_uop_1_28_bypassable}, {rob_uop_1_27_bypassable}, {rob_uop_1_26_bypassable}, {rob_uop_1_25_bypassable}, {rob_uop_1_24_bypassable}, {rob_uop_1_23_bypassable}, {rob_uop_1_22_bypassable}, {rob_uop_1_21_bypassable}, {rob_uop_1_20_bypassable}, {rob_uop_1_19_bypassable}, {rob_uop_1_18_bypassable}, {rob_uop_1_17_bypassable}, {rob_uop_1_16_bypassable}, {rob_uop_1_15_bypassable}, {rob_uop_1_14_bypassable}, {rob_uop_1_13_bypassable}, {rob_uop_1_12_bypassable}, {rob_uop_1_11_bypassable}, {rob_uop_1_10_bypassable}, {rob_uop_1_9_bypassable}, {rob_uop_1_8_bypassable}, {rob_uop_1_7_bypassable}, {rob_uop_1_6_bypassable}, {rob_uop_1_5_bypassable}, {rob_uop_1_4_bypassable}, {rob_uop_1_3_bypassable}, {rob_uop_1_2_bypassable}, {rob_uop_1_1_bypassable}, {rob_uop_1_0_bypassable}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_bypassable_0 = _GEN_147[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_148 = {{rob_uop_1_31_mem_cmd}, {rob_uop_1_30_mem_cmd}, {rob_uop_1_29_mem_cmd}, {rob_uop_1_28_mem_cmd}, {rob_uop_1_27_mem_cmd}, {rob_uop_1_26_mem_cmd}, {rob_uop_1_25_mem_cmd}, {rob_uop_1_24_mem_cmd}, {rob_uop_1_23_mem_cmd}, {rob_uop_1_22_mem_cmd}, {rob_uop_1_21_mem_cmd}, {rob_uop_1_20_mem_cmd}, {rob_uop_1_19_mem_cmd}, {rob_uop_1_18_mem_cmd}, {rob_uop_1_17_mem_cmd}, {rob_uop_1_16_mem_cmd}, {rob_uop_1_15_mem_cmd}, {rob_uop_1_14_mem_cmd}, {rob_uop_1_13_mem_cmd}, {rob_uop_1_12_mem_cmd}, {rob_uop_1_11_mem_cmd}, {rob_uop_1_10_mem_cmd}, {rob_uop_1_9_mem_cmd}, {rob_uop_1_8_mem_cmd}, {rob_uop_1_7_mem_cmd}, {rob_uop_1_6_mem_cmd}, {rob_uop_1_5_mem_cmd}, {rob_uop_1_4_mem_cmd}, {rob_uop_1_3_mem_cmd}, {rob_uop_1_2_mem_cmd}, {rob_uop_1_1_mem_cmd}, {rob_uop_1_0_mem_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_mem_cmd_0 = _GEN_148[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_149 = {{rob_uop_1_31_mem_size}, {rob_uop_1_30_mem_size}, {rob_uop_1_29_mem_size}, {rob_uop_1_28_mem_size}, {rob_uop_1_27_mem_size}, {rob_uop_1_26_mem_size}, {rob_uop_1_25_mem_size}, {rob_uop_1_24_mem_size}, {rob_uop_1_23_mem_size}, {rob_uop_1_22_mem_size}, {rob_uop_1_21_mem_size}, {rob_uop_1_20_mem_size}, {rob_uop_1_19_mem_size}, {rob_uop_1_18_mem_size}, {rob_uop_1_17_mem_size}, {rob_uop_1_16_mem_size}, {rob_uop_1_15_mem_size}, {rob_uop_1_14_mem_size}, {rob_uop_1_13_mem_size}, {rob_uop_1_12_mem_size}, {rob_uop_1_11_mem_size}, {rob_uop_1_10_mem_size}, {rob_uop_1_9_mem_size}, {rob_uop_1_8_mem_size}, {rob_uop_1_7_mem_size}, {rob_uop_1_6_mem_size}, {rob_uop_1_5_mem_size}, {rob_uop_1_4_mem_size}, {rob_uop_1_3_mem_size}, {rob_uop_1_2_mem_size}, {rob_uop_1_1_mem_size}, {rob_uop_1_0_mem_size}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_mem_size_0 = _GEN_149[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_150 = {{rob_uop_1_31_mem_signed}, {rob_uop_1_30_mem_signed}, {rob_uop_1_29_mem_signed}, {rob_uop_1_28_mem_signed}, {rob_uop_1_27_mem_signed}, {rob_uop_1_26_mem_signed}, {rob_uop_1_25_mem_signed}, {rob_uop_1_24_mem_signed}, {rob_uop_1_23_mem_signed}, {rob_uop_1_22_mem_signed}, {rob_uop_1_21_mem_signed}, {rob_uop_1_20_mem_signed}, {rob_uop_1_19_mem_signed}, {rob_uop_1_18_mem_signed}, {rob_uop_1_17_mem_signed}, {rob_uop_1_16_mem_signed}, {rob_uop_1_15_mem_signed}, {rob_uop_1_14_mem_signed}, {rob_uop_1_13_mem_signed}, {rob_uop_1_12_mem_signed}, {rob_uop_1_11_mem_signed}, {rob_uop_1_10_mem_signed}, {rob_uop_1_9_mem_signed}, {rob_uop_1_8_mem_signed}, {rob_uop_1_7_mem_signed}, {rob_uop_1_6_mem_signed}, {rob_uop_1_5_mem_signed}, {rob_uop_1_4_mem_signed}, {rob_uop_1_3_mem_signed}, {rob_uop_1_2_mem_signed}, {rob_uop_1_1_mem_signed}, {rob_uop_1_0_mem_signed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_mem_signed_0 = _GEN_150[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_151 = {{rob_uop_1_31_is_fence}, {rob_uop_1_30_is_fence}, {rob_uop_1_29_is_fence}, {rob_uop_1_28_is_fence}, {rob_uop_1_27_is_fence}, {rob_uop_1_26_is_fence}, {rob_uop_1_25_is_fence}, {rob_uop_1_24_is_fence}, {rob_uop_1_23_is_fence}, {rob_uop_1_22_is_fence}, {rob_uop_1_21_is_fence}, {rob_uop_1_20_is_fence}, {rob_uop_1_19_is_fence}, {rob_uop_1_18_is_fence}, {rob_uop_1_17_is_fence}, {rob_uop_1_16_is_fence}, {rob_uop_1_15_is_fence}, {rob_uop_1_14_is_fence}, {rob_uop_1_13_is_fence}, {rob_uop_1_12_is_fence}, {rob_uop_1_11_is_fence}, {rob_uop_1_10_is_fence}, {rob_uop_1_9_is_fence}, {rob_uop_1_8_is_fence}, {rob_uop_1_7_is_fence}, {rob_uop_1_6_is_fence}, {rob_uop_1_5_is_fence}, {rob_uop_1_4_is_fence}, {rob_uop_1_3_is_fence}, {rob_uop_1_2_is_fence}, {rob_uop_1_1_is_fence}, {rob_uop_1_0_is_fence}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_fence_0 = _GEN_151[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_152 = {{rob_uop_1_31_is_fencei}, {rob_uop_1_30_is_fencei}, {rob_uop_1_29_is_fencei}, {rob_uop_1_28_is_fencei}, {rob_uop_1_27_is_fencei}, {rob_uop_1_26_is_fencei}, {rob_uop_1_25_is_fencei}, {rob_uop_1_24_is_fencei}, {rob_uop_1_23_is_fencei}, {rob_uop_1_22_is_fencei}, {rob_uop_1_21_is_fencei}, {rob_uop_1_20_is_fencei}, {rob_uop_1_19_is_fencei}, {rob_uop_1_18_is_fencei}, {rob_uop_1_17_is_fencei}, {rob_uop_1_16_is_fencei}, {rob_uop_1_15_is_fencei}, {rob_uop_1_14_is_fencei}, {rob_uop_1_13_is_fencei}, {rob_uop_1_12_is_fencei}, {rob_uop_1_11_is_fencei}, {rob_uop_1_10_is_fencei}, {rob_uop_1_9_is_fencei}, {rob_uop_1_8_is_fencei}, {rob_uop_1_7_is_fencei}, {rob_uop_1_6_is_fencei}, {rob_uop_1_5_is_fencei}, {rob_uop_1_4_is_fencei}, {rob_uop_1_3_is_fencei}, {rob_uop_1_2_is_fencei}, {rob_uop_1_1_is_fencei}, {rob_uop_1_0_is_fencei}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_fencei_0 = _GEN_152[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_153 = {{rob_uop_1_31_is_amo}, {rob_uop_1_30_is_amo}, {rob_uop_1_29_is_amo}, {rob_uop_1_28_is_amo}, {rob_uop_1_27_is_amo}, {rob_uop_1_26_is_amo}, {rob_uop_1_25_is_amo}, {rob_uop_1_24_is_amo}, {rob_uop_1_23_is_amo}, {rob_uop_1_22_is_amo}, {rob_uop_1_21_is_amo}, {rob_uop_1_20_is_amo}, {rob_uop_1_19_is_amo}, {rob_uop_1_18_is_amo}, {rob_uop_1_17_is_amo}, {rob_uop_1_16_is_amo}, {rob_uop_1_15_is_amo}, {rob_uop_1_14_is_amo}, {rob_uop_1_13_is_amo}, {rob_uop_1_12_is_amo}, {rob_uop_1_11_is_amo}, {rob_uop_1_10_is_amo}, {rob_uop_1_9_is_amo}, {rob_uop_1_8_is_amo}, {rob_uop_1_7_is_amo}, {rob_uop_1_6_is_amo}, {rob_uop_1_5_is_amo}, {rob_uop_1_4_is_amo}, {rob_uop_1_3_is_amo}, {rob_uop_1_2_is_amo}, {rob_uop_1_1_is_amo}, {rob_uop_1_0_is_amo}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_amo_0 = _GEN_153[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_154 = {{rob_uop_1_31_uses_ldq}, {rob_uop_1_30_uses_ldq}, {rob_uop_1_29_uses_ldq}, {rob_uop_1_28_uses_ldq}, {rob_uop_1_27_uses_ldq}, {rob_uop_1_26_uses_ldq}, {rob_uop_1_25_uses_ldq}, {rob_uop_1_24_uses_ldq}, {rob_uop_1_23_uses_ldq}, {rob_uop_1_22_uses_ldq}, {rob_uop_1_21_uses_ldq}, {rob_uop_1_20_uses_ldq}, {rob_uop_1_19_uses_ldq}, {rob_uop_1_18_uses_ldq}, {rob_uop_1_17_uses_ldq}, {rob_uop_1_16_uses_ldq}, {rob_uop_1_15_uses_ldq}, {rob_uop_1_14_uses_ldq}, {rob_uop_1_13_uses_ldq}, {rob_uop_1_12_uses_ldq}, {rob_uop_1_11_uses_ldq}, {rob_uop_1_10_uses_ldq}, {rob_uop_1_9_uses_ldq}, {rob_uop_1_8_uses_ldq}, {rob_uop_1_7_uses_ldq}, {rob_uop_1_6_uses_ldq}, {rob_uop_1_5_uses_ldq}, {rob_uop_1_4_uses_ldq}, {rob_uop_1_3_uses_ldq}, {rob_uop_1_2_uses_ldq}, {rob_uop_1_1_uses_ldq}, {rob_uop_1_0_uses_ldq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_uses_ldq_0 = _GEN_154[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_155 = {{rob_uop_1_31_uses_stq}, {rob_uop_1_30_uses_stq}, {rob_uop_1_29_uses_stq}, {rob_uop_1_28_uses_stq}, {rob_uop_1_27_uses_stq}, {rob_uop_1_26_uses_stq}, {rob_uop_1_25_uses_stq}, {rob_uop_1_24_uses_stq}, {rob_uop_1_23_uses_stq}, {rob_uop_1_22_uses_stq}, {rob_uop_1_21_uses_stq}, {rob_uop_1_20_uses_stq}, {rob_uop_1_19_uses_stq}, {rob_uop_1_18_uses_stq}, {rob_uop_1_17_uses_stq}, {rob_uop_1_16_uses_stq}, {rob_uop_1_15_uses_stq}, {rob_uop_1_14_uses_stq}, {rob_uop_1_13_uses_stq}, {rob_uop_1_12_uses_stq}, {rob_uop_1_11_uses_stq}, {rob_uop_1_10_uses_stq}, {rob_uop_1_9_uses_stq}, {rob_uop_1_8_uses_stq}, {rob_uop_1_7_uses_stq}, {rob_uop_1_6_uses_stq}, {rob_uop_1_5_uses_stq}, {rob_uop_1_4_uses_stq}, {rob_uop_1_3_uses_stq}, {rob_uop_1_2_uses_stq}, {rob_uop_1_1_uses_stq}, {rob_uop_1_0_uses_stq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_uses_stq_0 = _GEN_155[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_156 = {{rob_uop_1_31_is_sys_pc2epc}, {rob_uop_1_30_is_sys_pc2epc}, {rob_uop_1_29_is_sys_pc2epc}, {rob_uop_1_28_is_sys_pc2epc}, {rob_uop_1_27_is_sys_pc2epc}, {rob_uop_1_26_is_sys_pc2epc}, {rob_uop_1_25_is_sys_pc2epc}, {rob_uop_1_24_is_sys_pc2epc}, {rob_uop_1_23_is_sys_pc2epc}, {rob_uop_1_22_is_sys_pc2epc}, {rob_uop_1_21_is_sys_pc2epc}, {rob_uop_1_20_is_sys_pc2epc}, {rob_uop_1_19_is_sys_pc2epc}, {rob_uop_1_18_is_sys_pc2epc}, {rob_uop_1_17_is_sys_pc2epc}, {rob_uop_1_16_is_sys_pc2epc}, {rob_uop_1_15_is_sys_pc2epc}, {rob_uop_1_14_is_sys_pc2epc}, {rob_uop_1_13_is_sys_pc2epc}, {rob_uop_1_12_is_sys_pc2epc}, {rob_uop_1_11_is_sys_pc2epc}, {rob_uop_1_10_is_sys_pc2epc}, {rob_uop_1_9_is_sys_pc2epc}, {rob_uop_1_8_is_sys_pc2epc}, {rob_uop_1_7_is_sys_pc2epc}, {rob_uop_1_6_is_sys_pc2epc}, {rob_uop_1_5_is_sys_pc2epc}, {rob_uop_1_4_is_sys_pc2epc}, {rob_uop_1_3_is_sys_pc2epc}, {rob_uop_1_2_is_sys_pc2epc}, {rob_uop_1_1_is_sys_pc2epc}, {rob_uop_1_0_is_sys_pc2epc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_sys_pc2epc_0 = _GEN_156[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_157 = {{rob_uop_1_31_is_unique}, {rob_uop_1_30_is_unique}, {rob_uop_1_29_is_unique}, {rob_uop_1_28_is_unique}, {rob_uop_1_27_is_unique}, {rob_uop_1_26_is_unique}, {rob_uop_1_25_is_unique}, {rob_uop_1_24_is_unique}, {rob_uop_1_23_is_unique}, {rob_uop_1_22_is_unique}, {rob_uop_1_21_is_unique}, {rob_uop_1_20_is_unique}, {rob_uop_1_19_is_unique}, {rob_uop_1_18_is_unique}, {rob_uop_1_17_is_unique}, {rob_uop_1_16_is_unique}, {rob_uop_1_15_is_unique}, {rob_uop_1_14_is_unique}, {rob_uop_1_13_is_unique}, {rob_uop_1_12_is_unique}, {rob_uop_1_11_is_unique}, {rob_uop_1_10_is_unique}, {rob_uop_1_9_is_unique}, {rob_uop_1_8_is_unique}, {rob_uop_1_7_is_unique}, {rob_uop_1_6_is_unique}, {rob_uop_1_5_is_unique}, {rob_uop_1_4_is_unique}, {rob_uop_1_3_is_unique}, {rob_uop_1_2_is_unique}, {rob_uop_1_1_is_unique}, {rob_uop_1_0_is_unique}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_is_unique_0 = _GEN_157[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_158 = {{rob_uop_1_31_flush_on_commit}, {rob_uop_1_30_flush_on_commit}, {rob_uop_1_29_flush_on_commit}, {rob_uop_1_28_flush_on_commit}, {rob_uop_1_27_flush_on_commit}, {rob_uop_1_26_flush_on_commit}, {rob_uop_1_25_flush_on_commit}, {rob_uop_1_24_flush_on_commit}, {rob_uop_1_23_flush_on_commit}, {rob_uop_1_22_flush_on_commit}, {rob_uop_1_21_flush_on_commit}, {rob_uop_1_20_flush_on_commit}, {rob_uop_1_19_flush_on_commit}, {rob_uop_1_18_flush_on_commit}, {rob_uop_1_17_flush_on_commit}, {rob_uop_1_16_flush_on_commit}, {rob_uop_1_15_flush_on_commit}, {rob_uop_1_14_flush_on_commit}, {rob_uop_1_13_flush_on_commit}, {rob_uop_1_12_flush_on_commit}, {rob_uop_1_11_flush_on_commit}, {rob_uop_1_10_flush_on_commit}, {rob_uop_1_9_flush_on_commit}, {rob_uop_1_8_flush_on_commit}, {rob_uop_1_7_flush_on_commit}, {rob_uop_1_6_flush_on_commit}, {rob_uop_1_5_flush_on_commit}, {rob_uop_1_4_flush_on_commit}, {rob_uop_1_3_flush_on_commit}, {rob_uop_1_2_flush_on_commit}, {rob_uop_1_1_flush_on_commit}, {rob_uop_1_0_flush_on_commit}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_flush_on_commit_0 = _GEN_158[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_159 = {{rob_uop_1_31_ldst_is_rs1}, {rob_uop_1_30_ldst_is_rs1}, {rob_uop_1_29_ldst_is_rs1}, {rob_uop_1_28_ldst_is_rs1}, {rob_uop_1_27_ldst_is_rs1}, {rob_uop_1_26_ldst_is_rs1}, {rob_uop_1_25_ldst_is_rs1}, {rob_uop_1_24_ldst_is_rs1}, {rob_uop_1_23_ldst_is_rs1}, {rob_uop_1_22_ldst_is_rs1}, {rob_uop_1_21_ldst_is_rs1}, {rob_uop_1_20_ldst_is_rs1}, {rob_uop_1_19_ldst_is_rs1}, {rob_uop_1_18_ldst_is_rs1}, {rob_uop_1_17_ldst_is_rs1}, {rob_uop_1_16_ldst_is_rs1}, {rob_uop_1_15_ldst_is_rs1}, {rob_uop_1_14_ldst_is_rs1}, {rob_uop_1_13_ldst_is_rs1}, {rob_uop_1_12_ldst_is_rs1}, {rob_uop_1_11_ldst_is_rs1}, {rob_uop_1_10_ldst_is_rs1}, {rob_uop_1_9_ldst_is_rs1}, {rob_uop_1_8_ldst_is_rs1}, {rob_uop_1_7_ldst_is_rs1}, {rob_uop_1_6_ldst_is_rs1}, {rob_uop_1_5_ldst_is_rs1}, {rob_uop_1_4_ldst_is_rs1}, {rob_uop_1_3_ldst_is_rs1}, {rob_uop_1_2_ldst_is_rs1}, {rob_uop_1_1_ldst_is_rs1}, {rob_uop_1_0_ldst_is_rs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ldst_is_rs1_0 = _GEN_159[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_160 = {{rob_uop_1_31_ldst}, {rob_uop_1_30_ldst}, {rob_uop_1_29_ldst}, {rob_uop_1_28_ldst}, {rob_uop_1_27_ldst}, {rob_uop_1_26_ldst}, {rob_uop_1_25_ldst}, {rob_uop_1_24_ldst}, {rob_uop_1_23_ldst}, {rob_uop_1_22_ldst}, {rob_uop_1_21_ldst}, {rob_uop_1_20_ldst}, {rob_uop_1_19_ldst}, {rob_uop_1_18_ldst}, {rob_uop_1_17_ldst}, {rob_uop_1_16_ldst}, {rob_uop_1_15_ldst}, {rob_uop_1_14_ldst}, {rob_uop_1_13_ldst}, {rob_uop_1_12_ldst}, {rob_uop_1_11_ldst}, {rob_uop_1_10_ldst}, {rob_uop_1_9_ldst}, {rob_uop_1_8_ldst}, {rob_uop_1_7_ldst}, {rob_uop_1_6_ldst}, {rob_uop_1_5_ldst}, {rob_uop_1_4_ldst}, {rob_uop_1_3_ldst}, {rob_uop_1_2_ldst}, {rob_uop_1_1_ldst}, {rob_uop_1_0_ldst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ldst_0 = _GEN_160[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_161 = {{rob_uop_1_31_lrs1}, {rob_uop_1_30_lrs1}, {rob_uop_1_29_lrs1}, {rob_uop_1_28_lrs1}, {rob_uop_1_27_lrs1}, {rob_uop_1_26_lrs1}, {rob_uop_1_25_lrs1}, {rob_uop_1_24_lrs1}, {rob_uop_1_23_lrs1}, {rob_uop_1_22_lrs1}, {rob_uop_1_21_lrs1}, {rob_uop_1_20_lrs1}, {rob_uop_1_19_lrs1}, {rob_uop_1_18_lrs1}, {rob_uop_1_17_lrs1}, {rob_uop_1_16_lrs1}, {rob_uop_1_15_lrs1}, {rob_uop_1_14_lrs1}, {rob_uop_1_13_lrs1}, {rob_uop_1_12_lrs1}, {rob_uop_1_11_lrs1}, {rob_uop_1_10_lrs1}, {rob_uop_1_9_lrs1}, {rob_uop_1_8_lrs1}, {rob_uop_1_7_lrs1}, {rob_uop_1_6_lrs1}, {rob_uop_1_5_lrs1}, {rob_uop_1_4_lrs1}, {rob_uop_1_3_lrs1}, {rob_uop_1_2_lrs1}, {rob_uop_1_1_lrs1}, {rob_uop_1_0_lrs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_lrs1_0 = _GEN_161[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_162 = {{rob_uop_1_31_lrs2}, {rob_uop_1_30_lrs2}, {rob_uop_1_29_lrs2}, {rob_uop_1_28_lrs2}, {rob_uop_1_27_lrs2}, {rob_uop_1_26_lrs2}, {rob_uop_1_25_lrs2}, {rob_uop_1_24_lrs2}, {rob_uop_1_23_lrs2}, {rob_uop_1_22_lrs2}, {rob_uop_1_21_lrs2}, {rob_uop_1_20_lrs2}, {rob_uop_1_19_lrs2}, {rob_uop_1_18_lrs2}, {rob_uop_1_17_lrs2}, {rob_uop_1_16_lrs2}, {rob_uop_1_15_lrs2}, {rob_uop_1_14_lrs2}, {rob_uop_1_13_lrs2}, {rob_uop_1_12_lrs2}, {rob_uop_1_11_lrs2}, {rob_uop_1_10_lrs2}, {rob_uop_1_9_lrs2}, {rob_uop_1_8_lrs2}, {rob_uop_1_7_lrs2}, {rob_uop_1_6_lrs2}, {rob_uop_1_5_lrs2}, {rob_uop_1_4_lrs2}, {rob_uop_1_3_lrs2}, {rob_uop_1_2_lrs2}, {rob_uop_1_1_lrs2}, {rob_uop_1_0_lrs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_lrs2_0 = _GEN_162[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_163 = {{rob_uop_1_31_lrs3}, {rob_uop_1_30_lrs3}, {rob_uop_1_29_lrs3}, {rob_uop_1_28_lrs3}, {rob_uop_1_27_lrs3}, {rob_uop_1_26_lrs3}, {rob_uop_1_25_lrs3}, {rob_uop_1_24_lrs3}, {rob_uop_1_23_lrs3}, {rob_uop_1_22_lrs3}, {rob_uop_1_21_lrs3}, {rob_uop_1_20_lrs3}, {rob_uop_1_19_lrs3}, {rob_uop_1_18_lrs3}, {rob_uop_1_17_lrs3}, {rob_uop_1_16_lrs3}, {rob_uop_1_15_lrs3}, {rob_uop_1_14_lrs3}, {rob_uop_1_13_lrs3}, {rob_uop_1_12_lrs3}, {rob_uop_1_11_lrs3}, {rob_uop_1_10_lrs3}, {rob_uop_1_9_lrs3}, {rob_uop_1_8_lrs3}, {rob_uop_1_7_lrs3}, {rob_uop_1_6_lrs3}, {rob_uop_1_5_lrs3}, {rob_uop_1_4_lrs3}, {rob_uop_1_3_lrs3}, {rob_uop_1_2_lrs3}, {rob_uop_1_1_lrs3}, {rob_uop_1_0_lrs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_lrs3_0 = _GEN_163[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_164 = {{rob_uop_1_31_ldst_val}, {rob_uop_1_30_ldst_val}, {rob_uop_1_29_ldst_val}, {rob_uop_1_28_ldst_val}, {rob_uop_1_27_ldst_val}, {rob_uop_1_26_ldst_val}, {rob_uop_1_25_ldst_val}, {rob_uop_1_24_ldst_val}, {rob_uop_1_23_ldst_val}, {rob_uop_1_22_ldst_val}, {rob_uop_1_21_ldst_val}, {rob_uop_1_20_ldst_val}, {rob_uop_1_19_ldst_val}, {rob_uop_1_18_ldst_val}, {rob_uop_1_17_ldst_val}, {rob_uop_1_16_ldst_val}, {rob_uop_1_15_ldst_val}, {rob_uop_1_14_ldst_val}, {rob_uop_1_13_ldst_val}, {rob_uop_1_12_ldst_val}, {rob_uop_1_11_ldst_val}, {rob_uop_1_10_ldst_val}, {rob_uop_1_9_ldst_val}, {rob_uop_1_8_ldst_val}, {rob_uop_1_7_ldst_val}, {rob_uop_1_6_ldst_val}, {rob_uop_1_5_ldst_val}, {rob_uop_1_4_ldst_val}, {rob_uop_1_3_ldst_val}, {rob_uop_1_2_ldst_val}, {rob_uop_1_1_ldst_val}, {rob_uop_1_0_ldst_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_ldst_val_0 = _GEN_164[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_165 = {{rob_uop_1_31_dst_rtype}, {rob_uop_1_30_dst_rtype}, {rob_uop_1_29_dst_rtype}, {rob_uop_1_28_dst_rtype}, {rob_uop_1_27_dst_rtype}, {rob_uop_1_26_dst_rtype}, {rob_uop_1_25_dst_rtype}, {rob_uop_1_24_dst_rtype}, {rob_uop_1_23_dst_rtype}, {rob_uop_1_22_dst_rtype}, {rob_uop_1_21_dst_rtype}, {rob_uop_1_20_dst_rtype}, {rob_uop_1_19_dst_rtype}, {rob_uop_1_18_dst_rtype}, {rob_uop_1_17_dst_rtype}, {rob_uop_1_16_dst_rtype}, {rob_uop_1_15_dst_rtype}, {rob_uop_1_14_dst_rtype}, {rob_uop_1_13_dst_rtype}, {rob_uop_1_12_dst_rtype}, {rob_uop_1_11_dst_rtype}, {rob_uop_1_10_dst_rtype}, {rob_uop_1_9_dst_rtype}, {rob_uop_1_8_dst_rtype}, {rob_uop_1_7_dst_rtype}, {rob_uop_1_6_dst_rtype}, {rob_uop_1_5_dst_rtype}, {rob_uop_1_4_dst_rtype}, {rob_uop_1_3_dst_rtype}, {rob_uop_1_2_dst_rtype}, {rob_uop_1_1_dst_rtype}, {rob_uop_1_0_dst_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_dst_rtype_0 = _GEN_165[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_166 = {{rob_uop_1_31_lrs1_rtype}, {rob_uop_1_30_lrs1_rtype}, {rob_uop_1_29_lrs1_rtype}, {rob_uop_1_28_lrs1_rtype}, {rob_uop_1_27_lrs1_rtype}, {rob_uop_1_26_lrs1_rtype}, {rob_uop_1_25_lrs1_rtype}, {rob_uop_1_24_lrs1_rtype}, {rob_uop_1_23_lrs1_rtype}, {rob_uop_1_22_lrs1_rtype}, {rob_uop_1_21_lrs1_rtype}, {rob_uop_1_20_lrs1_rtype}, {rob_uop_1_19_lrs1_rtype}, {rob_uop_1_18_lrs1_rtype}, {rob_uop_1_17_lrs1_rtype}, {rob_uop_1_16_lrs1_rtype}, {rob_uop_1_15_lrs1_rtype}, {rob_uop_1_14_lrs1_rtype}, {rob_uop_1_13_lrs1_rtype}, {rob_uop_1_12_lrs1_rtype}, {rob_uop_1_11_lrs1_rtype}, {rob_uop_1_10_lrs1_rtype}, {rob_uop_1_9_lrs1_rtype}, {rob_uop_1_8_lrs1_rtype}, {rob_uop_1_7_lrs1_rtype}, {rob_uop_1_6_lrs1_rtype}, {rob_uop_1_5_lrs1_rtype}, {rob_uop_1_4_lrs1_rtype}, {rob_uop_1_3_lrs1_rtype}, {rob_uop_1_2_lrs1_rtype}, {rob_uop_1_1_lrs1_rtype}, {rob_uop_1_0_lrs1_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_lrs1_rtype_0 = _GEN_166[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_167 = {{rob_uop_1_31_lrs2_rtype}, {rob_uop_1_30_lrs2_rtype}, {rob_uop_1_29_lrs2_rtype}, {rob_uop_1_28_lrs2_rtype}, {rob_uop_1_27_lrs2_rtype}, {rob_uop_1_26_lrs2_rtype}, {rob_uop_1_25_lrs2_rtype}, {rob_uop_1_24_lrs2_rtype}, {rob_uop_1_23_lrs2_rtype}, {rob_uop_1_22_lrs2_rtype}, {rob_uop_1_21_lrs2_rtype}, {rob_uop_1_20_lrs2_rtype}, {rob_uop_1_19_lrs2_rtype}, {rob_uop_1_18_lrs2_rtype}, {rob_uop_1_17_lrs2_rtype}, {rob_uop_1_16_lrs2_rtype}, {rob_uop_1_15_lrs2_rtype}, {rob_uop_1_14_lrs2_rtype}, {rob_uop_1_13_lrs2_rtype}, {rob_uop_1_12_lrs2_rtype}, {rob_uop_1_11_lrs2_rtype}, {rob_uop_1_10_lrs2_rtype}, {rob_uop_1_9_lrs2_rtype}, {rob_uop_1_8_lrs2_rtype}, {rob_uop_1_7_lrs2_rtype}, {rob_uop_1_6_lrs2_rtype}, {rob_uop_1_5_lrs2_rtype}, {rob_uop_1_4_lrs2_rtype}, {rob_uop_1_3_lrs2_rtype}, {rob_uop_1_2_lrs2_rtype}, {rob_uop_1_1_lrs2_rtype}, {rob_uop_1_0_lrs2_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_lrs2_rtype_0 = _GEN_167[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_168 = {{rob_uop_1_31_frs3_en}, {rob_uop_1_30_frs3_en}, {rob_uop_1_29_frs3_en}, {rob_uop_1_28_frs3_en}, {rob_uop_1_27_frs3_en}, {rob_uop_1_26_frs3_en}, {rob_uop_1_25_frs3_en}, {rob_uop_1_24_frs3_en}, {rob_uop_1_23_frs3_en}, {rob_uop_1_22_frs3_en}, {rob_uop_1_21_frs3_en}, {rob_uop_1_20_frs3_en}, {rob_uop_1_19_frs3_en}, {rob_uop_1_18_frs3_en}, {rob_uop_1_17_frs3_en}, {rob_uop_1_16_frs3_en}, {rob_uop_1_15_frs3_en}, {rob_uop_1_14_frs3_en}, {rob_uop_1_13_frs3_en}, {rob_uop_1_12_frs3_en}, {rob_uop_1_11_frs3_en}, {rob_uop_1_10_frs3_en}, {rob_uop_1_9_frs3_en}, {rob_uop_1_8_frs3_en}, {rob_uop_1_7_frs3_en}, {rob_uop_1_6_frs3_en}, {rob_uop_1_5_frs3_en}, {rob_uop_1_4_frs3_en}, {rob_uop_1_3_frs3_en}, {rob_uop_1_2_frs3_en}, {rob_uop_1_1_frs3_en}, {rob_uop_1_0_frs3_en}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_frs3_en_0 = _GEN_168[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_169 = {{rob_uop_1_31_fp_val}, {rob_uop_1_30_fp_val}, {rob_uop_1_29_fp_val}, {rob_uop_1_28_fp_val}, {rob_uop_1_27_fp_val}, {rob_uop_1_26_fp_val}, {rob_uop_1_25_fp_val}, {rob_uop_1_24_fp_val}, {rob_uop_1_23_fp_val}, {rob_uop_1_22_fp_val}, {rob_uop_1_21_fp_val}, {rob_uop_1_20_fp_val}, {rob_uop_1_19_fp_val}, {rob_uop_1_18_fp_val}, {rob_uop_1_17_fp_val}, {rob_uop_1_16_fp_val}, {rob_uop_1_15_fp_val}, {rob_uop_1_14_fp_val}, {rob_uop_1_13_fp_val}, {rob_uop_1_12_fp_val}, {rob_uop_1_11_fp_val}, {rob_uop_1_10_fp_val}, {rob_uop_1_9_fp_val}, {rob_uop_1_8_fp_val}, {rob_uop_1_7_fp_val}, {rob_uop_1_6_fp_val}, {rob_uop_1_5_fp_val}, {rob_uop_1_4_fp_val}, {rob_uop_1_3_fp_val}, {rob_uop_1_2_fp_val}, {rob_uop_1_1_fp_val}, {rob_uop_1_0_fp_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_fp_val_0 = _GEN_169[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_170 = {{rob_uop_1_31_fp_single}, {rob_uop_1_30_fp_single}, {rob_uop_1_29_fp_single}, {rob_uop_1_28_fp_single}, {rob_uop_1_27_fp_single}, {rob_uop_1_26_fp_single}, {rob_uop_1_25_fp_single}, {rob_uop_1_24_fp_single}, {rob_uop_1_23_fp_single}, {rob_uop_1_22_fp_single}, {rob_uop_1_21_fp_single}, {rob_uop_1_20_fp_single}, {rob_uop_1_19_fp_single}, {rob_uop_1_18_fp_single}, {rob_uop_1_17_fp_single}, {rob_uop_1_16_fp_single}, {rob_uop_1_15_fp_single}, {rob_uop_1_14_fp_single}, {rob_uop_1_13_fp_single}, {rob_uop_1_12_fp_single}, {rob_uop_1_11_fp_single}, {rob_uop_1_10_fp_single}, {rob_uop_1_9_fp_single}, {rob_uop_1_8_fp_single}, {rob_uop_1_7_fp_single}, {rob_uop_1_6_fp_single}, {rob_uop_1_5_fp_single}, {rob_uop_1_4_fp_single}, {rob_uop_1_3_fp_single}, {rob_uop_1_2_fp_single}, {rob_uop_1_1_fp_single}, {rob_uop_1_0_fp_single}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_fp_single_0 = _GEN_170[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_171 = {{rob_uop_1_31_xcpt_pf_if}, {rob_uop_1_30_xcpt_pf_if}, {rob_uop_1_29_xcpt_pf_if}, {rob_uop_1_28_xcpt_pf_if}, {rob_uop_1_27_xcpt_pf_if}, {rob_uop_1_26_xcpt_pf_if}, {rob_uop_1_25_xcpt_pf_if}, {rob_uop_1_24_xcpt_pf_if}, {rob_uop_1_23_xcpt_pf_if}, {rob_uop_1_22_xcpt_pf_if}, {rob_uop_1_21_xcpt_pf_if}, {rob_uop_1_20_xcpt_pf_if}, {rob_uop_1_19_xcpt_pf_if}, {rob_uop_1_18_xcpt_pf_if}, {rob_uop_1_17_xcpt_pf_if}, {rob_uop_1_16_xcpt_pf_if}, {rob_uop_1_15_xcpt_pf_if}, {rob_uop_1_14_xcpt_pf_if}, {rob_uop_1_13_xcpt_pf_if}, {rob_uop_1_12_xcpt_pf_if}, {rob_uop_1_11_xcpt_pf_if}, {rob_uop_1_10_xcpt_pf_if}, {rob_uop_1_9_xcpt_pf_if}, {rob_uop_1_8_xcpt_pf_if}, {rob_uop_1_7_xcpt_pf_if}, {rob_uop_1_6_xcpt_pf_if}, {rob_uop_1_5_xcpt_pf_if}, {rob_uop_1_4_xcpt_pf_if}, {rob_uop_1_3_xcpt_pf_if}, {rob_uop_1_2_xcpt_pf_if}, {rob_uop_1_1_xcpt_pf_if}, {rob_uop_1_0_xcpt_pf_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_xcpt_pf_if_0 = _GEN_171[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_172 = {{rob_uop_1_31_xcpt_ae_if}, {rob_uop_1_30_xcpt_ae_if}, {rob_uop_1_29_xcpt_ae_if}, {rob_uop_1_28_xcpt_ae_if}, {rob_uop_1_27_xcpt_ae_if}, {rob_uop_1_26_xcpt_ae_if}, {rob_uop_1_25_xcpt_ae_if}, {rob_uop_1_24_xcpt_ae_if}, {rob_uop_1_23_xcpt_ae_if}, {rob_uop_1_22_xcpt_ae_if}, {rob_uop_1_21_xcpt_ae_if}, {rob_uop_1_20_xcpt_ae_if}, {rob_uop_1_19_xcpt_ae_if}, {rob_uop_1_18_xcpt_ae_if}, {rob_uop_1_17_xcpt_ae_if}, {rob_uop_1_16_xcpt_ae_if}, {rob_uop_1_15_xcpt_ae_if}, {rob_uop_1_14_xcpt_ae_if}, {rob_uop_1_13_xcpt_ae_if}, {rob_uop_1_12_xcpt_ae_if}, {rob_uop_1_11_xcpt_ae_if}, {rob_uop_1_10_xcpt_ae_if}, {rob_uop_1_9_xcpt_ae_if}, {rob_uop_1_8_xcpt_ae_if}, {rob_uop_1_7_xcpt_ae_if}, {rob_uop_1_6_xcpt_ae_if}, {rob_uop_1_5_xcpt_ae_if}, {rob_uop_1_4_xcpt_ae_if}, {rob_uop_1_3_xcpt_ae_if}, {rob_uop_1_2_xcpt_ae_if}, {rob_uop_1_1_xcpt_ae_if}, {rob_uop_1_0_xcpt_ae_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_xcpt_ae_if_0 = _GEN_172[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_173 = {{rob_uop_1_31_xcpt_ma_if}, {rob_uop_1_30_xcpt_ma_if}, {rob_uop_1_29_xcpt_ma_if}, {rob_uop_1_28_xcpt_ma_if}, {rob_uop_1_27_xcpt_ma_if}, {rob_uop_1_26_xcpt_ma_if}, {rob_uop_1_25_xcpt_ma_if}, {rob_uop_1_24_xcpt_ma_if}, {rob_uop_1_23_xcpt_ma_if}, {rob_uop_1_22_xcpt_ma_if}, {rob_uop_1_21_xcpt_ma_if}, {rob_uop_1_20_xcpt_ma_if}, {rob_uop_1_19_xcpt_ma_if}, {rob_uop_1_18_xcpt_ma_if}, {rob_uop_1_17_xcpt_ma_if}, {rob_uop_1_16_xcpt_ma_if}, {rob_uop_1_15_xcpt_ma_if}, {rob_uop_1_14_xcpt_ma_if}, {rob_uop_1_13_xcpt_ma_if}, {rob_uop_1_12_xcpt_ma_if}, {rob_uop_1_11_xcpt_ma_if}, {rob_uop_1_10_xcpt_ma_if}, {rob_uop_1_9_xcpt_ma_if}, {rob_uop_1_8_xcpt_ma_if}, {rob_uop_1_7_xcpt_ma_if}, {rob_uop_1_6_xcpt_ma_if}, {rob_uop_1_5_xcpt_ma_if}, {rob_uop_1_4_xcpt_ma_if}, {rob_uop_1_3_xcpt_ma_if}, {rob_uop_1_2_xcpt_ma_if}, {rob_uop_1_1_xcpt_ma_if}, {rob_uop_1_0_xcpt_ma_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_xcpt_ma_if_0 = _GEN_173[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_174 = {{rob_uop_1_31_bp_debug_if}, {rob_uop_1_30_bp_debug_if}, {rob_uop_1_29_bp_debug_if}, {rob_uop_1_28_bp_debug_if}, {rob_uop_1_27_bp_debug_if}, {rob_uop_1_26_bp_debug_if}, {rob_uop_1_25_bp_debug_if}, {rob_uop_1_24_bp_debug_if}, {rob_uop_1_23_bp_debug_if}, {rob_uop_1_22_bp_debug_if}, {rob_uop_1_21_bp_debug_if}, {rob_uop_1_20_bp_debug_if}, {rob_uop_1_19_bp_debug_if}, {rob_uop_1_18_bp_debug_if}, {rob_uop_1_17_bp_debug_if}, {rob_uop_1_16_bp_debug_if}, {rob_uop_1_15_bp_debug_if}, {rob_uop_1_14_bp_debug_if}, {rob_uop_1_13_bp_debug_if}, {rob_uop_1_12_bp_debug_if}, {rob_uop_1_11_bp_debug_if}, {rob_uop_1_10_bp_debug_if}, {rob_uop_1_9_bp_debug_if}, {rob_uop_1_8_bp_debug_if}, {rob_uop_1_7_bp_debug_if}, {rob_uop_1_6_bp_debug_if}, {rob_uop_1_5_bp_debug_if}, {rob_uop_1_4_bp_debug_if}, {rob_uop_1_3_bp_debug_if}, {rob_uop_1_2_bp_debug_if}, {rob_uop_1_1_bp_debug_if}, {rob_uop_1_0_bp_debug_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_bp_debug_if_0 = _GEN_174[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_175 = {{rob_uop_1_31_bp_xcpt_if}, {rob_uop_1_30_bp_xcpt_if}, {rob_uop_1_29_bp_xcpt_if}, {rob_uop_1_28_bp_xcpt_if}, {rob_uop_1_27_bp_xcpt_if}, {rob_uop_1_26_bp_xcpt_if}, {rob_uop_1_25_bp_xcpt_if}, {rob_uop_1_24_bp_xcpt_if}, {rob_uop_1_23_bp_xcpt_if}, {rob_uop_1_22_bp_xcpt_if}, {rob_uop_1_21_bp_xcpt_if}, {rob_uop_1_20_bp_xcpt_if}, {rob_uop_1_19_bp_xcpt_if}, {rob_uop_1_18_bp_xcpt_if}, {rob_uop_1_17_bp_xcpt_if}, {rob_uop_1_16_bp_xcpt_if}, {rob_uop_1_15_bp_xcpt_if}, {rob_uop_1_14_bp_xcpt_if}, {rob_uop_1_13_bp_xcpt_if}, {rob_uop_1_12_bp_xcpt_if}, {rob_uop_1_11_bp_xcpt_if}, {rob_uop_1_10_bp_xcpt_if}, {rob_uop_1_9_bp_xcpt_if}, {rob_uop_1_8_bp_xcpt_if}, {rob_uop_1_7_bp_xcpt_if}, {rob_uop_1_6_bp_xcpt_if}, {rob_uop_1_5_bp_xcpt_if}, {rob_uop_1_4_bp_xcpt_if}, {rob_uop_1_3_bp_xcpt_if}, {rob_uop_1_2_bp_xcpt_if}, {rob_uop_1_1_bp_xcpt_if}, {rob_uop_1_0_bp_xcpt_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_bp_xcpt_if_0 = _GEN_175[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_176 = {{rob_uop_1_31_debug_fsrc}, {rob_uop_1_30_debug_fsrc}, {rob_uop_1_29_debug_fsrc}, {rob_uop_1_28_debug_fsrc}, {rob_uop_1_27_debug_fsrc}, {rob_uop_1_26_debug_fsrc}, {rob_uop_1_25_debug_fsrc}, {rob_uop_1_24_debug_fsrc}, {rob_uop_1_23_debug_fsrc}, {rob_uop_1_22_debug_fsrc}, {rob_uop_1_21_debug_fsrc}, {rob_uop_1_20_debug_fsrc}, {rob_uop_1_19_debug_fsrc}, {rob_uop_1_18_debug_fsrc}, {rob_uop_1_17_debug_fsrc}, {rob_uop_1_16_debug_fsrc}, {rob_uop_1_15_debug_fsrc}, {rob_uop_1_14_debug_fsrc}, {rob_uop_1_13_debug_fsrc}, {rob_uop_1_12_debug_fsrc}, {rob_uop_1_11_debug_fsrc}, {rob_uop_1_10_debug_fsrc}, {rob_uop_1_9_debug_fsrc}, {rob_uop_1_8_debug_fsrc}, {rob_uop_1_7_debug_fsrc}, {rob_uop_1_6_debug_fsrc}, {rob_uop_1_5_debug_fsrc}, {rob_uop_1_4_debug_fsrc}, {rob_uop_1_3_debug_fsrc}, {rob_uop_1_2_debug_fsrc}, {rob_uop_1_1_debug_fsrc}, {rob_uop_1_0_debug_fsrc}}; // @[rob.scala:311:28, :415:25]
wire [31:0][1:0] _GEN_177 = {{rob_uop_1_31_debug_tsrc}, {rob_uop_1_30_debug_tsrc}, {rob_uop_1_29_debug_tsrc}, {rob_uop_1_28_debug_tsrc}, {rob_uop_1_27_debug_tsrc}, {rob_uop_1_26_debug_tsrc}, {rob_uop_1_25_debug_tsrc}, {rob_uop_1_24_debug_tsrc}, {rob_uop_1_23_debug_tsrc}, {rob_uop_1_22_debug_tsrc}, {rob_uop_1_21_debug_tsrc}, {rob_uop_1_20_debug_tsrc}, {rob_uop_1_19_debug_tsrc}, {rob_uop_1_18_debug_tsrc}, {rob_uop_1_17_debug_tsrc}, {rob_uop_1_16_debug_tsrc}, {rob_uop_1_15_debug_tsrc}, {rob_uop_1_14_debug_tsrc}, {rob_uop_1_13_debug_tsrc}, {rob_uop_1_12_debug_tsrc}, {rob_uop_1_11_debug_tsrc}, {rob_uop_1_10_debug_tsrc}, {rob_uop_1_9_debug_tsrc}, {rob_uop_1_8_debug_tsrc}, {rob_uop_1_7_debug_tsrc}, {rob_uop_1_6_debug_tsrc}, {rob_uop_1_5_debug_tsrc}, {rob_uop_1_4_debug_tsrc}, {rob_uop_1_3_debug_tsrc}, {rob_uop_1_2_debug_tsrc}, {rob_uop_1_1_debug_tsrc}, {rob_uop_1_0_debug_tsrc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_1_debug_tsrc_0 = _GEN_177[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire _T_531 = io_brupdate_b2_mispredict_0 & io_brupdate_b2_uop_rob_idx_0[1:0] == 2'h1 & io_brupdate_b2_uop_rob_idx_0[6:2] == com_idx; // @[rob.scala:211:7, :235:20, :267:25, :271:36, :305:53, :420:37, :421:57, :422:45]
assign io_commit_uops_1_debug_fsrc_0 = _T_531 ? 2'h3 : _GEN_176[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :423:36]
assign io_commit_uops_1_taken_0 = _T_531 ? io_brupdate_b2_taken_0 : _GEN_130[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :424:36]
wire _rbk_row_T_3 = ~full; // @[rob.scala:239:26, :429:47]
wire rbk_row_1 = _rbk_row_T_2 & _rbk_row_T_3; // @[rob.scala:429:{29,44,47}]
wire _io_commit_rbk_valids_1_T = rbk_row_1 & _GEN_94[com_idx]; // @[rob.scala:235:20, :324:31, :429:44, :431:40]
assign _io_commit_rbk_valids_1_T_2 = _io_commit_rbk_valids_1_T; // @[rob.scala:431:{40,60}]
assign io_commit_rbk_valids_1_0 = _io_commit_rbk_valids_1_T_2; // @[rob.scala:211:7, :431:60]
wire [15:0] _rob_uop_0_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_0_br_mask_T_3 = rob_uop_1_0_br_mask & _rob_uop_0_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_1_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_1_br_mask_T_3 = rob_uop_1_1_br_mask & _rob_uop_1_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_2_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_2_br_mask_T_3 = rob_uop_1_2_br_mask & _rob_uop_2_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_3_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_3_br_mask_T_3 = rob_uop_1_3_br_mask & _rob_uop_3_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_4_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_4_br_mask_T_3 = rob_uop_1_4_br_mask & _rob_uop_4_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_5_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_5_br_mask_T_3 = rob_uop_1_5_br_mask & _rob_uop_5_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_6_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_6_br_mask_T_3 = rob_uop_1_6_br_mask & _rob_uop_6_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_7_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_7_br_mask_T_3 = rob_uop_1_7_br_mask & _rob_uop_7_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_8_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_8_br_mask_T_3 = rob_uop_1_8_br_mask & _rob_uop_8_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_9_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_9_br_mask_T_3 = rob_uop_1_9_br_mask & _rob_uop_9_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_10_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_10_br_mask_T_3 = rob_uop_1_10_br_mask & _rob_uop_10_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_11_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_11_br_mask_T_3 = rob_uop_1_11_br_mask & _rob_uop_11_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_12_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_12_br_mask_T_3 = rob_uop_1_12_br_mask & _rob_uop_12_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_13_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_13_br_mask_T_3 = rob_uop_1_13_br_mask & _rob_uop_13_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_14_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_14_br_mask_T_3 = rob_uop_1_14_br_mask & _rob_uop_14_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_15_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_15_br_mask_T_3 = rob_uop_1_15_br_mask & _rob_uop_15_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_16_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_16_br_mask_T_3 = rob_uop_1_16_br_mask & _rob_uop_16_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_17_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_17_br_mask_T_3 = rob_uop_1_17_br_mask & _rob_uop_17_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_18_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_18_br_mask_T_3 = rob_uop_1_18_br_mask & _rob_uop_18_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_19_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_19_br_mask_T_3 = rob_uop_1_19_br_mask & _rob_uop_19_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_20_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_20_br_mask_T_3 = rob_uop_1_20_br_mask & _rob_uop_20_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_21_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_21_br_mask_T_3 = rob_uop_1_21_br_mask & _rob_uop_21_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_22_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_22_br_mask_T_3 = rob_uop_1_22_br_mask & _rob_uop_22_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_23_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_23_br_mask_T_3 = rob_uop_1_23_br_mask & _rob_uop_23_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_24_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_24_br_mask_T_3 = rob_uop_1_24_br_mask & _rob_uop_24_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_25_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_25_br_mask_T_3 = rob_uop_1_25_br_mask & _rob_uop_25_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_26_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_26_br_mask_T_3 = rob_uop_1_26_br_mask & _rob_uop_26_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_27_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_27_br_mask_T_3 = rob_uop_1_27_br_mask & _rob_uop_27_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_28_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_28_br_mask_T_3 = rob_uop_1_28_br_mask & _rob_uop_28_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_29_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_29_br_mask_T_3 = rob_uop_1_29_br_mask & _rob_uop_29_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_30_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_30_br_mask_T_3 = rob_uop_1_30_br_mask & _rob_uop_30_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_31_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_31_br_mask_T_3 = rob_uop_1_31_br_mask & _rob_uop_31_br_mask_T_2; // @[util.scala:89:{21,23}]
wire [31:0][4:0] _GEN_178 = {{rob_fflags_1_31}, {rob_fflags_1_30}, {rob_fflags_1_29}, {rob_fflags_1_28}, {rob_fflags_1_27}, {rob_fflags_1_26}, {rob_fflags_1_25}, {rob_fflags_1_24}, {rob_fflags_1_23}, {rob_fflags_1_22}, {rob_fflags_1_21}, {rob_fflags_1_20}, {rob_fflags_1_19}, {rob_fflags_1_18}, {rob_fflags_1_17}, {rob_fflags_1_16}, {rob_fflags_1_15}, {rob_fflags_1_14}, {rob_fflags_1_13}, {rob_fflags_1_12}, {rob_fflags_1_11}, {rob_fflags_1_10}, {rob_fflags_1_9}, {rob_fflags_1_8}, {rob_fflags_1_7}, {rob_fflags_1_6}, {rob_fflags_1_5}, {rob_fflags_1_4}, {rob_fflags_1_3}, {rob_fflags_1_2}, {rob_fflags_1_1}, {rob_fflags_1_0}}; // @[rob.scala:302:46, :487:26]
assign rob_head_fflags_1 = _GEN_178[rob_head]; // @[rob.scala:223:29, :251:33, :487:26]
assign rob_head_uses_ldq_1 = _GEN_154[rob_head]; // @[rob.scala:223:29, :250:33, :415:25, :488:26]
assign rob_head_uses_stq_1 = _GEN_155[rob_head]; // @[rob.scala:223:29, :249:33, :415:25, :488:26]
wire _rob_unsafe_masked_1_T = rob_unsafe_1_0 | rob_exception_1_0; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_1_T_1 = rob_val_1_0 & _rob_unsafe_masked_1_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_1 = _rob_unsafe_masked_1_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_5_T = rob_unsafe_1_1 | rob_exception_1_1; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_5_T_1 = rob_val_1_1 & _rob_unsafe_masked_5_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_5 = _rob_unsafe_masked_5_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_9_T = rob_unsafe_1_2 | rob_exception_1_2; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_9_T_1 = rob_val_1_2 & _rob_unsafe_masked_9_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_9 = _rob_unsafe_masked_9_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_13_T = rob_unsafe_1_3 | rob_exception_1_3; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_13_T_1 = rob_val_1_3 & _rob_unsafe_masked_13_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_13 = _rob_unsafe_masked_13_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_17_T = rob_unsafe_1_4 | rob_exception_1_4; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_17_T_1 = rob_val_1_4 & _rob_unsafe_masked_17_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_17 = _rob_unsafe_masked_17_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_21_T = rob_unsafe_1_5 | rob_exception_1_5; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_21_T_1 = rob_val_1_5 & _rob_unsafe_masked_21_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_21 = _rob_unsafe_masked_21_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_25_T = rob_unsafe_1_6 | rob_exception_1_6; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_25_T_1 = rob_val_1_6 & _rob_unsafe_masked_25_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_25 = _rob_unsafe_masked_25_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_29_T = rob_unsafe_1_7 | rob_exception_1_7; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_29_T_1 = rob_val_1_7 & _rob_unsafe_masked_29_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_29 = _rob_unsafe_masked_29_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_33_T = rob_unsafe_1_8 | rob_exception_1_8; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_33_T_1 = rob_val_1_8 & _rob_unsafe_masked_33_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_33 = _rob_unsafe_masked_33_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_37_T = rob_unsafe_1_9 | rob_exception_1_9; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_37_T_1 = rob_val_1_9 & _rob_unsafe_masked_37_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_37 = _rob_unsafe_masked_37_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_41_T = rob_unsafe_1_10 | rob_exception_1_10; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_41_T_1 = rob_val_1_10 & _rob_unsafe_masked_41_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_41 = _rob_unsafe_masked_41_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_45_T = rob_unsafe_1_11 | rob_exception_1_11; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_45_T_1 = rob_val_1_11 & _rob_unsafe_masked_45_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_45 = _rob_unsafe_masked_45_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_49_T = rob_unsafe_1_12 | rob_exception_1_12; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_49_T_1 = rob_val_1_12 & _rob_unsafe_masked_49_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_49 = _rob_unsafe_masked_49_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_53_T = rob_unsafe_1_13 | rob_exception_1_13; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_53_T_1 = rob_val_1_13 & _rob_unsafe_masked_53_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_53 = _rob_unsafe_masked_53_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_57_T = rob_unsafe_1_14 | rob_exception_1_14; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_57_T_1 = rob_val_1_14 & _rob_unsafe_masked_57_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_57 = _rob_unsafe_masked_57_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_61_T = rob_unsafe_1_15 | rob_exception_1_15; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_61_T_1 = rob_val_1_15 & _rob_unsafe_masked_61_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_61 = _rob_unsafe_masked_61_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_65_T = rob_unsafe_1_16 | rob_exception_1_16; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_65_T_1 = rob_val_1_16 & _rob_unsafe_masked_65_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_65 = _rob_unsafe_masked_65_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_69_T = rob_unsafe_1_17 | rob_exception_1_17; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_69_T_1 = rob_val_1_17 & _rob_unsafe_masked_69_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_69 = _rob_unsafe_masked_69_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_73_T = rob_unsafe_1_18 | rob_exception_1_18; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_73_T_1 = rob_val_1_18 & _rob_unsafe_masked_73_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_73 = _rob_unsafe_masked_73_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_77_T = rob_unsafe_1_19 | rob_exception_1_19; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_77_T_1 = rob_val_1_19 & _rob_unsafe_masked_77_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_77 = _rob_unsafe_masked_77_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_81_T = rob_unsafe_1_20 | rob_exception_1_20; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_81_T_1 = rob_val_1_20 & _rob_unsafe_masked_81_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_81 = _rob_unsafe_masked_81_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_85_T = rob_unsafe_1_21 | rob_exception_1_21; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_85_T_1 = rob_val_1_21 & _rob_unsafe_masked_85_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_85 = _rob_unsafe_masked_85_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_89_T = rob_unsafe_1_22 | rob_exception_1_22; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_89_T_1 = rob_val_1_22 & _rob_unsafe_masked_89_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_89 = _rob_unsafe_masked_89_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_93_T = rob_unsafe_1_23 | rob_exception_1_23; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_93_T_1 = rob_val_1_23 & _rob_unsafe_masked_93_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_93 = _rob_unsafe_masked_93_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_97_T = rob_unsafe_1_24 | rob_exception_1_24; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_97_T_1 = rob_val_1_24 & _rob_unsafe_masked_97_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_97 = _rob_unsafe_masked_97_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_101_T = rob_unsafe_1_25 | rob_exception_1_25; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_101_T_1 = rob_val_1_25 & _rob_unsafe_masked_101_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_101 = _rob_unsafe_masked_101_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_105_T = rob_unsafe_1_26 | rob_exception_1_26; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_105_T_1 = rob_val_1_26 & _rob_unsafe_masked_105_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_105 = _rob_unsafe_masked_105_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_109_T = rob_unsafe_1_27 | rob_exception_1_27; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_109_T_1 = rob_val_1_27 & _rob_unsafe_masked_109_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_109 = _rob_unsafe_masked_109_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_113_T = rob_unsafe_1_28 | rob_exception_1_28; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_113_T_1 = rob_val_1_28 & _rob_unsafe_masked_113_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_113 = _rob_unsafe_masked_113_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_117_T = rob_unsafe_1_29 | rob_exception_1_29; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_117_T_1 = rob_val_1_29 & _rob_unsafe_masked_117_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_117 = _rob_unsafe_masked_117_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_121_T = rob_unsafe_1_30 | rob_exception_1_30; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_121_T_1 = rob_val_1_30 & _rob_unsafe_masked_121_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_121 = _rob_unsafe_masked_121_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_125_T = rob_unsafe_1_31 | rob_exception_1_31; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_125_T_1 = rob_val_1_31 & _rob_unsafe_masked_125_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_125 = _rob_unsafe_masked_125_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_pnr_unsafe_1_T = _GEN_97[rob_pnr] | _GEN_99[rob_pnr]; // @[rob.scala:231:29, :394:15, :402:49, :497:67]
assign _rob_pnr_unsafe_1_T_1 = _GEN_94[rob_pnr] & _rob_pnr_unsafe_1_T; // @[rob.scala:231:29, :324:31, :497:{43,67}]
assign rob_pnr_unsafe_1 = _rob_pnr_unsafe_1_T_1; // @[rob.scala:246:33, :497:43]
wire [4:0] _temp_uop_T_13 = _temp_uop_T_12[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_15 = _temp_uop_T_14[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_17 = _temp_uop_T_16[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_19 = _temp_uop_T_18[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_21 = _temp_uop_T_20[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_23 = _temp_uop_T_22[4:0]; // @[rob.scala:267:25]
reg rob_val_2_0; // @[rob.scala:308:32]
reg rob_val_2_1; // @[rob.scala:308:32]
reg rob_val_2_2; // @[rob.scala:308:32]
reg rob_val_2_3; // @[rob.scala:308:32]
reg rob_val_2_4; // @[rob.scala:308:32]
reg rob_val_2_5; // @[rob.scala:308:32]
reg rob_val_2_6; // @[rob.scala:308:32]
reg rob_val_2_7; // @[rob.scala:308:32]
reg rob_val_2_8; // @[rob.scala:308:32]
reg rob_val_2_9; // @[rob.scala:308:32]
reg rob_val_2_10; // @[rob.scala:308:32]
reg rob_val_2_11; // @[rob.scala:308:32]
reg rob_val_2_12; // @[rob.scala:308:32]
reg rob_val_2_13; // @[rob.scala:308:32]
reg rob_val_2_14; // @[rob.scala:308:32]
reg rob_val_2_15; // @[rob.scala:308:32]
reg rob_val_2_16; // @[rob.scala:308:32]
reg rob_val_2_17; // @[rob.scala:308:32]
reg rob_val_2_18; // @[rob.scala:308:32]
reg rob_val_2_19; // @[rob.scala:308:32]
reg rob_val_2_20; // @[rob.scala:308:32]
reg rob_val_2_21; // @[rob.scala:308:32]
reg rob_val_2_22; // @[rob.scala:308:32]
reg rob_val_2_23; // @[rob.scala:308:32]
reg rob_val_2_24; // @[rob.scala:308:32]
reg rob_val_2_25; // @[rob.scala:308:32]
reg rob_val_2_26; // @[rob.scala:308:32]
reg rob_val_2_27; // @[rob.scala:308:32]
reg rob_val_2_28; // @[rob.scala:308:32]
reg rob_val_2_29; // @[rob.scala:308:32]
reg rob_val_2_30; // @[rob.scala:308:32]
reg rob_val_2_31; // @[rob.scala:308:32]
reg rob_bsy_2_0; // @[rob.scala:309:28]
reg rob_bsy_2_1; // @[rob.scala:309:28]
reg rob_bsy_2_2; // @[rob.scala:309:28]
reg rob_bsy_2_3; // @[rob.scala:309:28]
reg rob_bsy_2_4; // @[rob.scala:309:28]
reg rob_bsy_2_5; // @[rob.scala:309:28]
reg rob_bsy_2_6; // @[rob.scala:309:28]
reg rob_bsy_2_7; // @[rob.scala:309:28]
reg rob_bsy_2_8; // @[rob.scala:309:28]
reg rob_bsy_2_9; // @[rob.scala:309:28]
reg rob_bsy_2_10; // @[rob.scala:309:28]
reg rob_bsy_2_11; // @[rob.scala:309:28]
reg rob_bsy_2_12; // @[rob.scala:309:28]
reg rob_bsy_2_13; // @[rob.scala:309:28]
reg rob_bsy_2_14; // @[rob.scala:309:28]
reg rob_bsy_2_15; // @[rob.scala:309:28]
reg rob_bsy_2_16; // @[rob.scala:309:28]
reg rob_bsy_2_17; // @[rob.scala:309:28]
reg rob_bsy_2_18; // @[rob.scala:309:28]
reg rob_bsy_2_19; // @[rob.scala:309:28]
reg rob_bsy_2_20; // @[rob.scala:309:28]
reg rob_bsy_2_21; // @[rob.scala:309:28]
reg rob_bsy_2_22; // @[rob.scala:309:28]
reg rob_bsy_2_23; // @[rob.scala:309:28]
reg rob_bsy_2_24; // @[rob.scala:309:28]
reg rob_bsy_2_25; // @[rob.scala:309:28]
reg rob_bsy_2_26; // @[rob.scala:309:28]
reg rob_bsy_2_27; // @[rob.scala:309:28]
reg rob_bsy_2_28; // @[rob.scala:309:28]
reg rob_bsy_2_29; // @[rob.scala:309:28]
reg rob_bsy_2_30; // @[rob.scala:309:28]
reg rob_bsy_2_31; // @[rob.scala:309:28]
reg rob_unsafe_2_0; // @[rob.scala:310:28]
reg rob_unsafe_2_1; // @[rob.scala:310:28]
reg rob_unsafe_2_2; // @[rob.scala:310:28]
reg rob_unsafe_2_3; // @[rob.scala:310:28]
reg rob_unsafe_2_4; // @[rob.scala:310:28]
reg rob_unsafe_2_5; // @[rob.scala:310:28]
reg rob_unsafe_2_6; // @[rob.scala:310:28]
reg rob_unsafe_2_7; // @[rob.scala:310:28]
reg rob_unsafe_2_8; // @[rob.scala:310:28]
reg rob_unsafe_2_9; // @[rob.scala:310:28]
reg rob_unsafe_2_10; // @[rob.scala:310:28]
reg rob_unsafe_2_11; // @[rob.scala:310:28]
reg rob_unsafe_2_12; // @[rob.scala:310:28]
reg rob_unsafe_2_13; // @[rob.scala:310:28]
reg rob_unsafe_2_14; // @[rob.scala:310:28]
reg rob_unsafe_2_15; // @[rob.scala:310:28]
reg rob_unsafe_2_16; // @[rob.scala:310:28]
reg rob_unsafe_2_17; // @[rob.scala:310:28]
reg rob_unsafe_2_18; // @[rob.scala:310:28]
reg rob_unsafe_2_19; // @[rob.scala:310:28]
reg rob_unsafe_2_20; // @[rob.scala:310:28]
reg rob_unsafe_2_21; // @[rob.scala:310:28]
reg rob_unsafe_2_22; // @[rob.scala:310:28]
reg rob_unsafe_2_23; // @[rob.scala:310:28]
reg rob_unsafe_2_24; // @[rob.scala:310:28]
reg rob_unsafe_2_25; // @[rob.scala:310:28]
reg rob_unsafe_2_26; // @[rob.scala:310:28]
reg rob_unsafe_2_27; // @[rob.scala:310:28]
reg rob_unsafe_2_28; // @[rob.scala:310:28]
reg rob_unsafe_2_29; // @[rob.scala:310:28]
reg rob_unsafe_2_30; // @[rob.scala:310:28]
reg rob_unsafe_2_31; // @[rob.scala:310:28]
reg [6:0] rob_uop_2_0_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_0_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_0_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_0_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_0_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_0_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_0_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_0_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_0_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_0_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_0_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_0_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_0_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_0_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_0_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_0_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_0_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_0_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_0_is_br; // @[rob.scala:311:28]
reg rob_uop_2_0_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_0_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_0_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_0_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_0_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_0_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_0_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_0_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_0_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_0_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_0_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_0_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_0_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_prs3; // @[rob.scala:311:28]
reg rob_uop_2_0_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_0_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_0_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_0_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_0_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_0_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_0_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_0_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_0_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_0_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_0_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_0_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_0_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_0_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_0_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_0_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_0_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_0_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_0_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_0_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_0_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_0_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_0_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_0_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_0_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_0_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_0_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_0_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_0_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_0_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_0_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_0_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_1_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_1_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_1_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_1_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_1_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_1_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_1_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_1_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_1_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_1_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_1_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_1_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_1_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_1_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_1_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_1_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_1_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_1_is_br; // @[rob.scala:311:28]
reg rob_uop_2_1_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_1_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_1_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_1_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_1_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_1_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_1_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_1_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_1_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_1_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_1_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_1_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_1_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_prs3; // @[rob.scala:311:28]
reg rob_uop_2_1_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_1_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_1_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_1_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_1_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_1_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_1_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_1_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_1_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_1_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_1_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_1_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_1_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_1_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_1_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_1_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_1_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_1_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_1_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_1_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_1_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_1_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_1_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_1_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_1_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_1_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_1_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_1_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_1_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_1_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_1_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_1_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_2_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_2_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_2_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_2_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_2_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_2_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_2_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_2_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_2_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_2_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_2_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_2_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_2_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_2_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_2_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_2_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_2_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_2_is_br; // @[rob.scala:311:28]
reg rob_uop_2_2_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_2_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_2_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_2_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_2_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_2_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_2_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_2_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_2_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_2_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_2_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_2_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_2_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_prs3; // @[rob.scala:311:28]
reg rob_uop_2_2_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_2_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_2_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_2_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_2_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_2_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_2_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_2_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_2_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_2_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_2_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_2_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_2_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_2_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_2_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_2_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_2_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_2_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_2_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_2_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_2_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_2_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_2_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_2_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_2_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_2_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_2_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_2_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_2_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_2_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_2_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_2_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_3_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_3_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_3_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_3_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_3_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_3_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_3_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_3_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_3_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_3_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_3_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_3_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_3_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_3_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_3_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_3_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_3_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_3_is_br; // @[rob.scala:311:28]
reg rob_uop_2_3_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_3_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_3_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_3_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_3_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_3_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_3_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_3_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_3_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_3_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_3_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_3_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_3_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_prs3; // @[rob.scala:311:28]
reg rob_uop_2_3_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_3_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_3_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_3_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_3_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_3_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_3_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_3_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_3_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_3_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_3_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_3_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_3_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_3_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_3_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_3_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_3_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_3_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_3_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_3_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_3_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_3_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_3_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_3_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_3_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_3_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_3_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_3_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_3_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_3_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_3_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_3_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_4_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_4_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_4_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_4_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_4_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_4_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_4_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_4_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_4_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_4_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_4_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_4_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_4_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_4_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_4_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_4_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_4_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_4_is_br; // @[rob.scala:311:28]
reg rob_uop_2_4_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_4_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_4_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_4_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_4_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_4_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_4_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_4_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_4_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_4_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_4_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_4_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_4_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_prs3; // @[rob.scala:311:28]
reg rob_uop_2_4_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_4_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_4_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_4_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_4_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_4_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_4_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_4_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_4_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_4_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_4_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_4_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_4_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_4_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_4_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_4_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_4_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_4_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_4_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_4_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_4_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_4_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_4_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_4_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_4_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_4_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_4_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_4_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_4_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_4_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_4_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_4_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_5_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_5_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_5_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_5_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_5_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_5_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_5_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_5_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_5_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_5_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_5_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_5_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_5_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_5_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_5_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_5_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_5_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_5_is_br; // @[rob.scala:311:28]
reg rob_uop_2_5_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_5_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_5_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_5_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_5_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_5_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_5_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_5_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_5_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_5_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_5_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_5_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_5_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_prs3; // @[rob.scala:311:28]
reg rob_uop_2_5_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_5_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_5_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_5_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_5_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_5_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_5_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_5_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_5_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_5_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_5_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_5_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_5_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_5_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_5_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_5_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_5_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_5_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_5_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_5_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_5_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_5_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_5_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_5_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_5_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_5_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_5_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_5_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_5_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_5_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_5_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_5_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_6_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_6_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_6_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_6_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_6_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_6_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_6_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_6_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_6_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_6_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_6_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_6_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_6_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_6_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_6_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_6_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_6_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_6_is_br; // @[rob.scala:311:28]
reg rob_uop_2_6_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_6_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_6_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_6_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_6_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_6_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_6_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_6_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_6_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_6_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_6_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_6_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_6_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_prs3; // @[rob.scala:311:28]
reg rob_uop_2_6_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_6_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_6_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_6_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_6_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_6_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_6_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_6_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_6_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_6_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_6_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_6_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_6_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_6_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_6_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_6_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_6_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_6_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_6_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_6_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_6_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_6_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_6_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_6_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_6_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_6_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_6_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_6_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_6_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_6_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_6_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_6_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_7_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_7_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_7_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_7_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_7_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_7_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_7_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_7_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_7_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_7_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_7_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_7_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_7_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_7_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_7_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_7_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_7_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_7_is_br; // @[rob.scala:311:28]
reg rob_uop_2_7_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_7_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_7_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_7_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_7_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_7_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_7_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_7_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_7_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_7_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_7_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_7_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_7_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_prs3; // @[rob.scala:311:28]
reg rob_uop_2_7_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_7_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_7_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_7_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_7_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_7_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_7_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_7_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_7_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_7_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_7_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_7_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_7_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_7_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_7_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_7_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_7_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_7_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_7_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_7_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_7_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_7_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_7_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_7_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_7_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_7_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_7_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_7_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_7_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_7_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_7_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_7_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_8_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_8_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_8_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_8_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_8_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_8_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_8_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_8_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_8_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_8_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_8_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_8_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_8_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_8_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_8_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_8_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_8_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_8_is_br; // @[rob.scala:311:28]
reg rob_uop_2_8_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_8_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_8_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_8_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_8_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_8_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_8_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_8_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_8_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_8_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_8_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_8_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_8_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_prs3; // @[rob.scala:311:28]
reg rob_uop_2_8_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_8_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_8_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_8_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_8_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_8_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_8_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_8_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_8_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_8_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_8_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_8_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_8_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_8_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_8_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_8_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_8_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_8_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_8_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_8_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_8_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_8_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_8_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_8_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_8_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_8_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_8_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_8_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_8_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_8_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_8_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_8_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_9_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_9_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_9_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_9_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_9_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_9_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_9_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_9_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_9_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_9_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_9_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_9_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_9_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_9_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_9_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_9_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_9_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_9_is_br; // @[rob.scala:311:28]
reg rob_uop_2_9_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_9_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_9_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_9_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_9_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_9_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_9_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_9_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_9_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_9_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_9_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_9_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_9_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_prs3; // @[rob.scala:311:28]
reg rob_uop_2_9_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_9_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_9_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_9_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_9_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_9_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_9_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_9_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_9_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_9_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_9_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_9_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_9_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_9_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_9_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_9_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_9_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_9_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_9_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_9_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_9_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_9_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_9_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_9_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_9_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_9_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_9_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_9_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_9_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_9_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_9_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_9_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_10_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_10_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_10_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_10_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_10_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_10_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_10_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_10_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_10_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_10_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_10_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_10_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_10_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_10_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_10_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_10_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_10_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_10_is_br; // @[rob.scala:311:28]
reg rob_uop_2_10_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_10_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_10_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_10_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_10_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_10_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_10_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_10_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_10_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_10_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_10_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_10_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_10_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_prs3; // @[rob.scala:311:28]
reg rob_uop_2_10_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_10_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_10_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_10_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_10_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_10_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_10_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_10_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_10_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_10_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_10_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_10_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_10_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_10_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_10_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_10_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_10_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_10_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_10_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_10_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_10_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_10_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_10_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_10_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_10_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_10_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_10_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_10_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_10_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_10_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_10_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_10_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_11_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_11_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_11_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_11_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_11_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_11_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_11_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_11_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_11_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_11_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_11_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_11_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_11_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_11_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_11_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_11_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_11_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_11_is_br; // @[rob.scala:311:28]
reg rob_uop_2_11_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_11_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_11_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_11_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_11_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_11_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_11_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_11_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_11_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_11_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_11_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_11_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_11_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_prs3; // @[rob.scala:311:28]
reg rob_uop_2_11_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_11_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_11_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_11_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_11_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_11_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_11_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_11_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_11_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_11_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_11_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_11_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_11_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_11_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_11_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_11_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_11_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_11_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_11_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_11_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_11_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_11_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_11_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_11_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_11_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_11_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_11_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_11_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_11_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_11_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_11_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_11_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_12_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_12_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_12_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_12_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_12_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_12_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_12_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_12_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_12_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_12_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_12_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_12_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_12_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_12_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_12_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_12_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_12_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_12_is_br; // @[rob.scala:311:28]
reg rob_uop_2_12_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_12_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_12_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_12_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_12_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_12_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_12_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_12_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_12_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_12_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_12_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_12_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_12_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_prs3; // @[rob.scala:311:28]
reg rob_uop_2_12_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_12_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_12_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_12_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_12_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_12_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_12_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_12_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_12_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_12_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_12_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_12_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_12_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_12_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_12_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_12_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_12_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_12_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_12_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_12_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_12_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_12_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_12_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_12_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_12_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_12_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_12_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_12_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_12_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_12_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_12_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_12_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_13_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_13_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_13_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_13_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_13_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_13_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_13_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_13_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_13_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_13_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_13_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_13_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_13_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_13_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_13_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_13_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_13_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_13_is_br; // @[rob.scala:311:28]
reg rob_uop_2_13_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_13_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_13_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_13_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_13_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_13_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_13_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_13_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_13_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_13_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_13_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_13_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_13_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_prs3; // @[rob.scala:311:28]
reg rob_uop_2_13_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_13_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_13_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_13_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_13_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_13_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_13_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_13_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_13_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_13_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_13_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_13_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_13_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_13_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_13_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_13_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_13_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_13_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_13_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_13_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_13_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_13_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_13_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_13_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_13_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_13_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_13_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_13_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_13_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_13_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_13_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_13_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_14_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_14_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_14_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_14_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_14_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_14_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_14_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_14_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_14_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_14_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_14_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_14_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_14_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_14_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_14_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_14_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_14_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_14_is_br; // @[rob.scala:311:28]
reg rob_uop_2_14_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_14_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_14_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_14_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_14_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_14_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_14_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_14_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_14_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_14_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_14_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_14_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_14_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_prs3; // @[rob.scala:311:28]
reg rob_uop_2_14_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_14_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_14_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_14_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_14_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_14_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_14_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_14_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_14_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_14_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_14_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_14_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_14_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_14_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_14_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_14_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_14_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_14_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_14_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_14_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_14_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_14_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_14_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_14_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_14_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_14_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_14_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_14_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_14_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_14_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_14_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_14_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_15_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_15_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_15_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_15_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_15_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_15_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_15_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_15_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_15_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_15_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_15_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_15_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_15_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_15_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_15_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_15_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_15_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_15_is_br; // @[rob.scala:311:28]
reg rob_uop_2_15_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_15_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_15_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_15_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_15_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_15_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_15_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_15_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_15_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_15_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_15_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_15_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_15_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_prs3; // @[rob.scala:311:28]
reg rob_uop_2_15_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_15_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_15_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_15_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_15_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_15_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_15_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_15_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_15_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_15_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_15_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_15_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_15_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_15_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_15_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_15_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_15_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_15_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_15_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_15_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_15_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_15_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_15_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_15_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_15_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_15_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_15_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_15_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_15_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_15_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_15_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_15_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_16_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_16_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_16_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_16_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_16_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_16_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_16_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_16_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_16_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_16_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_16_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_16_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_16_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_16_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_16_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_16_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_16_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_16_is_br; // @[rob.scala:311:28]
reg rob_uop_2_16_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_16_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_16_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_16_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_16_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_16_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_16_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_16_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_16_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_16_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_16_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_16_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_16_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_prs3; // @[rob.scala:311:28]
reg rob_uop_2_16_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_16_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_16_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_16_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_16_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_16_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_16_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_16_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_16_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_16_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_16_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_16_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_16_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_16_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_16_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_16_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_16_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_16_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_16_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_16_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_16_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_16_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_16_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_16_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_16_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_16_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_16_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_16_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_16_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_16_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_16_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_16_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_17_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_17_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_17_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_17_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_17_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_17_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_17_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_17_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_17_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_17_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_17_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_17_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_17_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_17_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_17_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_17_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_17_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_17_is_br; // @[rob.scala:311:28]
reg rob_uop_2_17_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_17_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_17_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_17_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_17_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_17_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_17_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_17_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_17_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_17_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_17_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_17_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_17_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_prs3; // @[rob.scala:311:28]
reg rob_uop_2_17_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_17_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_17_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_17_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_17_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_17_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_17_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_17_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_17_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_17_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_17_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_17_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_17_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_17_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_17_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_17_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_17_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_17_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_17_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_17_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_17_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_17_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_17_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_17_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_17_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_17_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_17_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_17_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_17_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_17_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_17_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_17_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_18_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_18_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_18_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_18_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_18_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_18_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_18_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_18_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_18_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_18_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_18_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_18_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_18_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_18_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_18_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_18_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_18_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_18_is_br; // @[rob.scala:311:28]
reg rob_uop_2_18_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_18_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_18_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_18_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_18_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_18_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_18_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_18_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_18_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_18_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_18_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_18_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_18_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_prs3; // @[rob.scala:311:28]
reg rob_uop_2_18_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_18_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_18_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_18_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_18_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_18_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_18_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_18_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_18_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_18_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_18_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_18_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_18_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_18_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_18_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_18_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_18_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_18_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_18_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_18_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_18_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_18_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_18_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_18_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_18_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_18_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_18_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_18_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_18_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_18_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_18_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_18_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_19_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_19_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_19_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_19_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_19_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_19_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_19_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_19_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_19_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_19_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_19_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_19_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_19_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_19_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_19_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_19_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_19_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_19_is_br; // @[rob.scala:311:28]
reg rob_uop_2_19_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_19_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_19_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_19_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_19_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_19_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_19_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_19_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_19_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_19_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_19_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_19_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_19_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_prs3; // @[rob.scala:311:28]
reg rob_uop_2_19_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_19_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_19_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_19_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_19_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_19_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_19_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_19_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_19_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_19_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_19_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_19_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_19_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_19_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_19_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_19_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_19_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_19_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_19_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_19_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_19_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_19_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_19_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_19_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_19_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_19_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_19_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_19_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_19_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_19_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_19_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_19_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_20_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_20_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_20_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_20_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_20_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_20_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_20_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_20_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_20_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_20_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_20_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_20_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_20_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_20_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_20_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_20_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_20_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_20_is_br; // @[rob.scala:311:28]
reg rob_uop_2_20_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_20_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_20_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_20_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_20_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_20_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_20_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_20_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_20_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_20_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_20_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_20_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_20_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_prs3; // @[rob.scala:311:28]
reg rob_uop_2_20_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_20_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_20_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_20_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_20_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_20_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_20_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_20_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_20_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_20_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_20_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_20_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_20_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_20_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_20_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_20_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_20_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_20_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_20_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_20_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_20_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_20_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_20_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_20_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_20_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_20_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_20_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_20_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_20_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_20_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_20_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_20_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_21_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_21_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_21_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_21_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_21_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_21_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_21_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_21_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_21_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_21_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_21_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_21_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_21_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_21_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_21_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_21_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_21_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_21_is_br; // @[rob.scala:311:28]
reg rob_uop_2_21_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_21_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_21_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_21_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_21_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_21_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_21_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_21_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_21_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_21_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_21_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_21_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_21_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_prs3; // @[rob.scala:311:28]
reg rob_uop_2_21_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_21_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_21_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_21_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_21_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_21_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_21_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_21_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_21_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_21_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_21_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_21_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_21_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_21_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_21_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_21_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_21_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_21_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_21_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_21_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_21_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_21_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_21_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_21_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_21_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_21_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_21_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_21_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_21_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_21_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_21_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_21_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_22_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_22_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_22_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_22_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_22_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_22_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_22_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_22_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_22_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_22_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_22_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_22_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_22_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_22_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_22_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_22_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_22_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_22_is_br; // @[rob.scala:311:28]
reg rob_uop_2_22_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_22_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_22_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_22_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_22_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_22_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_22_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_22_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_22_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_22_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_22_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_22_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_22_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_prs3; // @[rob.scala:311:28]
reg rob_uop_2_22_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_22_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_22_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_22_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_22_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_22_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_22_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_22_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_22_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_22_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_22_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_22_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_22_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_22_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_22_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_22_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_22_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_22_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_22_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_22_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_22_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_22_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_22_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_22_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_22_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_22_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_22_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_22_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_22_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_22_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_22_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_22_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_23_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_23_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_23_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_23_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_23_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_23_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_23_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_23_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_23_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_23_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_23_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_23_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_23_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_23_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_23_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_23_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_23_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_23_is_br; // @[rob.scala:311:28]
reg rob_uop_2_23_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_23_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_23_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_23_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_23_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_23_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_23_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_23_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_23_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_23_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_23_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_23_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_23_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_prs3; // @[rob.scala:311:28]
reg rob_uop_2_23_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_23_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_23_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_23_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_23_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_23_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_23_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_23_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_23_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_23_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_23_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_23_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_23_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_23_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_23_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_23_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_23_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_23_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_23_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_23_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_23_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_23_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_23_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_23_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_23_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_23_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_23_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_23_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_23_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_23_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_23_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_23_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_24_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_24_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_24_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_24_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_24_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_24_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_24_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_24_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_24_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_24_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_24_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_24_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_24_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_24_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_24_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_24_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_24_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_24_is_br; // @[rob.scala:311:28]
reg rob_uop_2_24_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_24_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_24_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_24_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_24_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_24_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_24_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_24_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_24_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_24_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_24_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_24_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_24_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_prs3; // @[rob.scala:311:28]
reg rob_uop_2_24_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_24_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_24_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_24_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_24_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_24_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_24_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_24_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_24_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_24_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_24_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_24_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_24_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_24_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_24_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_24_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_24_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_24_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_24_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_24_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_24_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_24_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_24_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_24_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_24_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_24_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_24_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_24_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_24_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_24_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_24_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_24_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_25_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_25_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_25_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_25_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_25_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_25_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_25_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_25_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_25_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_25_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_25_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_25_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_25_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_25_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_25_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_25_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_25_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_25_is_br; // @[rob.scala:311:28]
reg rob_uop_2_25_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_25_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_25_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_25_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_25_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_25_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_25_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_25_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_25_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_25_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_25_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_25_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_25_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_prs3; // @[rob.scala:311:28]
reg rob_uop_2_25_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_25_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_25_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_25_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_25_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_25_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_25_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_25_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_25_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_25_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_25_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_25_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_25_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_25_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_25_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_25_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_25_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_25_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_25_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_25_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_25_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_25_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_25_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_25_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_25_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_25_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_25_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_25_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_25_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_25_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_25_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_25_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_26_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_26_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_26_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_26_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_26_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_26_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_26_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_26_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_26_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_26_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_26_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_26_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_26_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_26_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_26_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_26_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_26_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_26_is_br; // @[rob.scala:311:28]
reg rob_uop_2_26_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_26_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_26_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_26_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_26_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_26_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_26_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_26_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_26_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_26_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_26_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_26_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_26_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_prs3; // @[rob.scala:311:28]
reg rob_uop_2_26_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_26_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_26_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_26_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_26_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_26_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_26_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_26_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_26_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_26_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_26_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_26_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_26_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_26_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_26_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_26_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_26_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_26_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_26_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_26_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_26_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_26_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_26_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_26_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_26_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_26_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_26_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_26_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_26_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_26_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_26_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_26_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_27_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_27_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_27_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_27_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_27_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_27_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_27_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_27_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_27_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_27_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_27_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_27_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_27_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_27_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_27_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_27_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_27_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_27_is_br; // @[rob.scala:311:28]
reg rob_uop_2_27_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_27_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_27_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_27_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_27_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_27_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_27_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_27_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_27_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_27_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_27_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_27_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_27_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_prs3; // @[rob.scala:311:28]
reg rob_uop_2_27_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_27_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_27_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_27_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_27_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_27_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_27_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_27_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_27_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_27_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_27_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_27_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_27_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_27_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_27_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_27_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_27_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_27_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_27_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_27_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_27_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_27_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_27_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_27_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_27_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_27_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_27_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_27_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_27_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_27_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_27_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_27_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_28_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_28_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_28_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_28_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_28_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_28_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_28_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_28_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_28_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_28_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_28_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_28_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_28_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_28_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_28_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_28_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_28_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_28_is_br; // @[rob.scala:311:28]
reg rob_uop_2_28_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_28_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_28_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_28_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_28_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_28_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_28_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_28_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_28_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_28_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_28_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_28_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_28_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_prs3; // @[rob.scala:311:28]
reg rob_uop_2_28_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_28_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_28_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_28_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_28_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_28_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_28_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_28_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_28_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_28_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_28_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_28_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_28_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_28_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_28_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_28_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_28_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_28_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_28_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_28_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_28_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_28_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_28_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_28_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_28_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_28_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_28_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_28_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_28_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_28_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_28_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_28_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_29_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_29_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_29_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_29_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_29_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_29_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_29_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_29_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_29_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_29_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_29_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_29_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_29_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_29_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_29_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_29_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_29_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_29_is_br; // @[rob.scala:311:28]
reg rob_uop_2_29_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_29_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_29_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_29_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_29_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_29_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_29_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_29_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_29_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_29_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_29_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_29_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_29_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_prs3; // @[rob.scala:311:28]
reg rob_uop_2_29_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_29_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_29_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_29_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_29_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_29_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_29_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_29_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_29_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_29_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_29_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_29_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_29_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_29_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_29_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_29_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_29_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_29_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_29_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_29_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_29_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_29_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_29_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_29_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_29_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_29_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_29_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_29_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_29_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_29_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_29_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_29_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_30_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_30_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_30_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_30_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_30_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_30_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_30_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_30_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_30_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_30_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_30_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_30_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_30_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_30_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_30_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_30_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_30_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_30_is_br; // @[rob.scala:311:28]
reg rob_uop_2_30_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_30_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_30_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_30_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_30_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_30_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_30_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_30_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_30_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_30_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_30_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_30_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_30_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_prs3; // @[rob.scala:311:28]
reg rob_uop_2_30_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_30_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_30_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_30_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_30_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_30_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_30_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_30_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_30_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_30_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_30_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_30_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_30_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_30_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_30_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_30_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_30_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_30_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_30_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_30_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_30_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_30_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_30_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_30_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_30_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_30_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_30_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_30_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_30_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_30_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_30_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_30_debug_tsrc; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_uopc; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_31_inst; // @[rob.scala:311:28]
reg [31:0] rob_uop_2_31_debug_inst; // @[rob.scala:311:28]
reg rob_uop_2_31_is_rvc; // @[rob.scala:311:28]
reg [39:0] rob_uop_2_31_debug_pc; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_31_iq_type; // @[rob.scala:311:28]
reg [9:0] rob_uop_2_31_fu_code; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_31_ctrl_br_type; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_ctrl_op1_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_31_ctrl_op2_sel; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_31_ctrl_imm_sel; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_31_ctrl_op_fcn; // @[rob.scala:311:28]
reg rob_uop_2_31_ctrl_fcn_dw; // @[rob.scala:311:28]
reg [2:0] rob_uop_2_31_ctrl_csr_cmd; // @[rob.scala:311:28]
reg rob_uop_2_31_ctrl_is_load; // @[rob.scala:311:28]
reg rob_uop_2_31_ctrl_is_sta; // @[rob.scala:311:28]
reg rob_uop_2_31_ctrl_is_std; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_iw_state; // @[rob.scala:311:28]
reg rob_uop_2_31_iw_p1_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_31_iw_p2_poisoned; // @[rob.scala:311:28]
reg rob_uop_2_31_is_br; // @[rob.scala:311:28]
reg rob_uop_2_31_is_jalr; // @[rob.scala:311:28]
reg rob_uop_2_31_is_jal; // @[rob.scala:311:28]
reg rob_uop_2_31_is_sfb; // @[rob.scala:311:28]
reg [15:0] rob_uop_2_31_br_mask; // @[rob.scala:311:28]
reg [3:0] rob_uop_2_31_br_tag; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_31_ftq_idx; // @[rob.scala:311:28]
reg rob_uop_2_31_edge_inst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_31_pc_lob; // @[rob.scala:311:28]
reg rob_uop_2_31_taken; // @[rob.scala:311:28]
reg [19:0] rob_uop_2_31_imm_packed; // @[rob.scala:311:28]
reg [11:0] rob_uop_2_31_csr_addr; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_rob_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_31_ldq_idx; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_31_stq_idx; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_rxq_idx; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_pdst; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_prs1; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_prs2; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_prs3; // @[rob.scala:311:28]
reg rob_uop_2_31_prs1_busy; // @[rob.scala:311:28]
reg rob_uop_2_31_prs2_busy; // @[rob.scala:311:28]
reg rob_uop_2_31_prs3_busy; // @[rob.scala:311:28]
reg [6:0] rob_uop_2_31_stale_pdst; // @[rob.scala:311:28]
reg rob_uop_2_31_exception; // @[rob.scala:311:28]
reg [63:0] rob_uop_2_31_exc_cause; // @[rob.scala:311:28]
reg rob_uop_2_31_bypassable; // @[rob.scala:311:28]
reg [4:0] rob_uop_2_31_mem_cmd; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_mem_size; // @[rob.scala:311:28]
reg rob_uop_2_31_mem_signed; // @[rob.scala:311:28]
reg rob_uop_2_31_is_fence; // @[rob.scala:311:28]
reg rob_uop_2_31_is_fencei; // @[rob.scala:311:28]
reg rob_uop_2_31_is_amo; // @[rob.scala:311:28]
reg rob_uop_2_31_uses_ldq; // @[rob.scala:311:28]
reg rob_uop_2_31_uses_stq; // @[rob.scala:311:28]
reg rob_uop_2_31_is_sys_pc2epc; // @[rob.scala:311:28]
reg rob_uop_2_31_is_unique; // @[rob.scala:311:28]
reg rob_uop_2_31_flush_on_commit; // @[rob.scala:311:28]
reg rob_uop_2_31_ldst_is_rs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_31_ldst; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_31_lrs1; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_31_lrs2; // @[rob.scala:311:28]
reg [5:0] rob_uop_2_31_lrs3; // @[rob.scala:311:28]
reg rob_uop_2_31_ldst_val; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_dst_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_lrs1_rtype; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_lrs2_rtype; // @[rob.scala:311:28]
reg rob_uop_2_31_frs3_en; // @[rob.scala:311:28]
reg rob_uop_2_31_fp_val; // @[rob.scala:311:28]
reg rob_uop_2_31_fp_single; // @[rob.scala:311:28]
reg rob_uop_2_31_xcpt_pf_if; // @[rob.scala:311:28]
reg rob_uop_2_31_xcpt_ae_if; // @[rob.scala:311:28]
reg rob_uop_2_31_xcpt_ma_if; // @[rob.scala:311:28]
reg rob_uop_2_31_bp_debug_if; // @[rob.scala:311:28]
reg rob_uop_2_31_bp_xcpt_if; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_debug_fsrc; // @[rob.scala:311:28]
reg [1:0] rob_uop_2_31_debug_tsrc; // @[rob.scala:311:28]
reg rob_exception_2_0; // @[rob.scala:312:28]
reg rob_exception_2_1; // @[rob.scala:312:28]
reg rob_exception_2_2; // @[rob.scala:312:28]
reg rob_exception_2_3; // @[rob.scala:312:28]
reg rob_exception_2_4; // @[rob.scala:312:28]
reg rob_exception_2_5; // @[rob.scala:312:28]
reg rob_exception_2_6; // @[rob.scala:312:28]
reg rob_exception_2_7; // @[rob.scala:312:28]
reg rob_exception_2_8; // @[rob.scala:312:28]
reg rob_exception_2_9; // @[rob.scala:312:28]
reg rob_exception_2_10; // @[rob.scala:312:28]
reg rob_exception_2_11; // @[rob.scala:312:28]
reg rob_exception_2_12; // @[rob.scala:312:28]
reg rob_exception_2_13; // @[rob.scala:312:28]
reg rob_exception_2_14; // @[rob.scala:312:28]
reg rob_exception_2_15; // @[rob.scala:312:28]
reg rob_exception_2_16; // @[rob.scala:312:28]
reg rob_exception_2_17; // @[rob.scala:312:28]
reg rob_exception_2_18; // @[rob.scala:312:28]
reg rob_exception_2_19; // @[rob.scala:312:28]
reg rob_exception_2_20; // @[rob.scala:312:28]
reg rob_exception_2_21; // @[rob.scala:312:28]
reg rob_exception_2_22; // @[rob.scala:312:28]
reg rob_exception_2_23; // @[rob.scala:312:28]
reg rob_exception_2_24; // @[rob.scala:312:28]
reg rob_exception_2_25; // @[rob.scala:312:28]
reg rob_exception_2_26; // @[rob.scala:312:28]
reg rob_exception_2_27; // @[rob.scala:312:28]
reg rob_exception_2_28; // @[rob.scala:312:28]
reg rob_exception_2_29; // @[rob.scala:312:28]
reg rob_exception_2_30; // @[rob.scala:312:28]
reg rob_exception_2_31; // @[rob.scala:312:28]
reg rob_predicated_2_0; // @[rob.scala:313:29]
reg rob_predicated_2_1; // @[rob.scala:313:29]
reg rob_predicated_2_2; // @[rob.scala:313:29]
reg rob_predicated_2_3; // @[rob.scala:313:29]
reg rob_predicated_2_4; // @[rob.scala:313:29]
reg rob_predicated_2_5; // @[rob.scala:313:29]
reg rob_predicated_2_6; // @[rob.scala:313:29]
reg rob_predicated_2_7; // @[rob.scala:313:29]
reg rob_predicated_2_8; // @[rob.scala:313:29]
reg rob_predicated_2_9; // @[rob.scala:313:29]
reg rob_predicated_2_10; // @[rob.scala:313:29]
reg rob_predicated_2_11; // @[rob.scala:313:29]
reg rob_predicated_2_12; // @[rob.scala:313:29]
reg rob_predicated_2_13; // @[rob.scala:313:29]
reg rob_predicated_2_14; // @[rob.scala:313:29]
reg rob_predicated_2_15; // @[rob.scala:313:29]
reg rob_predicated_2_16; // @[rob.scala:313:29]
reg rob_predicated_2_17; // @[rob.scala:313:29]
reg rob_predicated_2_18; // @[rob.scala:313:29]
reg rob_predicated_2_19; // @[rob.scala:313:29]
reg rob_predicated_2_20; // @[rob.scala:313:29]
reg rob_predicated_2_21; // @[rob.scala:313:29]
reg rob_predicated_2_22; // @[rob.scala:313:29]
reg rob_predicated_2_23; // @[rob.scala:313:29]
reg rob_predicated_2_24; // @[rob.scala:313:29]
reg rob_predicated_2_25; // @[rob.scala:313:29]
reg rob_predicated_2_26; // @[rob.scala:313:29]
reg rob_predicated_2_27; // @[rob.scala:313:29]
reg rob_predicated_2_28; // @[rob.scala:313:29]
reg rob_predicated_2_29; // @[rob.scala:313:29]
reg rob_predicated_2_30; // @[rob.scala:313:29]
reg rob_predicated_2_31; // @[rob.scala:313:29]
wire [31:0] _GEN_179 = {{rob_val_2_31}, {rob_val_2_30}, {rob_val_2_29}, {rob_val_2_28}, {rob_val_2_27}, {rob_val_2_26}, {rob_val_2_25}, {rob_val_2_24}, {rob_val_2_23}, {rob_val_2_22}, {rob_val_2_21}, {rob_val_2_20}, {rob_val_2_19}, {rob_val_2_18}, {rob_val_2_17}, {rob_val_2_16}, {rob_val_2_15}, {rob_val_2_14}, {rob_val_2_13}, {rob_val_2_12}, {rob_val_2_11}, {rob_val_2_10}, {rob_val_2_9}, {rob_val_2_8}, {rob_val_2_7}, {rob_val_2_6}, {rob_val_2_5}, {rob_val_2_4}, {rob_val_2_3}, {rob_val_2_2}, {rob_val_2_1}, {rob_val_2_0}}; // @[rob.scala:308:32, :324:31]
assign rob_tail_vals_2 = _GEN_179[rob_tail]; // @[rob.scala:227:29, :248:33, :324:31]
wire _rob_bsy_T_4 = io_enq_uops_2_is_fence_0 | io_enq_uops_2_is_fencei_0; // @[rob.scala:211:7, :325:60]
wire _rob_bsy_T_5 = ~_rob_bsy_T_4; // @[rob.scala:325:{34,60}]
wire _rob_unsafe_T_10 = ~io_enq_uops_2_is_fence_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_11 = io_enq_uops_2_uses_stq_0 & _rob_unsafe_T_10; // @[rob.scala:211:7]
wire _rob_unsafe_T_12 = io_enq_uops_2_uses_ldq_0 | _rob_unsafe_T_11; // @[rob.scala:211:7]
wire _rob_unsafe_T_13 = _rob_unsafe_T_12 | io_enq_uops_2_is_br_0; // @[rob.scala:211:7]
wire _rob_unsafe_T_14 = _rob_unsafe_T_13 | io_enq_uops_2_is_jalr_0; // @[rob.scala:211:7]
wire _T_885 = io_lsu_clr_bsy_0_valid_0 & io_lsu_clr_bsy_0_bits_0[1:0] == 2'h2; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire [31:0] _GEN_180 = {{rob_bsy_2_31}, {rob_bsy_2_30}, {rob_bsy_2_29}, {rob_bsy_2_28}, {rob_bsy_2_27}, {rob_bsy_2_26}, {rob_bsy_2_25}, {rob_bsy_2_24}, {rob_bsy_2_23}, {rob_bsy_2_22}, {rob_bsy_2_21}, {rob_bsy_2_20}, {rob_bsy_2_19}, {rob_bsy_2_18}, {rob_bsy_2_17}, {rob_bsy_2_16}, {rob_bsy_2_15}, {rob_bsy_2_14}, {rob_bsy_2_13}, {rob_bsy_2_12}, {rob_bsy_2_11}, {rob_bsy_2_10}, {rob_bsy_2_9}, {rob_bsy_2_8}, {rob_bsy_2_7}, {rob_bsy_2_6}, {rob_bsy_2_5}, {rob_bsy_2_4}, {rob_bsy_2_3}, {rob_bsy_2_2}, {rob_bsy_2_1}, {rob_bsy_2_0}}; // @[rob.scala:309:28, :366:31]
wire _T_900 = io_lsu_clr_bsy_1_valid_0 & io_lsu_clr_bsy_1_bits_0[1:0] == 2'h2; // @[rob.scala:211:7, :271:36, :305:53, :361:31]
wire _T_929 = io_lxcpt_valid_0 & io_lxcpt_bits_uop_rob_idx_0[1:0] == 2'h2; // @[rob.scala:211:7, :271:36, :305:53, :390:26]
wire _GEN_181 = _T_929 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:211:7, :390:26, :392:{33,66}, :394:15]
wire [31:0] _GEN_182 = {{rob_unsafe_2_31}, {rob_unsafe_2_30}, {rob_unsafe_2_29}, {rob_unsafe_2_28}, {rob_unsafe_2_27}, {rob_unsafe_2_26}, {rob_unsafe_2_25}, {rob_unsafe_2_24}, {rob_unsafe_2_23}, {rob_unsafe_2_22}, {rob_unsafe_2_21}, {rob_unsafe_2_20}, {rob_unsafe_2_19}, {rob_unsafe_2_18}, {rob_unsafe_2_17}, {rob_unsafe_2_16}, {rob_unsafe_2_15}, {rob_unsafe_2_14}, {rob_unsafe_2_13}, {rob_unsafe_2_12}, {rob_unsafe_2_11}, {rob_unsafe_2_10}, {rob_unsafe_2_9}, {rob_unsafe_2_8}, {rob_unsafe_2_7}, {rob_unsafe_2_6}, {rob_unsafe_2_5}, {rob_unsafe_2_4}, {rob_unsafe_2_3}, {rob_unsafe_2_2}, {rob_unsafe_2_1}, {rob_unsafe_2_0}}; // @[rob.scala:310:28, :394:15]
wire _GEN_183 = _GEN_182[io_lxcpt_bits_uop_rob_idx_0[6:2]]; // @[rob.scala:211:7, :267:25, :394:15]
assign rob_head_vals_2 = _GEN_179[rob_head]; // @[rob.scala:223:29, :247:33, :324:31, :402:49]
wire [31:0] _GEN_184 = {{rob_exception_2_31}, {rob_exception_2_30}, {rob_exception_2_29}, {rob_exception_2_28}, {rob_exception_2_27}, {rob_exception_2_26}, {rob_exception_2_25}, {rob_exception_2_24}, {rob_exception_2_23}, {rob_exception_2_22}, {rob_exception_2_21}, {rob_exception_2_20}, {rob_exception_2_19}, {rob_exception_2_18}, {rob_exception_2_17}, {rob_exception_2_16}, {rob_exception_2_15}, {rob_exception_2_14}, {rob_exception_2_13}, {rob_exception_2_12}, {rob_exception_2_11}, {rob_exception_2_10}, {rob_exception_2_9}, {rob_exception_2_8}, {rob_exception_2_7}, {rob_exception_2_6}, {rob_exception_2_5}, {rob_exception_2_4}, {rob_exception_2_3}, {rob_exception_2_2}, {rob_exception_2_1}, {rob_exception_2_0}}; // @[rob.scala:312:28, :402:49]
assign _can_throw_exception_2_T = rob_head_vals_2 & _GEN_184[rob_head]; // @[rob.scala:223:29, :247:33, :402:49]
assign can_throw_exception_2 = _can_throw_exception_2_T; // @[rob.scala:244:33, :402:49]
wire _can_commit_2_T = ~_GEN_180[rob_head]; // @[rob.scala:223:29, :366:31, :408:43]
wire _can_commit_2_T_1 = rob_head_vals_2 & _can_commit_2_T; // @[rob.scala:247:33, :408:{40,43}]
wire _can_commit_2_T_2 = ~io_csr_stall_0; // @[rob.scala:211:7, :408:67]
assign _can_commit_2_T_3 = _can_commit_2_T_1 & _can_commit_2_T_2; // @[rob.scala:408:{40,64,67}]
assign can_commit_2 = _can_commit_2_T_3; // @[rob.scala:243:33, :408:64]
wire [31:0] _GEN_185 = {{rob_predicated_2_31}, {rob_predicated_2_30}, {rob_predicated_2_29}, {rob_predicated_2_28}, {rob_predicated_2_27}, {rob_predicated_2_26}, {rob_predicated_2_25}, {rob_predicated_2_24}, {rob_predicated_2_23}, {rob_predicated_2_22}, {rob_predicated_2_21}, {rob_predicated_2_20}, {rob_predicated_2_19}, {rob_predicated_2_18}, {rob_predicated_2_17}, {rob_predicated_2_16}, {rob_predicated_2_15}, {rob_predicated_2_14}, {rob_predicated_2_13}, {rob_predicated_2_12}, {rob_predicated_2_11}, {rob_predicated_2_10}, {rob_predicated_2_9}, {rob_predicated_2_8}, {rob_predicated_2_7}, {rob_predicated_2_6}, {rob_predicated_2_5}, {rob_predicated_2_4}, {rob_predicated_2_3}, {rob_predicated_2_2}, {rob_predicated_2_1}, {rob_predicated_2_0}}; // @[rob.scala:313:29, :414:51]
wire _io_commit_arch_valids_2_T = ~_GEN_185[com_idx]; // @[rob.scala:235:20, :414:51]
assign _io_commit_arch_valids_2_T_1 = will_commit_2 & _io_commit_arch_valids_2_T; // @[rob.scala:242:33, :414:{48,51}]
assign io_commit_arch_valids_2_0 = _io_commit_arch_valids_2_T_1; // @[rob.scala:211:7, :414:48]
wire [31:0][6:0] _GEN_186 = {{rob_uop_2_31_uopc}, {rob_uop_2_30_uopc}, {rob_uop_2_29_uopc}, {rob_uop_2_28_uopc}, {rob_uop_2_27_uopc}, {rob_uop_2_26_uopc}, {rob_uop_2_25_uopc}, {rob_uop_2_24_uopc}, {rob_uop_2_23_uopc}, {rob_uop_2_22_uopc}, {rob_uop_2_21_uopc}, {rob_uop_2_20_uopc}, {rob_uop_2_19_uopc}, {rob_uop_2_18_uopc}, {rob_uop_2_17_uopc}, {rob_uop_2_16_uopc}, {rob_uop_2_15_uopc}, {rob_uop_2_14_uopc}, {rob_uop_2_13_uopc}, {rob_uop_2_12_uopc}, {rob_uop_2_11_uopc}, {rob_uop_2_10_uopc}, {rob_uop_2_9_uopc}, {rob_uop_2_8_uopc}, {rob_uop_2_7_uopc}, {rob_uop_2_6_uopc}, {rob_uop_2_5_uopc}, {rob_uop_2_4_uopc}, {rob_uop_2_3_uopc}, {rob_uop_2_2_uopc}, {rob_uop_2_1_uopc}, {rob_uop_2_0_uopc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_uopc_0 = _GEN_186[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_187 = {{rob_uop_2_31_inst}, {rob_uop_2_30_inst}, {rob_uop_2_29_inst}, {rob_uop_2_28_inst}, {rob_uop_2_27_inst}, {rob_uop_2_26_inst}, {rob_uop_2_25_inst}, {rob_uop_2_24_inst}, {rob_uop_2_23_inst}, {rob_uop_2_22_inst}, {rob_uop_2_21_inst}, {rob_uop_2_20_inst}, {rob_uop_2_19_inst}, {rob_uop_2_18_inst}, {rob_uop_2_17_inst}, {rob_uop_2_16_inst}, {rob_uop_2_15_inst}, {rob_uop_2_14_inst}, {rob_uop_2_13_inst}, {rob_uop_2_12_inst}, {rob_uop_2_11_inst}, {rob_uop_2_10_inst}, {rob_uop_2_9_inst}, {rob_uop_2_8_inst}, {rob_uop_2_7_inst}, {rob_uop_2_6_inst}, {rob_uop_2_5_inst}, {rob_uop_2_4_inst}, {rob_uop_2_3_inst}, {rob_uop_2_2_inst}, {rob_uop_2_1_inst}, {rob_uop_2_0_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_inst_0 = _GEN_187[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][31:0] _GEN_188 = {{rob_uop_2_31_debug_inst}, {rob_uop_2_30_debug_inst}, {rob_uop_2_29_debug_inst}, {rob_uop_2_28_debug_inst}, {rob_uop_2_27_debug_inst}, {rob_uop_2_26_debug_inst}, {rob_uop_2_25_debug_inst}, {rob_uop_2_24_debug_inst}, {rob_uop_2_23_debug_inst}, {rob_uop_2_22_debug_inst}, {rob_uop_2_21_debug_inst}, {rob_uop_2_20_debug_inst}, {rob_uop_2_19_debug_inst}, {rob_uop_2_18_debug_inst}, {rob_uop_2_17_debug_inst}, {rob_uop_2_16_debug_inst}, {rob_uop_2_15_debug_inst}, {rob_uop_2_14_debug_inst}, {rob_uop_2_13_debug_inst}, {rob_uop_2_12_debug_inst}, {rob_uop_2_11_debug_inst}, {rob_uop_2_10_debug_inst}, {rob_uop_2_9_debug_inst}, {rob_uop_2_8_debug_inst}, {rob_uop_2_7_debug_inst}, {rob_uop_2_6_debug_inst}, {rob_uop_2_5_debug_inst}, {rob_uop_2_4_debug_inst}, {rob_uop_2_3_debug_inst}, {rob_uop_2_2_debug_inst}, {rob_uop_2_1_debug_inst}, {rob_uop_2_0_debug_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_debug_inst_0 = _GEN_188[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_189 = {{rob_uop_2_31_is_rvc}, {rob_uop_2_30_is_rvc}, {rob_uop_2_29_is_rvc}, {rob_uop_2_28_is_rvc}, {rob_uop_2_27_is_rvc}, {rob_uop_2_26_is_rvc}, {rob_uop_2_25_is_rvc}, {rob_uop_2_24_is_rvc}, {rob_uop_2_23_is_rvc}, {rob_uop_2_22_is_rvc}, {rob_uop_2_21_is_rvc}, {rob_uop_2_20_is_rvc}, {rob_uop_2_19_is_rvc}, {rob_uop_2_18_is_rvc}, {rob_uop_2_17_is_rvc}, {rob_uop_2_16_is_rvc}, {rob_uop_2_15_is_rvc}, {rob_uop_2_14_is_rvc}, {rob_uop_2_13_is_rvc}, {rob_uop_2_12_is_rvc}, {rob_uop_2_11_is_rvc}, {rob_uop_2_10_is_rvc}, {rob_uop_2_9_is_rvc}, {rob_uop_2_8_is_rvc}, {rob_uop_2_7_is_rvc}, {rob_uop_2_6_is_rvc}, {rob_uop_2_5_is_rvc}, {rob_uop_2_4_is_rvc}, {rob_uop_2_3_is_rvc}, {rob_uop_2_2_is_rvc}, {rob_uop_2_1_is_rvc}, {rob_uop_2_0_is_rvc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_rvc_0 = _GEN_189[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][39:0] _GEN_190 = {{rob_uop_2_31_debug_pc}, {rob_uop_2_30_debug_pc}, {rob_uop_2_29_debug_pc}, {rob_uop_2_28_debug_pc}, {rob_uop_2_27_debug_pc}, {rob_uop_2_26_debug_pc}, {rob_uop_2_25_debug_pc}, {rob_uop_2_24_debug_pc}, {rob_uop_2_23_debug_pc}, {rob_uop_2_22_debug_pc}, {rob_uop_2_21_debug_pc}, {rob_uop_2_20_debug_pc}, {rob_uop_2_19_debug_pc}, {rob_uop_2_18_debug_pc}, {rob_uop_2_17_debug_pc}, {rob_uop_2_16_debug_pc}, {rob_uop_2_15_debug_pc}, {rob_uop_2_14_debug_pc}, {rob_uop_2_13_debug_pc}, {rob_uop_2_12_debug_pc}, {rob_uop_2_11_debug_pc}, {rob_uop_2_10_debug_pc}, {rob_uop_2_9_debug_pc}, {rob_uop_2_8_debug_pc}, {rob_uop_2_7_debug_pc}, {rob_uop_2_6_debug_pc}, {rob_uop_2_5_debug_pc}, {rob_uop_2_4_debug_pc}, {rob_uop_2_3_debug_pc}, {rob_uop_2_2_debug_pc}, {rob_uop_2_1_debug_pc}, {rob_uop_2_0_debug_pc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_debug_pc_0 = _GEN_190[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_191 = {{rob_uop_2_31_iq_type}, {rob_uop_2_30_iq_type}, {rob_uop_2_29_iq_type}, {rob_uop_2_28_iq_type}, {rob_uop_2_27_iq_type}, {rob_uop_2_26_iq_type}, {rob_uop_2_25_iq_type}, {rob_uop_2_24_iq_type}, {rob_uop_2_23_iq_type}, {rob_uop_2_22_iq_type}, {rob_uop_2_21_iq_type}, {rob_uop_2_20_iq_type}, {rob_uop_2_19_iq_type}, {rob_uop_2_18_iq_type}, {rob_uop_2_17_iq_type}, {rob_uop_2_16_iq_type}, {rob_uop_2_15_iq_type}, {rob_uop_2_14_iq_type}, {rob_uop_2_13_iq_type}, {rob_uop_2_12_iq_type}, {rob_uop_2_11_iq_type}, {rob_uop_2_10_iq_type}, {rob_uop_2_9_iq_type}, {rob_uop_2_8_iq_type}, {rob_uop_2_7_iq_type}, {rob_uop_2_6_iq_type}, {rob_uop_2_5_iq_type}, {rob_uop_2_4_iq_type}, {rob_uop_2_3_iq_type}, {rob_uop_2_2_iq_type}, {rob_uop_2_1_iq_type}, {rob_uop_2_0_iq_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_iq_type_0 = _GEN_191[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][9:0] _GEN_192 = {{rob_uop_2_31_fu_code}, {rob_uop_2_30_fu_code}, {rob_uop_2_29_fu_code}, {rob_uop_2_28_fu_code}, {rob_uop_2_27_fu_code}, {rob_uop_2_26_fu_code}, {rob_uop_2_25_fu_code}, {rob_uop_2_24_fu_code}, {rob_uop_2_23_fu_code}, {rob_uop_2_22_fu_code}, {rob_uop_2_21_fu_code}, {rob_uop_2_20_fu_code}, {rob_uop_2_19_fu_code}, {rob_uop_2_18_fu_code}, {rob_uop_2_17_fu_code}, {rob_uop_2_16_fu_code}, {rob_uop_2_15_fu_code}, {rob_uop_2_14_fu_code}, {rob_uop_2_13_fu_code}, {rob_uop_2_12_fu_code}, {rob_uop_2_11_fu_code}, {rob_uop_2_10_fu_code}, {rob_uop_2_9_fu_code}, {rob_uop_2_8_fu_code}, {rob_uop_2_7_fu_code}, {rob_uop_2_6_fu_code}, {rob_uop_2_5_fu_code}, {rob_uop_2_4_fu_code}, {rob_uop_2_3_fu_code}, {rob_uop_2_2_fu_code}, {rob_uop_2_1_fu_code}, {rob_uop_2_0_fu_code}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_fu_code_0 = _GEN_192[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_193 = {{rob_uop_2_31_ctrl_br_type}, {rob_uop_2_30_ctrl_br_type}, {rob_uop_2_29_ctrl_br_type}, {rob_uop_2_28_ctrl_br_type}, {rob_uop_2_27_ctrl_br_type}, {rob_uop_2_26_ctrl_br_type}, {rob_uop_2_25_ctrl_br_type}, {rob_uop_2_24_ctrl_br_type}, {rob_uop_2_23_ctrl_br_type}, {rob_uop_2_22_ctrl_br_type}, {rob_uop_2_21_ctrl_br_type}, {rob_uop_2_20_ctrl_br_type}, {rob_uop_2_19_ctrl_br_type}, {rob_uop_2_18_ctrl_br_type}, {rob_uop_2_17_ctrl_br_type}, {rob_uop_2_16_ctrl_br_type}, {rob_uop_2_15_ctrl_br_type}, {rob_uop_2_14_ctrl_br_type}, {rob_uop_2_13_ctrl_br_type}, {rob_uop_2_12_ctrl_br_type}, {rob_uop_2_11_ctrl_br_type}, {rob_uop_2_10_ctrl_br_type}, {rob_uop_2_9_ctrl_br_type}, {rob_uop_2_8_ctrl_br_type}, {rob_uop_2_7_ctrl_br_type}, {rob_uop_2_6_ctrl_br_type}, {rob_uop_2_5_ctrl_br_type}, {rob_uop_2_4_ctrl_br_type}, {rob_uop_2_3_ctrl_br_type}, {rob_uop_2_2_ctrl_br_type}, {rob_uop_2_1_ctrl_br_type}, {rob_uop_2_0_ctrl_br_type}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_br_type_0 = _GEN_193[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_194 = {{rob_uop_2_31_ctrl_op1_sel}, {rob_uop_2_30_ctrl_op1_sel}, {rob_uop_2_29_ctrl_op1_sel}, {rob_uop_2_28_ctrl_op1_sel}, {rob_uop_2_27_ctrl_op1_sel}, {rob_uop_2_26_ctrl_op1_sel}, {rob_uop_2_25_ctrl_op1_sel}, {rob_uop_2_24_ctrl_op1_sel}, {rob_uop_2_23_ctrl_op1_sel}, {rob_uop_2_22_ctrl_op1_sel}, {rob_uop_2_21_ctrl_op1_sel}, {rob_uop_2_20_ctrl_op1_sel}, {rob_uop_2_19_ctrl_op1_sel}, {rob_uop_2_18_ctrl_op1_sel}, {rob_uop_2_17_ctrl_op1_sel}, {rob_uop_2_16_ctrl_op1_sel}, {rob_uop_2_15_ctrl_op1_sel}, {rob_uop_2_14_ctrl_op1_sel}, {rob_uop_2_13_ctrl_op1_sel}, {rob_uop_2_12_ctrl_op1_sel}, {rob_uop_2_11_ctrl_op1_sel}, {rob_uop_2_10_ctrl_op1_sel}, {rob_uop_2_9_ctrl_op1_sel}, {rob_uop_2_8_ctrl_op1_sel}, {rob_uop_2_7_ctrl_op1_sel}, {rob_uop_2_6_ctrl_op1_sel}, {rob_uop_2_5_ctrl_op1_sel}, {rob_uop_2_4_ctrl_op1_sel}, {rob_uop_2_3_ctrl_op1_sel}, {rob_uop_2_2_ctrl_op1_sel}, {rob_uop_2_1_ctrl_op1_sel}, {rob_uop_2_0_ctrl_op1_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_op1_sel_0 = _GEN_194[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_195 = {{rob_uop_2_31_ctrl_op2_sel}, {rob_uop_2_30_ctrl_op2_sel}, {rob_uop_2_29_ctrl_op2_sel}, {rob_uop_2_28_ctrl_op2_sel}, {rob_uop_2_27_ctrl_op2_sel}, {rob_uop_2_26_ctrl_op2_sel}, {rob_uop_2_25_ctrl_op2_sel}, {rob_uop_2_24_ctrl_op2_sel}, {rob_uop_2_23_ctrl_op2_sel}, {rob_uop_2_22_ctrl_op2_sel}, {rob_uop_2_21_ctrl_op2_sel}, {rob_uop_2_20_ctrl_op2_sel}, {rob_uop_2_19_ctrl_op2_sel}, {rob_uop_2_18_ctrl_op2_sel}, {rob_uop_2_17_ctrl_op2_sel}, {rob_uop_2_16_ctrl_op2_sel}, {rob_uop_2_15_ctrl_op2_sel}, {rob_uop_2_14_ctrl_op2_sel}, {rob_uop_2_13_ctrl_op2_sel}, {rob_uop_2_12_ctrl_op2_sel}, {rob_uop_2_11_ctrl_op2_sel}, {rob_uop_2_10_ctrl_op2_sel}, {rob_uop_2_9_ctrl_op2_sel}, {rob_uop_2_8_ctrl_op2_sel}, {rob_uop_2_7_ctrl_op2_sel}, {rob_uop_2_6_ctrl_op2_sel}, {rob_uop_2_5_ctrl_op2_sel}, {rob_uop_2_4_ctrl_op2_sel}, {rob_uop_2_3_ctrl_op2_sel}, {rob_uop_2_2_ctrl_op2_sel}, {rob_uop_2_1_ctrl_op2_sel}, {rob_uop_2_0_ctrl_op2_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_op2_sel_0 = _GEN_195[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_196 = {{rob_uop_2_31_ctrl_imm_sel}, {rob_uop_2_30_ctrl_imm_sel}, {rob_uop_2_29_ctrl_imm_sel}, {rob_uop_2_28_ctrl_imm_sel}, {rob_uop_2_27_ctrl_imm_sel}, {rob_uop_2_26_ctrl_imm_sel}, {rob_uop_2_25_ctrl_imm_sel}, {rob_uop_2_24_ctrl_imm_sel}, {rob_uop_2_23_ctrl_imm_sel}, {rob_uop_2_22_ctrl_imm_sel}, {rob_uop_2_21_ctrl_imm_sel}, {rob_uop_2_20_ctrl_imm_sel}, {rob_uop_2_19_ctrl_imm_sel}, {rob_uop_2_18_ctrl_imm_sel}, {rob_uop_2_17_ctrl_imm_sel}, {rob_uop_2_16_ctrl_imm_sel}, {rob_uop_2_15_ctrl_imm_sel}, {rob_uop_2_14_ctrl_imm_sel}, {rob_uop_2_13_ctrl_imm_sel}, {rob_uop_2_12_ctrl_imm_sel}, {rob_uop_2_11_ctrl_imm_sel}, {rob_uop_2_10_ctrl_imm_sel}, {rob_uop_2_9_ctrl_imm_sel}, {rob_uop_2_8_ctrl_imm_sel}, {rob_uop_2_7_ctrl_imm_sel}, {rob_uop_2_6_ctrl_imm_sel}, {rob_uop_2_5_ctrl_imm_sel}, {rob_uop_2_4_ctrl_imm_sel}, {rob_uop_2_3_ctrl_imm_sel}, {rob_uop_2_2_ctrl_imm_sel}, {rob_uop_2_1_ctrl_imm_sel}, {rob_uop_2_0_ctrl_imm_sel}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_imm_sel_0 = _GEN_196[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_197 = {{rob_uop_2_31_ctrl_op_fcn}, {rob_uop_2_30_ctrl_op_fcn}, {rob_uop_2_29_ctrl_op_fcn}, {rob_uop_2_28_ctrl_op_fcn}, {rob_uop_2_27_ctrl_op_fcn}, {rob_uop_2_26_ctrl_op_fcn}, {rob_uop_2_25_ctrl_op_fcn}, {rob_uop_2_24_ctrl_op_fcn}, {rob_uop_2_23_ctrl_op_fcn}, {rob_uop_2_22_ctrl_op_fcn}, {rob_uop_2_21_ctrl_op_fcn}, {rob_uop_2_20_ctrl_op_fcn}, {rob_uop_2_19_ctrl_op_fcn}, {rob_uop_2_18_ctrl_op_fcn}, {rob_uop_2_17_ctrl_op_fcn}, {rob_uop_2_16_ctrl_op_fcn}, {rob_uop_2_15_ctrl_op_fcn}, {rob_uop_2_14_ctrl_op_fcn}, {rob_uop_2_13_ctrl_op_fcn}, {rob_uop_2_12_ctrl_op_fcn}, {rob_uop_2_11_ctrl_op_fcn}, {rob_uop_2_10_ctrl_op_fcn}, {rob_uop_2_9_ctrl_op_fcn}, {rob_uop_2_8_ctrl_op_fcn}, {rob_uop_2_7_ctrl_op_fcn}, {rob_uop_2_6_ctrl_op_fcn}, {rob_uop_2_5_ctrl_op_fcn}, {rob_uop_2_4_ctrl_op_fcn}, {rob_uop_2_3_ctrl_op_fcn}, {rob_uop_2_2_ctrl_op_fcn}, {rob_uop_2_1_ctrl_op_fcn}, {rob_uop_2_0_ctrl_op_fcn}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_op_fcn_0 = _GEN_197[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_198 = {{rob_uop_2_31_ctrl_fcn_dw}, {rob_uop_2_30_ctrl_fcn_dw}, {rob_uop_2_29_ctrl_fcn_dw}, {rob_uop_2_28_ctrl_fcn_dw}, {rob_uop_2_27_ctrl_fcn_dw}, {rob_uop_2_26_ctrl_fcn_dw}, {rob_uop_2_25_ctrl_fcn_dw}, {rob_uop_2_24_ctrl_fcn_dw}, {rob_uop_2_23_ctrl_fcn_dw}, {rob_uop_2_22_ctrl_fcn_dw}, {rob_uop_2_21_ctrl_fcn_dw}, {rob_uop_2_20_ctrl_fcn_dw}, {rob_uop_2_19_ctrl_fcn_dw}, {rob_uop_2_18_ctrl_fcn_dw}, {rob_uop_2_17_ctrl_fcn_dw}, {rob_uop_2_16_ctrl_fcn_dw}, {rob_uop_2_15_ctrl_fcn_dw}, {rob_uop_2_14_ctrl_fcn_dw}, {rob_uop_2_13_ctrl_fcn_dw}, {rob_uop_2_12_ctrl_fcn_dw}, {rob_uop_2_11_ctrl_fcn_dw}, {rob_uop_2_10_ctrl_fcn_dw}, {rob_uop_2_9_ctrl_fcn_dw}, {rob_uop_2_8_ctrl_fcn_dw}, {rob_uop_2_7_ctrl_fcn_dw}, {rob_uop_2_6_ctrl_fcn_dw}, {rob_uop_2_5_ctrl_fcn_dw}, {rob_uop_2_4_ctrl_fcn_dw}, {rob_uop_2_3_ctrl_fcn_dw}, {rob_uop_2_2_ctrl_fcn_dw}, {rob_uop_2_1_ctrl_fcn_dw}, {rob_uop_2_0_ctrl_fcn_dw}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_fcn_dw_0 = _GEN_198[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][2:0] _GEN_199 = {{rob_uop_2_31_ctrl_csr_cmd}, {rob_uop_2_30_ctrl_csr_cmd}, {rob_uop_2_29_ctrl_csr_cmd}, {rob_uop_2_28_ctrl_csr_cmd}, {rob_uop_2_27_ctrl_csr_cmd}, {rob_uop_2_26_ctrl_csr_cmd}, {rob_uop_2_25_ctrl_csr_cmd}, {rob_uop_2_24_ctrl_csr_cmd}, {rob_uop_2_23_ctrl_csr_cmd}, {rob_uop_2_22_ctrl_csr_cmd}, {rob_uop_2_21_ctrl_csr_cmd}, {rob_uop_2_20_ctrl_csr_cmd}, {rob_uop_2_19_ctrl_csr_cmd}, {rob_uop_2_18_ctrl_csr_cmd}, {rob_uop_2_17_ctrl_csr_cmd}, {rob_uop_2_16_ctrl_csr_cmd}, {rob_uop_2_15_ctrl_csr_cmd}, {rob_uop_2_14_ctrl_csr_cmd}, {rob_uop_2_13_ctrl_csr_cmd}, {rob_uop_2_12_ctrl_csr_cmd}, {rob_uop_2_11_ctrl_csr_cmd}, {rob_uop_2_10_ctrl_csr_cmd}, {rob_uop_2_9_ctrl_csr_cmd}, {rob_uop_2_8_ctrl_csr_cmd}, {rob_uop_2_7_ctrl_csr_cmd}, {rob_uop_2_6_ctrl_csr_cmd}, {rob_uop_2_5_ctrl_csr_cmd}, {rob_uop_2_4_ctrl_csr_cmd}, {rob_uop_2_3_ctrl_csr_cmd}, {rob_uop_2_2_ctrl_csr_cmd}, {rob_uop_2_1_ctrl_csr_cmd}, {rob_uop_2_0_ctrl_csr_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_csr_cmd_0 = _GEN_199[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_200 = {{rob_uop_2_31_ctrl_is_load}, {rob_uop_2_30_ctrl_is_load}, {rob_uop_2_29_ctrl_is_load}, {rob_uop_2_28_ctrl_is_load}, {rob_uop_2_27_ctrl_is_load}, {rob_uop_2_26_ctrl_is_load}, {rob_uop_2_25_ctrl_is_load}, {rob_uop_2_24_ctrl_is_load}, {rob_uop_2_23_ctrl_is_load}, {rob_uop_2_22_ctrl_is_load}, {rob_uop_2_21_ctrl_is_load}, {rob_uop_2_20_ctrl_is_load}, {rob_uop_2_19_ctrl_is_load}, {rob_uop_2_18_ctrl_is_load}, {rob_uop_2_17_ctrl_is_load}, {rob_uop_2_16_ctrl_is_load}, {rob_uop_2_15_ctrl_is_load}, {rob_uop_2_14_ctrl_is_load}, {rob_uop_2_13_ctrl_is_load}, {rob_uop_2_12_ctrl_is_load}, {rob_uop_2_11_ctrl_is_load}, {rob_uop_2_10_ctrl_is_load}, {rob_uop_2_9_ctrl_is_load}, {rob_uop_2_8_ctrl_is_load}, {rob_uop_2_7_ctrl_is_load}, {rob_uop_2_6_ctrl_is_load}, {rob_uop_2_5_ctrl_is_load}, {rob_uop_2_4_ctrl_is_load}, {rob_uop_2_3_ctrl_is_load}, {rob_uop_2_2_ctrl_is_load}, {rob_uop_2_1_ctrl_is_load}, {rob_uop_2_0_ctrl_is_load}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_is_load_0 = _GEN_200[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_201 = {{rob_uop_2_31_ctrl_is_sta}, {rob_uop_2_30_ctrl_is_sta}, {rob_uop_2_29_ctrl_is_sta}, {rob_uop_2_28_ctrl_is_sta}, {rob_uop_2_27_ctrl_is_sta}, {rob_uop_2_26_ctrl_is_sta}, {rob_uop_2_25_ctrl_is_sta}, {rob_uop_2_24_ctrl_is_sta}, {rob_uop_2_23_ctrl_is_sta}, {rob_uop_2_22_ctrl_is_sta}, {rob_uop_2_21_ctrl_is_sta}, {rob_uop_2_20_ctrl_is_sta}, {rob_uop_2_19_ctrl_is_sta}, {rob_uop_2_18_ctrl_is_sta}, {rob_uop_2_17_ctrl_is_sta}, {rob_uop_2_16_ctrl_is_sta}, {rob_uop_2_15_ctrl_is_sta}, {rob_uop_2_14_ctrl_is_sta}, {rob_uop_2_13_ctrl_is_sta}, {rob_uop_2_12_ctrl_is_sta}, {rob_uop_2_11_ctrl_is_sta}, {rob_uop_2_10_ctrl_is_sta}, {rob_uop_2_9_ctrl_is_sta}, {rob_uop_2_8_ctrl_is_sta}, {rob_uop_2_7_ctrl_is_sta}, {rob_uop_2_6_ctrl_is_sta}, {rob_uop_2_5_ctrl_is_sta}, {rob_uop_2_4_ctrl_is_sta}, {rob_uop_2_3_ctrl_is_sta}, {rob_uop_2_2_ctrl_is_sta}, {rob_uop_2_1_ctrl_is_sta}, {rob_uop_2_0_ctrl_is_sta}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_is_sta_0 = _GEN_201[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_202 = {{rob_uop_2_31_ctrl_is_std}, {rob_uop_2_30_ctrl_is_std}, {rob_uop_2_29_ctrl_is_std}, {rob_uop_2_28_ctrl_is_std}, {rob_uop_2_27_ctrl_is_std}, {rob_uop_2_26_ctrl_is_std}, {rob_uop_2_25_ctrl_is_std}, {rob_uop_2_24_ctrl_is_std}, {rob_uop_2_23_ctrl_is_std}, {rob_uop_2_22_ctrl_is_std}, {rob_uop_2_21_ctrl_is_std}, {rob_uop_2_20_ctrl_is_std}, {rob_uop_2_19_ctrl_is_std}, {rob_uop_2_18_ctrl_is_std}, {rob_uop_2_17_ctrl_is_std}, {rob_uop_2_16_ctrl_is_std}, {rob_uop_2_15_ctrl_is_std}, {rob_uop_2_14_ctrl_is_std}, {rob_uop_2_13_ctrl_is_std}, {rob_uop_2_12_ctrl_is_std}, {rob_uop_2_11_ctrl_is_std}, {rob_uop_2_10_ctrl_is_std}, {rob_uop_2_9_ctrl_is_std}, {rob_uop_2_8_ctrl_is_std}, {rob_uop_2_7_ctrl_is_std}, {rob_uop_2_6_ctrl_is_std}, {rob_uop_2_5_ctrl_is_std}, {rob_uop_2_4_ctrl_is_std}, {rob_uop_2_3_ctrl_is_std}, {rob_uop_2_2_ctrl_is_std}, {rob_uop_2_1_ctrl_is_std}, {rob_uop_2_0_ctrl_is_std}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ctrl_is_std_0 = _GEN_202[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_203 = {{rob_uop_2_31_iw_state}, {rob_uop_2_30_iw_state}, {rob_uop_2_29_iw_state}, {rob_uop_2_28_iw_state}, {rob_uop_2_27_iw_state}, {rob_uop_2_26_iw_state}, {rob_uop_2_25_iw_state}, {rob_uop_2_24_iw_state}, {rob_uop_2_23_iw_state}, {rob_uop_2_22_iw_state}, {rob_uop_2_21_iw_state}, {rob_uop_2_20_iw_state}, {rob_uop_2_19_iw_state}, {rob_uop_2_18_iw_state}, {rob_uop_2_17_iw_state}, {rob_uop_2_16_iw_state}, {rob_uop_2_15_iw_state}, {rob_uop_2_14_iw_state}, {rob_uop_2_13_iw_state}, {rob_uop_2_12_iw_state}, {rob_uop_2_11_iw_state}, {rob_uop_2_10_iw_state}, {rob_uop_2_9_iw_state}, {rob_uop_2_8_iw_state}, {rob_uop_2_7_iw_state}, {rob_uop_2_6_iw_state}, {rob_uop_2_5_iw_state}, {rob_uop_2_4_iw_state}, {rob_uop_2_3_iw_state}, {rob_uop_2_2_iw_state}, {rob_uop_2_1_iw_state}, {rob_uop_2_0_iw_state}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_iw_state_0 = _GEN_203[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_204 = {{rob_uop_2_31_iw_p1_poisoned}, {rob_uop_2_30_iw_p1_poisoned}, {rob_uop_2_29_iw_p1_poisoned}, {rob_uop_2_28_iw_p1_poisoned}, {rob_uop_2_27_iw_p1_poisoned}, {rob_uop_2_26_iw_p1_poisoned}, {rob_uop_2_25_iw_p1_poisoned}, {rob_uop_2_24_iw_p1_poisoned}, {rob_uop_2_23_iw_p1_poisoned}, {rob_uop_2_22_iw_p1_poisoned}, {rob_uop_2_21_iw_p1_poisoned}, {rob_uop_2_20_iw_p1_poisoned}, {rob_uop_2_19_iw_p1_poisoned}, {rob_uop_2_18_iw_p1_poisoned}, {rob_uop_2_17_iw_p1_poisoned}, {rob_uop_2_16_iw_p1_poisoned}, {rob_uop_2_15_iw_p1_poisoned}, {rob_uop_2_14_iw_p1_poisoned}, {rob_uop_2_13_iw_p1_poisoned}, {rob_uop_2_12_iw_p1_poisoned}, {rob_uop_2_11_iw_p1_poisoned}, {rob_uop_2_10_iw_p1_poisoned}, {rob_uop_2_9_iw_p1_poisoned}, {rob_uop_2_8_iw_p1_poisoned}, {rob_uop_2_7_iw_p1_poisoned}, {rob_uop_2_6_iw_p1_poisoned}, {rob_uop_2_5_iw_p1_poisoned}, {rob_uop_2_4_iw_p1_poisoned}, {rob_uop_2_3_iw_p1_poisoned}, {rob_uop_2_2_iw_p1_poisoned}, {rob_uop_2_1_iw_p1_poisoned}, {rob_uop_2_0_iw_p1_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_iw_p1_poisoned_0 = _GEN_204[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_205 = {{rob_uop_2_31_iw_p2_poisoned}, {rob_uop_2_30_iw_p2_poisoned}, {rob_uop_2_29_iw_p2_poisoned}, {rob_uop_2_28_iw_p2_poisoned}, {rob_uop_2_27_iw_p2_poisoned}, {rob_uop_2_26_iw_p2_poisoned}, {rob_uop_2_25_iw_p2_poisoned}, {rob_uop_2_24_iw_p2_poisoned}, {rob_uop_2_23_iw_p2_poisoned}, {rob_uop_2_22_iw_p2_poisoned}, {rob_uop_2_21_iw_p2_poisoned}, {rob_uop_2_20_iw_p2_poisoned}, {rob_uop_2_19_iw_p2_poisoned}, {rob_uop_2_18_iw_p2_poisoned}, {rob_uop_2_17_iw_p2_poisoned}, {rob_uop_2_16_iw_p2_poisoned}, {rob_uop_2_15_iw_p2_poisoned}, {rob_uop_2_14_iw_p2_poisoned}, {rob_uop_2_13_iw_p2_poisoned}, {rob_uop_2_12_iw_p2_poisoned}, {rob_uop_2_11_iw_p2_poisoned}, {rob_uop_2_10_iw_p2_poisoned}, {rob_uop_2_9_iw_p2_poisoned}, {rob_uop_2_8_iw_p2_poisoned}, {rob_uop_2_7_iw_p2_poisoned}, {rob_uop_2_6_iw_p2_poisoned}, {rob_uop_2_5_iw_p2_poisoned}, {rob_uop_2_4_iw_p2_poisoned}, {rob_uop_2_3_iw_p2_poisoned}, {rob_uop_2_2_iw_p2_poisoned}, {rob_uop_2_1_iw_p2_poisoned}, {rob_uop_2_0_iw_p2_poisoned}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_iw_p2_poisoned_0 = _GEN_205[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_206 = {{rob_uop_2_31_is_br}, {rob_uop_2_30_is_br}, {rob_uop_2_29_is_br}, {rob_uop_2_28_is_br}, {rob_uop_2_27_is_br}, {rob_uop_2_26_is_br}, {rob_uop_2_25_is_br}, {rob_uop_2_24_is_br}, {rob_uop_2_23_is_br}, {rob_uop_2_22_is_br}, {rob_uop_2_21_is_br}, {rob_uop_2_20_is_br}, {rob_uop_2_19_is_br}, {rob_uop_2_18_is_br}, {rob_uop_2_17_is_br}, {rob_uop_2_16_is_br}, {rob_uop_2_15_is_br}, {rob_uop_2_14_is_br}, {rob_uop_2_13_is_br}, {rob_uop_2_12_is_br}, {rob_uop_2_11_is_br}, {rob_uop_2_10_is_br}, {rob_uop_2_9_is_br}, {rob_uop_2_8_is_br}, {rob_uop_2_7_is_br}, {rob_uop_2_6_is_br}, {rob_uop_2_5_is_br}, {rob_uop_2_4_is_br}, {rob_uop_2_3_is_br}, {rob_uop_2_2_is_br}, {rob_uop_2_1_is_br}, {rob_uop_2_0_is_br}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_br_0 = _GEN_206[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_207 = {{rob_uop_2_31_is_jalr}, {rob_uop_2_30_is_jalr}, {rob_uop_2_29_is_jalr}, {rob_uop_2_28_is_jalr}, {rob_uop_2_27_is_jalr}, {rob_uop_2_26_is_jalr}, {rob_uop_2_25_is_jalr}, {rob_uop_2_24_is_jalr}, {rob_uop_2_23_is_jalr}, {rob_uop_2_22_is_jalr}, {rob_uop_2_21_is_jalr}, {rob_uop_2_20_is_jalr}, {rob_uop_2_19_is_jalr}, {rob_uop_2_18_is_jalr}, {rob_uop_2_17_is_jalr}, {rob_uop_2_16_is_jalr}, {rob_uop_2_15_is_jalr}, {rob_uop_2_14_is_jalr}, {rob_uop_2_13_is_jalr}, {rob_uop_2_12_is_jalr}, {rob_uop_2_11_is_jalr}, {rob_uop_2_10_is_jalr}, {rob_uop_2_9_is_jalr}, {rob_uop_2_8_is_jalr}, {rob_uop_2_7_is_jalr}, {rob_uop_2_6_is_jalr}, {rob_uop_2_5_is_jalr}, {rob_uop_2_4_is_jalr}, {rob_uop_2_3_is_jalr}, {rob_uop_2_2_is_jalr}, {rob_uop_2_1_is_jalr}, {rob_uop_2_0_is_jalr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_jalr_0 = _GEN_207[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_208 = {{rob_uop_2_31_is_jal}, {rob_uop_2_30_is_jal}, {rob_uop_2_29_is_jal}, {rob_uop_2_28_is_jal}, {rob_uop_2_27_is_jal}, {rob_uop_2_26_is_jal}, {rob_uop_2_25_is_jal}, {rob_uop_2_24_is_jal}, {rob_uop_2_23_is_jal}, {rob_uop_2_22_is_jal}, {rob_uop_2_21_is_jal}, {rob_uop_2_20_is_jal}, {rob_uop_2_19_is_jal}, {rob_uop_2_18_is_jal}, {rob_uop_2_17_is_jal}, {rob_uop_2_16_is_jal}, {rob_uop_2_15_is_jal}, {rob_uop_2_14_is_jal}, {rob_uop_2_13_is_jal}, {rob_uop_2_12_is_jal}, {rob_uop_2_11_is_jal}, {rob_uop_2_10_is_jal}, {rob_uop_2_9_is_jal}, {rob_uop_2_8_is_jal}, {rob_uop_2_7_is_jal}, {rob_uop_2_6_is_jal}, {rob_uop_2_5_is_jal}, {rob_uop_2_4_is_jal}, {rob_uop_2_3_is_jal}, {rob_uop_2_2_is_jal}, {rob_uop_2_1_is_jal}, {rob_uop_2_0_is_jal}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_jal_0 = _GEN_208[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_209 = {{rob_uop_2_31_is_sfb}, {rob_uop_2_30_is_sfb}, {rob_uop_2_29_is_sfb}, {rob_uop_2_28_is_sfb}, {rob_uop_2_27_is_sfb}, {rob_uop_2_26_is_sfb}, {rob_uop_2_25_is_sfb}, {rob_uop_2_24_is_sfb}, {rob_uop_2_23_is_sfb}, {rob_uop_2_22_is_sfb}, {rob_uop_2_21_is_sfb}, {rob_uop_2_20_is_sfb}, {rob_uop_2_19_is_sfb}, {rob_uop_2_18_is_sfb}, {rob_uop_2_17_is_sfb}, {rob_uop_2_16_is_sfb}, {rob_uop_2_15_is_sfb}, {rob_uop_2_14_is_sfb}, {rob_uop_2_13_is_sfb}, {rob_uop_2_12_is_sfb}, {rob_uop_2_11_is_sfb}, {rob_uop_2_10_is_sfb}, {rob_uop_2_9_is_sfb}, {rob_uop_2_8_is_sfb}, {rob_uop_2_7_is_sfb}, {rob_uop_2_6_is_sfb}, {rob_uop_2_5_is_sfb}, {rob_uop_2_4_is_sfb}, {rob_uop_2_3_is_sfb}, {rob_uop_2_2_is_sfb}, {rob_uop_2_1_is_sfb}, {rob_uop_2_0_is_sfb}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_sfb_0 = _GEN_209[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][15:0] _GEN_210 = {{rob_uop_2_31_br_mask}, {rob_uop_2_30_br_mask}, {rob_uop_2_29_br_mask}, {rob_uop_2_28_br_mask}, {rob_uop_2_27_br_mask}, {rob_uop_2_26_br_mask}, {rob_uop_2_25_br_mask}, {rob_uop_2_24_br_mask}, {rob_uop_2_23_br_mask}, {rob_uop_2_22_br_mask}, {rob_uop_2_21_br_mask}, {rob_uop_2_20_br_mask}, {rob_uop_2_19_br_mask}, {rob_uop_2_18_br_mask}, {rob_uop_2_17_br_mask}, {rob_uop_2_16_br_mask}, {rob_uop_2_15_br_mask}, {rob_uop_2_14_br_mask}, {rob_uop_2_13_br_mask}, {rob_uop_2_12_br_mask}, {rob_uop_2_11_br_mask}, {rob_uop_2_10_br_mask}, {rob_uop_2_9_br_mask}, {rob_uop_2_8_br_mask}, {rob_uop_2_7_br_mask}, {rob_uop_2_6_br_mask}, {rob_uop_2_5_br_mask}, {rob_uop_2_4_br_mask}, {rob_uop_2_3_br_mask}, {rob_uop_2_2_br_mask}, {rob_uop_2_1_br_mask}, {rob_uop_2_0_br_mask}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_br_mask_0 = _GEN_210[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][3:0] _GEN_211 = {{rob_uop_2_31_br_tag}, {rob_uop_2_30_br_tag}, {rob_uop_2_29_br_tag}, {rob_uop_2_28_br_tag}, {rob_uop_2_27_br_tag}, {rob_uop_2_26_br_tag}, {rob_uop_2_25_br_tag}, {rob_uop_2_24_br_tag}, {rob_uop_2_23_br_tag}, {rob_uop_2_22_br_tag}, {rob_uop_2_21_br_tag}, {rob_uop_2_20_br_tag}, {rob_uop_2_19_br_tag}, {rob_uop_2_18_br_tag}, {rob_uop_2_17_br_tag}, {rob_uop_2_16_br_tag}, {rob_uop_2_15_br_tag}, {rob_uop_2_14_br_tag}, {rob_uop_2_13_br_tag}, {rob_uop_2_12_br_tag}, {rob_uop_2_11_br_tag}, {rob_uop_2_10_br_tag}, {rob_uop_2_9_br_tag}, {rob_uop_2_8_br_tag}, {rob_uop_2_7_br_tag}, {rob_uop_2_6_br_tag}, {rob_uop_2_5_br_tag}, {rob_uop_2_4_br_tag}, {rob_uop_2_3_br_tag}, {rob_uop_2_2_br_tag}, {rob_uop_2_1_br_tag}, {rob_uop_2_0_br_tag}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_br_tag_0 = _GEN_211[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_212 = {{rob_uop_2_31_ftq_idx}, {rob_uop_2_30_ftq_idx}, {rob_uop_2_29_ftq_idx}, {rob_uop_2_28_ftq_idx}, {rob_uop_2_27_ftq_idx}, {rob_uop_2_26_ftq_idx}, {rob_uop_2_25_ftq_idx}, {rob_uop_2_24_ftq_idx}, {rob_uop_2_23_ftq_idx}, {rob_uop_2_22_ftq_idx}, {rob_uop_2_21_ftq_idx}, {rob_uop_2_20_ftq_idx}, {rob_uop_2_19_ftq_idx}, {rob_uop_2_18_ftq_idx}, {rob_uop_2_17_ftq_idx}, {rob_uop_2_16_ftq_idx}, {rob_uop_2_15_ftq_idx}, {rob_uop_2_14_ftq_idx}, {rob_uop_2_13_ftq_idx}, {rob_uop_2_12_ftq_idx}, {rob_uop_2_11_ftq_idx}, {rob_uop_2_10_ftq_idx}, {rob_uop_2_9_ftq_idx}, {rob_uop_2_8_ftq_idx}, {rob_uop_2_7_ftq_idx}, {rob_uop_2_6_ftq_idx}, {rob_uop_2_5_ftq_idx}, {rob_uop_2_4_ftq_idx}, {rob_uop_2_3_ftq_idx}, {rob_uop_2_2_ftq_idx}, {rob_uop_2_1_ftq_idx}, {rob_uop_2_0_ftq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ftq_idx_0 = _GEN_212[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_213 = {{rob_uop_2_31_edge_inst}, {rob_uop_2_30_edge_inst}, {rob_uop_2_29_edge_inst}, {rob_uop_2_28_edge_inst}, {rob_uop_2_27_edge_inst}, {rob_uop_2_26_edge_inst}, {rob_uop_2_25_edge_inst}, {rob_uop_2_24_edge_inst}, {rob_uop_2_23_edge_inst}, {rob_uop_2_22_edge_inst}, {rob_uop_2_21_edge_inst}, {rob_uop_2_20_edge_inst}, {rob_uop_2_19_edge_inst}, {rob_uop_2_18_edge_inst}, {rob_uop_2_17_edge_inst}, {rob_uop_2_16_edge_inst}, {rob_uop_2_15_edge_inst}, {rob_uop_2_14_edge_inst}, {rob_uop_2_13_edge_inst}, {rob_uop_2_12_edge_inst}, {rob_uop_2_11_edge_inst}, {rob_uop_2_10_edge_inst}, {rob_uop_2_9_edge_inst}, {rob_uop_2_8_edge_inst}, {rob_uop_2_7_edge_inst}, {rob_uop_2_6_edge_inst}, {rob_uop_2_5_edge_inst}, {rob_uop_2_4_edge_inst}, {rob_uop_2_3_edge_inst}, {rob_uop_2_2_edge_inst}, {rob_uop_2_1_edge_inst}, {rob_uop_2_0_edge_inst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_edge_inst_0 = _GEN_213[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_214 = {{rob_uop_2_31_pc_lob}, {rob_uop_2_30_pc_lob}, {rob_uop_2_29_pc_lob}, {rob_uop_2_28_pc_lob}, {rob_uop_2_27_pc_lob}, {rob_uop_2_26_pc_lob}, {rob_uop_2_25_pc_lob}, {rob_uop_2_24_pc_lob}, {rob_uop_2_23_pc_lob}, {rob_uop_2_22_pc_lob}, {rob_uop_2_21_pc_lob}, {rob_uop_2_20_pc_lob}, {rob_uop_2_19_pc_lob}, {rob_uop_2_18_pc_lob}, {rob_uop_2_17_pc_lob}, {rob_uop_2_16_pc_lob}, {rob_uop_2_15_pc_lob}, {rob_uop_2_14_pc_lob}, {rob_uop_2_13_pc_lob}, {rob_uop_2_12_pc_lob}, {rob_uop_2_11_pc_lob}, {rob_uop_2_10_pc_lob}, {rob_uop_2_9_pc_lob}, {rob_uop_2_8_pc_lob}, {rob_uop_2_7_pc_lob}, {rob_uop_2_6_pc_lob}, {rob_uop_2_5_pc_lob}, {rob_uop_2_4_pc_lob}, {rob_uop_2_3_pc_lob}, {rob_uop_2_2_pc_lob}, {rob_uop_2_1_pc_lob}, {rob_uop_2_0_pc_lob}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_pc_lob_0 = _GEN_214[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_215 = {{rob_uop_2_31_taken}, {rob_uop_2_30_taken}, {rob_uop_2_29_taken}, {rob_uop_2_28_taken}, {rob_uop_2_27_taken}, {rob_uop_2_26_taken}, {rob_uop_2_25_taken}, {rob_uop_2_24_taken}, {rob_uop_2_23_taken}, {rob_uop_2_22_taken}, {rob_uop_2_21_taken}, {rob_uop_2_20_taken}, {rob_uop_2_19_taken}, {rob_uop_2_18_taken}, {rob_uop_2_17_taken}, {rob_uop_2_16_taken}, {rob_uop_2_15_taken}, {rob_uop_2_14_taken}, {rob_uop_2_13_taken}, {rob_uop_2_12_taken}, {rob_uop_2_11_taken}, {rob_uop_2_10_taken}, {rob_uop_2_9_taken}, {rob_uop_2_8_taken}, {rob_uop_2_7_taken}, {rob_uop_2_6_taken}, {rob_uop_2_5_taken}, {rob_uop_2_4_taken}, {rob_uop_2_3_taken}, {rob_uop_2_2_taken}, {rob_uop_2_1_taken}, {rob_uop_2_0_taken}}; // @[rob.scala:311:28, :415:25]
wire [31:0][19:0] _GEN_216 = {{rob_uop_2_31_imm_packed}, {rob_uop_2_30_imm_packed}, {rob_uop_2_29_imm_packed}, {rob_uop_2_28_imm_packed}, {rob_uop_2_27_imm_packed}, {rob_uop_2_26_imm_packed}, {rob_uop_2_25_imm_packed}, {rob_uop_2_24_imm_packed}, {rob_uop_2_23_imm_packed}, {rob_uop_2_22_imm_packed}, {rob_uop_2_21_imm_packed}, {rob_uop_2_20_imm_packed}, {rob_uop_2_19_imm_packed}, {rob_uop_2_18_imm_packed}, {rob_uop_2_17_imm_packed}, {rob_uop_2_16_imm_packed}, {rob_uop_2_15_imm_packed}, {rob_uop_2_14_imm_packed}, {rob_uop_2_13_imm_packed}, {rob_uop_2_12_imm_packed}, {rob_uop_2_11_imm_packed}, {rob_uop_2_10_imm_packed}, {rob_uop_2_9_imm_packed}, {rob_uop_2_8_imm_packed}, {rob_uop_2_7_imm_packed}, {rob_uop_2_6_imm_packed}, {rob_uop_2_5_imm_packed}, {rob_uop_2_4_imm_packed}, {rob_uop_2_3_imm_packed}, {rob_uop_2_2_imm_packed}, {rob_uop_2_1_imm_packed}, {rob_uop_2_0_imm_packed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_imm_packed_0 = _GEN_216[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][11:0] _GEN_217 = {{rob_uop_2_31_csr_addr}, {rob_uop_2_30_csr_addr}, {rob_uop_2_29_csr_addr}, {rob_uop_2_28_csr_addr}, {rob_uop_2_27_csr_addr}, {rob_uop_2_26_csr_addr}, {rob_uop_2_25_csr_addr}, {rob_uop_2_24_csr_addr}, {rob_uop_2_23_csr_addr}, {rob_uop_2_22_csr_addr}, {rob_uop_2_21_csr_addr}, {rob_uop_2_20_csr_addr}, {rob_uop_2_19_csr_addr}, {rob_uop_2_18_csr_addr}, {rob_uop_2_17_csr_addr}, {rob_uop_2_16_csr_addr}, {rob_uop_2_15_csr_addr}, {rob_uop_2_14_csr_addr}, {rob_uop_2_13_csr_addr}, {rob_uop_2_12_csr_addr}, {rob_uop_2_11_csr_addr}, {rob_uop_2_10_csr_addr}, {rob_uop_2_9_csr_addr}, {rob_uop_2_8_csr_addr}, {rob_uop_2_7_csr_addr}, {rob_uop_2_6_csr_addr}, {rob_uop_2_5_csr_addr}, {rob_uop_2_4_csr_addr}, {rob_uop_2_3_csr_addr}, {rob_uop_2_2_csr_addr}, {rob_uop_2_1_csr_addr}, {rob_uop_2_0_csr_addr}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_csr_addr_0 = _GEN_217[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_218 = {{rob_uop_2_31_rob_idx}, {rob_uop_2_30_rob_idx}, {rob_uop_2_29_rob_idx}, {rob_uop_2_28_rob_idx}, {rob_uop_2_27_rob_idx}, {rob_uop_2_26_rob_idx}, {rob_uop_2_25_rob_idx}, {rob_uop_2_24_rob_idx}, {rob_uop_2_23_rob_idx}, {rob_uop_2_22_rob_idx}, {rob_uop_2_21_rob_idx}, {rob_uop_2_20_rob_idx}, {rob_uop_2_19_rob_idx}, {rob_uop_2_18_rob_idx}, {rob_uop_2_17_rob_idx}, {rob_uop_2_16_rob_idx}, {rob_uop_2_15_rob_idx}, {rob_uop_2_14_rob_idx}, {rob_uop_2_13_rob_idx}, {rob_uop_2_12_rob_idx}, {rob_uop_2_11_rob_idx}, {rob_uop_2_10_rob_idx}, {rob_uop_2_9_rob_idx}, {rob_uop_2_8_rob_idx}, {rob_uop_2_7_rob_idx}, {rob_uop_2_6_rob_idx}, {rob_uop_2_5_rob_idx}, {rob_uop_2_4_rob_idx}, {rob_uop_2_3_rob_idx}, {rob_uop_2_2_rob_idx}, {rob_uop_2_1_rob_idx}, {rob_uop_2_0_rob_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_rob_idx_0 = _GEN_218[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_219 = {{rob_uop_2_31_ldq_idx}, {rob_uop_2_30_ldq_idx}, {rob_uop_2_29_ldq_idx}, {rob_uop_2_28_ldq_idx}, {rob_uop_2_27_ldq_idx}, {rob_uop_2_26_ldq_idx}, {rob_uop_2_25_ldq_idx}, {rob_uop_2_24_ldq_idx}, {rob_uop_2_23_ldq_idx}, {rob_uop_2_22_ldq_idx}, {rob_uop_2_21_ldq_idx}, {rob_uop_2_20_ldq_idx}, {rob_uop_2_19_ldq_idx}, {rob_uop_2_18_ldq_idx}, {rob_uop_2_17_ldq_idx}, {rob_uop_2_16_ldq_idx}, {rob_uop_2_15_ldq_idx}, {rob_uop_2_14_ldq_idx}, {rob_uop_2_13_ldq_idx}, {rob_uop_2_12_ldq_idx}, {rob_uop_2_11_ldq_idx}, {rob_uop_2_10_ldq_idx}, {rob_uop_2_9_ldq_idx}, {rob_uop_2_8_ldq_idx}, {rob_uop_2_7_ldq_idx}, {rob_uop_2_6_ldq_idx}, {rob_uop_2_5_ldq_idx}, {rob_uop_2_4_ldq_idx}, {rob_uop_2_3_ldq_idx}, {rob_uop_2_2_ldq_idx}, {rob_uop_2_1_ldq_idx}, {rob_uop_2_0_ldq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ldq_idx_0 = _GEN_219[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_220 = {{rob_uop_2_31_stq_idx}, {rob_uop_2_30_stq_idx}, {rob_uop_2_29_stq_idx}, {rob_uop_2_28_stq_idx}, {rob_uop_2_27_stq_idx}, {rob_uop_2_26_stq_idx}, {rob_uop_2_25_stq_idx}, {rob_uop_2_24_stq_idx}, {rob_uop_2_23_stq_idx}, {rob_uop_2_22_stq_idx}, {rob_uop_2_21_stq_idx}, {rob_uop_2_20_stq_idx}, {rob_uop_2_19_stq_idx}, {rob_uop_2_18_stq_idx}, {rob_uop_2_17_stq_idx}, {rob_uop_2_16_stq_idx}, {rob_uop_2_15_stq_idx}, {rob_uop_2_14_stq_idx}, {rob_uop_2_13_stq_idx}, {rob_uop_2_12_stq_idx}, {rob_uop_2_11_stq_idx}, {rob_uop_2_10_stq_idx}, {rob_uop_2_9_stq_idx}, {rob_uop_2_8_stq_idx}, {rob_uop_2_7_stq_idx}, {rob_uop_2_6_stq_idx}, {rob_uop_2_5_stq_idx}, {rob_uop_2_4_stq_idx}, {rob_uop_2_3_stq_idx}, {rob_uop_2_2_stq_idx}, {rob_uop_2_1_stq_idx}, {rob_uop_2_0_stq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_stq_idx_0 = _GEN_220[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_221 = {{rob_uop_2_31_rxq_idx}, {rob_uop_2_30_rxq_idx}, {rob_uop_2_29_rxq_idx}, {rob_uop_2_28_rxq_idx}, {rob_uop_2_27_rxq_idx}, {rob_uop_2_26_rxq_idx}, {rob_uop_2_25_rxq_idx}, {rob_uop_2_24_rxq_idx}, {rob_uop_2_23_rxq_idx}, {rob_uop_2_22_rxq_idx}, {rob_uop_2_21_rxq_idx}, {rob_uop_2_20_rxq_idx}, {rob_uop_2_19_rxq_idx}, {rob_uop_2_18_rxq_idx}, {rob_uop_2_17_rxq_idx}, {rob_uop_2_16_rxq_idx}, {rob_uop_2_15_rxq_idx}, {rob_uop_2_14_rxq_idx}, {rob_uop_2_13_rxq_idx}, {rob_uop_2_12_rxq_idx}, {rob_uop_2_11_rxq_idx}, {rob_uop_2_10_rxq_idx}, {rob_uop_2_9_rxq_idx}, {rob_uop_2_8_rxq_idx}, {rob_uop_2_7_rxq_idx}, {rob_uop_2_6_rxq_idx}, {rob_uop_2_5_rxq_idx}, {rob_uop_2_4_rxq_idx}, {rob_uop_2_3_rxq_idx}, {rob_uop_2_2_rxq_idx}, {rob_uop_2_1_rxq_idx}, {rob_uop_2_0_rxq_idx}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_rxq_idx_0 = _GEN_221[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_222 = {{rob_uop_2_31_pdst}, {rob_uop_2_30_pdst}, {rob_uop_2_29_pdst}, {rob_uop_2_28_pdst}, {rob_uop_2_27_pdst}, {rob_uop_2_26_pdst}, {rob_uop_2_25_pdst}, {rob_uop_2_24_pdst}, {rob_uop_2_23_pdst}, {rob_uop_2_22_pdst}, {rob_uop_2_21_pdst}, {rob_uop_2_20_pdst}, {rob_uop_2_19_pdst}, {rob_uop_2_18_pdst}, {rob_uop_2_17_pdst}, {rob_uop_2_16_pdst}, {rob_uop_2_15_pdst}, {rob_uop_2_14_pdst}, {rob_uop_2_13_pdst}, {rob_uop_2_12_pdst}, {rob_uop_2_11_pdst}, {rob_uop_2_10_pdst}, {rob_uop_2_9_pdst}, {rob_uop_2_8_pdst}, {rob_uop_2_7_pdst}, {rob_uop_2_6_pdst}, {rob_uop_2_5_pdst}, {rob_uop_2_4_pdst}, {rob_uop_2_3_pdst}, {rob_uop_2_2_pdst}, {rob_uop_2_1_pdst}, {rob_uop_2_0_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_pdst_0 = _GEN_222[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_223 = {{rob_uop_2_31_prs1}, {rob_uop_2_30_prs1}, {rob_uop_2_29_prs1}, {rob_uop_2_28_prs1}, {rob_uop_2_27_prs1}, {rob_uop_2_26_prs1}, {rob_uop_2_25_prs1}, {rob_uop_2_24_prs1}, {rob_uop_2_23_prs1}, {rob_uop_2_22_prs1}, {rob_uop_2_21_prs1}, {rob_uop_2_20_prs1}, {rob_uop_2_19_prs1}, {rob_uop_2_18_prs1}, {rob_uop_2_17_prs1}, {rob_uop_2_16_prs1}, {rob_uop_2_15_prs1}, {rob_uop_2_14_prs1}, {rob_uop_2_13_prs1}, {rob_uop_2_12_prs1}, {rob_uop_2_11_prs1}, {rob_uop_2_10_prs1}, {rob_uop_2_9_prs1}, {rob_uop_2_8_prs1}, {rob_uop_2_7_prs1}, {rob_uop_2_6_prs1}, {rob_uop_2_5_prs1}, {rob_uop_2_4_prs1}, {rob_uop_2_3_prs1}, {rob_uop_2_2_prs1}, {rob_uop_2_1_prs1}, {rob_uop_2_0_prs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs1_0 = _GEN_223[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_224 = {{rob_uop_2_31_prs2}, {rob_uop_2_30_prs2}, {rob_uop_2_29_prs2}, {rob_uop_2_28_prs2}, {rob_uop_2_27_prs2}, {rob_uop_2_26_prs2}, {rob_uop_2_25_prs2}, {rob_uop_2_24_prs2}, {rob_uop_2_23_prs2}, {rob_uop_2_22_prs2}, {rob_uop_2_21_prs2}, {rob_uop_2_20_prs2}, {rob_uop_2_19_prs2}, {rob_uop_2_18_prs2}, {rob_uop_2_17_prs2}, {rob_uop_2_16_prs2}, {rob_uop_2_15_prs2}, {rob_uop_2_14_prs2}, {rob_uop_2_13_prs2}, {rob_uop_2_12_prs2}, {rob_uop_2_11_prs2}, {rob_uop_2_10_prs2}, {rob_uop_2_9_prs2}, {rob_uop_2_8_prs2}, {rob_uop_2_7_prs2}, {rob_uop_2_6_prs2}, {rob_uop_2_5_prs2}, {rob_uop_2_4_prs2}, {rob_uop_2_3_prs2}, {rob_uop_2_2_prs2}, {rob_uop_2_1_prs2}, {rob_uop_2_0_prs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs2_0 = _GEN_224[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_225 = {{rob_uop_2_31_prs3}, {rob_uop_2_30_prs3}, {rob_uop_2_29_prs3}, {rob_uop_2_28_prs3}, {rob_uop_2_27_prs3}, {rob_uop_2_26_prs3}, {rob_uop_2_25_prs3}, {rob_uop_2_24_prs3}, {rob_uop_2_23_prs3}, {rob_uop_2_22_prs3}, {rob_uop_2_21_prs3}, {rob_uop_2_20_prs3}, {rob_uop_2_19_prs3}, {rob_uop_2_18_prs3}, {rob_uop_2_17_prs3}, {rob_uop_2_16_prs3}, {rob_uop_2_15_prs3}, {rob_uop_2_14_prs3}, {rob_uop_2_13_prs3}, {rob_uop_2_12_prs3}, {rob_uop_2_11_prs3}, {rob_uop_2_10_prs3}, {rob_uop_2_9_prs3}, {rob_uop_2_8_prs3}, {rob_uop_2_7_prs3}, {rob_uop_2_6_prs3}, {rob_uop_2_5_prs3}, {rob_uop_2_4_prs3}, {rob_uop_2_3_prs3}, {rob_uop_2_2_prs3}, {rob_uop_2_1_prs3}, {rob_uop_2_0_prs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs3_0 = _GEN_225[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_226 = {{rob_uop_2_31_prs1_busy}, {rob_uop_2_30_prs1_busy}, {rob_uop_2_29_prs1_busy}, {rob_uop_2_28_prs1_busy}, {rob_uop_2_27_prs1_busy}, {rob_uop_2_26_prs1_busy}, {rob_uop_2_25_prs1_busy}, {rob_uop_2_24_prs1_busy}, {rob_uop_2_23_prs1_busy}, {rob_uop_2_22_prs1_busy}, {rob_uop_2_21_prs1_busy}, {rob_uop_2_20_prs1_busy}, {rob_uop_2_19_prs1_busy}, {rob_uop_2_18_prs1_busy}, {rob_uop_2_17_prs1_busy}, {rob_uop_2_16_prs1_busy}, {rob_uop_2_15_prs1_busy}, {rob_uop_2_14_prs1_busy}, {rob_uop_2_13_prs1_busy}, {rob_uop_2_12_prs1_busy}, {rob_uop_2_11_prs1_busy}, {rob_uop_2_10_prs1_busy}, {rob_uop_2_9_prs1_busy}, {rob_uop_2_8_prs1_busy}, {rob_uop_2_7_prs1_busy}, {rob_uop_2_6_prs1_busy}, {rob_uop_2_5_prs1_busy}, {rob_uop_2_4_prs1_busy}, {rob_uop_2_3_prs1_busy}, {rob_uop_2_2_prs1_busy}, {rob_uop_2_1_prs1_busy}, {rob_uop_2_0_prs1_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs1_busy_0 = _GEN_226[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_227 = {{rob_uop_2_31_prs2_busy}, {rob_uop_2_30_prs2_busy}, {rob_uop_2_29_prs2_busy}, {rob_uop_2_28_prs2_busy}, {rob_uop_2_27_prs2_busy}, {rob_uop_2_26_prs2_busy}, {rob_uop_2_25_prs2_busy}, {rob_uop_2_24_prs2_busy}, {rob_uop_2_23_prs2_busy}, {rob_uop_2_22_prs2_busy}, {rob_uop_2_21_prs2_busy}, {rob_uop_2_20_prs2_busy}, {rob_uop_2_19_prs2_busy}, {rob_uop_2_18_prs2_busy}, {rob_uop_2_17_prs2_busy}, {rob_uop_2_16_prs2_busy}, {rob_uop_2_15_prs2_busy}, {rob_uop_2_14_prs2_busy}, {rob_uop_2_13_prs2_busy}, {rob_uop_2_12_prs2_busy}, {rob_uop_2_11_prs2_busy}, {rob_uop_2_10_prs2_busy}, {rob_uop_2_9_prs2_busy}, {rob_uop_2_8_prs2_busy}, {rob_uop_2_7_prs2_busy}, {rob_uop_2_6_prs2_busy}, {rob_uop_2_5_prs2_busy}, {rob_uop_2_4_prs2_busy}, {rob_uop_2_3_prs2_busy}, {rob_uop_2_2_prs2_busy}, {rob_uop_2_1_prs2_busy}, {rob_uop_2_0_prs2_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs2_busy_0 = _GEN_227[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_228 = {{rob_uop_2_31_prs3_busy}, {rob_uop_2_30_prs3_busy}, {rob_uop_2_29_prs3_busy}, {rob_uop_2_28_prs3_busy}, {rob_uop_2_27_prs3_busy}, {rob_uop_2_26_prs3_busy}, {rob_uop_2_25_prs3_busy}, {rob_uop_2_24_prs3_busy}, {rob_uop_2_23_prs3_busy}, {rob_uop_2_22_prs3_busy}, {rob_uop_2_21_prs3_busy}, {rob_uop_2_20_prs3_busy}, {rob_uop_2_19_prs3_busy}, {rob_uop_2_18_prs3_busy}, {rob_uop_2_17_prs3_busy}, {rob_uop_2_16_prs3_busy}, {rob_uop_2_15_prs3_busy}, {rob_uop_2_14_prs3_busy}, {rob_uop_2_13_prs3_busy}, {rob_uop_2_12_prs3_busy}, {rob_uop_2_11_prs3_busy}, {rob_uop_2_10_prs3_busy}, {rob_uop_2_9_prs3_busy}, {rob_uop_2_8_prs3_busy}, {rob_uop_2_7_prs3_busy}, {rob_uop_2_6_prs3_busy}, {rob_uop_2_5_prs3_busy}, {rob_uop_2_4_prs3_busy}, {rob_uop_2_3_prs3_busy}, {rob_uop_2_2_prs3_busy}, {rob_uop_2_1_prs3_busy}, {rob_uop_2_0_prs3_busy}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_prs3_busy_0 = _GEN_228[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][6:0] _GEN_229 = {{rob_uop_2_31_stale_pdst}, {rob_uop_2_30_stale_pdst}, {rob_uop_2_29_stale_pdst}, {rob_uop_2_28_stale_pdst}, {rob_uop_2_27_stale_pdst}, {rob_uop_2_26_stale_pdst}, {rob_uop_2_25_stale_pdst}, {rob_uop_2_24_stale_pdst}, {rob_uop_2_23_stale_pdst}, {rob_uop_2_22_stale_pdst}, {rob_uop_2_21_stale_pdst}, {rob_uop_2_20_stale_pdst}, {rob_uop_2_19_stale_pdst}, {rob_uop_2_18_stale_pdst}, {rob_uop_2_17_stale_pdst}, {rob_uop_2_16_stale_pdst}, {rob_uop_2_15_stale_pdst}, {rob_uop_2_14_stale_pdst}, {rob_uop_2_13_stale_pdst}, {rob_uop_2_12_stale_pdst}, {rob_uop_2_11_stale_pdst}, {rob_uop_2_10_stale_pdst}, {rob_uop_2_9_stale_pdst}, {rob_uop_2_8_stale_pdst}, {rob_uop_2_7_stale_pdst}, {rob_uop_2_6_stale_pdst}, {rob_uop_2_5_stale_pdst}, {rob_uop_2_4_stale_pdst}, {rob_uop_2_3_stale_pdst}, {rob_uop_2_2_stale_pdst}, {rob_uop_2_1_stale_pdst}, {rob_uop_2_0_stale_pdst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_stale_pdst_0 = _GEN_229[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_230 = {{rob_uop_2_31_exception}, {rob_uop_2_30_exception}, {rob_uop_2_29_exception}, {rob_uop_2_28_exception}, {rob_uop_2_27_exception}, {rob_uop_2_26_exception}, {rob_uop_2_25_exception}, {rob_uop_2_24_exception}, {rob_uop_2_23_exception}, {rob_uop_2_22_exception}, {rob_uop_2_21_exception}, {rob_uop_2_20_exception}, {rob_uop_2_19_exception}, {rob_uop_2_18_exception}, {rob_uop_2_17_exception}, {rob_uop_2_16_exception}, {rob_uop_2_15_exception}, {rob_uop_2_14_exception}, {rob_uop_2_13_exception}, {rob_uop_2_12_exception}, {rob_uop_2_11_exception}, {rob_uop_2_10_exception}, {rob_uop_2_9_exception}, {rob_uop_2_8_exception}, {rob_uop_2_7_exception}, {rob_uop_2_6_exception}, {rob_uop_2_5_exception}, {rob_uop_2_4_exception}, {rob_uop_2_3_exception}, {rob_uop_2_2_exception}, {rob_uop_2_1_exception}, {rob_uop_2_0_exception}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_exception_0 = _GEN_230[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][63:0] _GEN_231 = {{rob_uop_2_31_exc_cause}, {rob_uop_2_30_exc_cause}, {rob_uop_2_29_exc_cause}, {rob_uop_2_28_exc_cause}, {rob_uop_2_27_exc_cause}, {rob_uop_2_26_exc_cause}, {rob_uop_2_25_exc_cause}, {rob_uop_2_24_exc_cause}, {rob_uop_2_23_exc_cause}, {rob_uop_2_22_exc_cause}, {rob_uop_2_21_exc_cause}, {rob_uop_2_20_exc_cause}, {rob_uop_2_19_exc_cause}, {rob_uop_2_18_exc_cause}, {rob_uop_2_17_exc_cause}, {rob_uop_2_16_exc_cause}, {rob_uop_2_15_exc_cause}, {rob_uop_2_14_exc_cause}, {rob_uop_2_13_exc_cause}, {rob_uop_2_12_exc_cause}, {rob_uop_2_11_exc_cause}, {rob_uop_2_10_exc_cause}, {rob_uop_2_9_exc_cause}, {rob_uop_2_8_exc_cause}, {rob_uop_2_7_exc_cause}, {rob_uop_2_6_exc_cause}, {rob_uop_2_5_exc_cause}, {rob_uop_2_4_exc_cause}, {rob_uop_2_3_exc_cause}, {rob_uop_2_2_exc_cause}, {rob_uop_2_1_exc_cause}, {rob_uop_2_0_exc_cause}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_exc_cause_0 = _GEN_231[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_232 = {{rob_uop_2_31_bypassable}, {rob_uop_2_30_bypassable}, {rob_uop_2_29_bypassable}, {rob_uop_2_28_bypassable}, {rob_uop_2_27_bypassable}, {rob_uop_2_26_bypassable}, {rob_uop_2_25_bypassable}, {rob_uop_2_24_bypassable}, {rob_uop_2_23_bypassable}, {rob_uop_2_22_bypassable}, {rob_uop_2_21_bypassable}, {rob_uop_2_20_bypassable}, {rob_uop_2_19_bypassable}, {rob_uop_2_18_bypassable}, {rob_uop_2_17_bypassable}, {rob_uop_2_16_bypassable}, {rob_uop_2_15_bypassable}, {rob_uop_2_14_bypassable}, {rob_uop_2_13_bypassable}, {rob_uop_2_12_bypassable}, {rob_uop_2_11_bypassable}, {rob_uop_2_10_bypassable}, {rob_uop_2_9_bypassable}, {rob_uop_2_8_bypassable}, {rob_uop_2_7_bypassable}, {rob_uop_2_6_bypassable}, {rob_uop_2_5_bypassable}, {rob_uop_2_4_bypassable}, {rob_uop_2_3_bypassable}, {rob_uop_2_2_bypassable}, {rob_uop_2_1_bypassable}, {rob_uop_2_0_bypassable}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_bypassable_0 = _GEN_232[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][4:0] _GEN_233 = {{rob_uop_2_31_mem_cmd}, {rob_uop_2_30_mem_cmd}, {rob_uop_2_29_mem_cmd}, {rob_uop_2_28_mem_cmd}, {rob_uop_2_27_mem_cmd}, {rob_uop_2_26_mem_cmd}, {rob_uop_2_25_mem_cmd}, {rob_uop_2_24_mem_cmd}, {rob_uop_2_23_mem_cmd}, {rob_uop_2_22_mem_cmd}, {rob_uop_2_21_mem_cmd}, {rob_uop_2_20_mem_cmd}, {rob_uop_2_19_mem_cmd}, {rob_uop_2_18_mem_cmd}, {rob_uop_2_17_mem_cmd}, {rob_uop_2_16_mem_cmd}, {rob_uop_2_15_mem_cmd}, {rob_uop_2_14_mem_cmd}, {rob_uop_2_13_mem_cmd}, {rob_uop_2_12_mem_cmd}, {rob_uop_2_11_mem_cmd}, {rob_uop_2_10_mem_cmd}, {rob_uop_2_9_mem_cmd}, {rob_uop_2_8_mem_cmd}, {rob_uop_2_7_mem_cmd}, {rob_uop_2_6_mem_cmd}, {rob_uop_2_5_mem_cmd}, {rob_uop_2_4_mem_cmd}, {rob_uop_2_3_mem_cmd}, {rob_uop_2_2_mem_cmd}, {rob_uop_2_1_mem_cmd}, {rob_uop_2_0_mem_cmd}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_mem_cmd_0 = _GEN_233[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_234 = {{rob_uop_2_31_mem_size}, {rob_uop_2_30_mem_size}, {rob_uop_2_29_mem_size}, {rob_uop_2_28_mem_size}, {rob_uop_2_27_mem_size}, {rob_uop_2_26_mem_size}, {rob_uop_2_25_mem_size}, {rob_uop_2_24_mem_size}, {rob_uop_2_23_mem_size}, {rob_uop_2_22_mem_size}, {rob_uop_2_21_mem_size}, {rob_uop_2_20_mem_size}, {rob_uop_2_19_mem_size}, {rob_uop_2_18_mem_size}, {rob_uop_2_17_mem_size}, {rob_uop_2_16_mem_size}, {rob_uop_2_15_mem_size}, {rob_uop_2_14_mem_size}, {rob_uop_2_13_mem_size}, {rob_uop_2_12_mem_size}, {rob_uop_2_11_mem_size}, {rob_uop_2_10_mem_size}, {rob_uop_2_9_mem_size}, {rob_uop_2_8_mem_size}, {rob_uop_2_7_mem_size}, {rob_uop_2_6_mem_size}, {rob_uop_2_5_mem_size}, {rob_uop_2_4_mem_size}, {rob_uop_2_3_mem_size}, {rob_uop_2_2_mem_size}, {rob_uop_2_1_mem_size}, {rob_uop_2_0_mem_size}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_mem_size_0 = _GEN_234[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_235 = {{rob_uop_2_31_mem_signed}, {rob_uop_2_30_mem_signed}, {rob_uop_2_29_mem_signed}, {rob_uop_2_28_mem_signed}, {rob_uop_2_27_mem_signed}, {rob_uop_2_26_mem_signed}, {rob_uop_2_25_mem_signed}, {rob_uop_2_24_mem_signed}, {rob_uop_2_23_mem_signed}, {rob_uop_2_22_mem_signed}, {rob_uop_2_21_mem_signed}, {rob_uop_2_20_mem_signed}, {rob_uop_2_19_mem_signed}, {rob_uop_2_18_mem_signed}, {rob_uop_2_17_mem_signed}, {rob_uop_2_16_mem_signed}, {rob_uop_2_15_mem_signed}, {rob_uop_2_14_mem_signed}, {rob_uop_2_13_mem_signed}, {rob_uop_2_12_mem_signed}, {rob_uop_2_11_mem_signed}, {rob_uop_2_10_mem_signed}, {rob_uop_2_9_mem_signed}, {rob_uop_2_8_mem_signed}, {rob_uop_2_7_mem_signed}, {rob_uop_2_6_mem_signed}, {rob_uop_2_5_mem_signed}, {rob_uop_2_4_mem_signed}, {rob_uop_2_3_mem_signed}, {rob_uop_2_2_mem_signed}, {rob_uop_2_1_mem_signed}, {rob_uop_2_0_mem_signed}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_mem_signed_0 = _GEN_235[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_236 = {{rob_uop_2_31_is_fence}, {rob_uop_2_30_is_fence}, {rob_uop_2_29_is_fence}, {rob_uop_2_28_is_fence}, {rob_uop_2_27_is_fence}, {rob_uop_2_26_is_fence}, {rob_uop_2_25_is_fence}, {rob_uop_2_24_is_fence}, {rob_uop_2_23_is_fence}, {rob_uop_2_22_is_fence}, {rob_uop_2_21_is_fence}, {rob_uop_2_20_is_fence}, {rob_uop_2_19_is_fence}, {rob_uop_2_18_is_fence}, {rob_uop_2_17_is_fence}, {rob_uop_2_16_is_fence}, {rob_uop_2_15_is_fence}, {rob_uop_2_14_is_fence}, {rob_uop_2_13_is_fence}, {rob_uop_2_12_is_fence}, {rob_uop_2_11_is_fence}, {rob_uop_2_10_is_fence}, {rob_uop_2_9_is_fence}, {rob_uop_2_8_is_fence}, {rob_uop_2_7_is_fence}, {rob_uop_2_6_is_fence}, {rob_uop_2_5_is_fence}, {rob_uop_2_4_is_fence}, {rob_uop_2_3_is_fence}, {rob_uop_2_2_is_fence}, {rob_uop_2_1_is_fence}, {rob_uop_2_0_is_fence}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_fence_0 = _GEN_236[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_237 = {{rob_uop_2_31_is_fencei}, {rob_uop_2_30_is_fencei}, {rob_uop_2_29_is_fencei}, {rob_uop_2_28_is_fencei}, {rob_uop_2_27_is_fencei}, {rob_uop_2_26_is_fencei}, {rob_uop_2_25_is_fencei}, {rob_uop_2_24_is_fencei}, {rob_uop_2_23_is_fencei}, {rob_uop_2_22_is_fencei}, {rob_uop_2_21_is_fencei}, {rob_uop_2_20_is_fencei}, {rob_uop_2_19_is_fencei}, {rob_uop_2_18_is_fencei}, {rob_uop_2_17_is_fencei}, {rob_uop_2_16_is_fencei}, {rob_uop_2_15_is_fencei}, {rob_uop_2_14_is_fencei}, {rob_uop_2_13_is_fencei}, {rob_uop_2_12_is_fencei}, {rob_uop_2_11_is_fencei}, {rob_uop_2_10_is_fencei}, {rob_uop_2_9_is_fencei}, {rob_uop_2_8_is_fencei}, {rob_uop_2_7_is_fencei}, {rob_uop_2_6_is_fencei}, {rob_uop_2_5_is_fencei}, {rob_uop_2_4_is_fencei}, {rob_uop_2_3_is_fencei}, {rob_uop_2_2_is_fencei}, {rob_uop_2_1_is_fencei}, {rob_uop_2_0_is_fencei}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_fencei_0 = _GEN_237[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_238 = {{rob_uop_2_31_is_amo}, {rob_uop_2_30_is_amo}, {rob_uop_2_29_is_amo}, {rob_uop_2_28_is_amo}, {rob_uop_2_27_is_amo}, {rob_uop_2_26_is_amo}, {rob_uop_2_25_is_amo}, {rob_uop_2_24_is_amo}, {rob_uop_2_23_is_amo}, {rob_uop_2_22_is_amo}, {rob_uop_2_21_is_amo}, {rob_uop_2_20_is_amo}, {rob_uop_2_19_is_amo}, {rob_uop_2_18_is_amo}, {rob_uop_2_17_is_amo}, {rob_uop_2_16_is_amo}, {rob_uop_2_15_is_amo}, {rob_uop_2_14_is_amo}, {rob_uop_2_13_is_amo}, {rob_uop_2_12_is_amo}, {rob_uop_2_11_is_amo}, {rob_uop_2_10_is_amo}, {rob_uop_2_9_is_amo}, {rob_uop_2_8_is_amo}, {rob_uop_2_7_is_amo}, {rob_uop_2_6_is_amo}, {rob_uop_2_5_is_amo}, {rob_uop_2_4_is_amo}, {rob_uop_2_3_is_amo}, {rob_uop_2_2_is_amo}, {rob_uop_2_1_is_amo}, {rob_uop_2_0_is_amo}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_amo_0 = _GEN_238[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_239 = {{rob_uop_2_31_uses_ldq}, {rob_uop_2_30_uses_ldq}, {rob_uop_2_29_uses_ldq}, {rob_uop_2_28_uses_ldq}, {rob_uop_2_27_uses_ldq}, {rob_uop_2_26_uses_ldq}, {rob_uop_2_25_uses_ldq}, {rob_uop_2_24_uses_ldq}, {rob_uop_2_23_uses_ldq}, {rob_uop_2_22_uses_ldq}, {rob_uop_2_21_uses_ldq}, {rob_uop_2_20_uses_ldq}, {rob_uop_2_19_uses_ldq}, {rob_uop_2_18_uses_ldq}, {rob_uop_2_17_uses_ldq}, {rob_uop_2_16_uses_ldq}, {rob_uop_2_15_uses_ldq}, {rob_uop_2_14_uses_ldq}, {rob_uop_2_13_uses_ldq}, {rob_uop_2_12_uses_ldq}, {rob_uop_2_11_uses_ldq}, {rob_uop_2_10_uses_ldq}, {rob_uop_2_9_uses_ldq}, {rob_uop_2_8_uses_ldq}, {rob_uop_2_7_uses_ldq}, {rob_uop_2_6_uses_ldq}, {rob_uop_2_5_uses_ldq}, {rob_uop_2_4_uses_ldq}, {rob_uop_2_3_uses_ldq}, {rob_uop_2_2_uses_ldq}, {rob_uop_2_1_uses_ldq}, {rob_uop_2_0_uses_ldq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_uses_ldq_0 = _GEN_239[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_240 = {{rob_uop_2_31_uses_stq}, {rob_uop_2_30_uses_stq}, {rob_uop_2_29_uses_stq}, {rob_uop_2_28_uses_stq}, {rob_uop_2_27_uses_stq}, {rob_uop_2_26_uses_stq}, {rob_uop_2_25_uses_stq}, {rob_uop_2_24_uses_stq}, {rob_uop_2_23_uses_stq}, {rob_uop_2_22_uses_stq}, {rob_uop_2_21_uses_stq}, {rob_uop_2_20_uses_stq}, {rob_uop_2_19_uses_stq}, {rob_uop_2_18_uses_stq}, {rob_uop_2_17_uses_stq}, {rob_uop_2_16_uses_stq}, {rob_uop_2_15_uses_stq}, {rob_uop_2_14_uses_stq}, {rob_uop_2_13_uses_stq}, {rob_uop_2_12_uses_stq}, {rob_uop_2_11_uses_stq}, {rob_uop_2_10_uses_stq}, {rob_uop_2_9_uses_stq}, {rob_uop_2_8_uses_stq}, {rob_uop_2_7_uses_stq}, {rob_uop_2_6_uses_stq}, {rob_uop_2_5_uses_stq}, {rob_uop_2_4_uses_stq}, {rob_uop_2_3_uses_stq}, {rob_uop_2_2_uses_stq}, {rob_uop_2_1_uses_stq}, {rob_uop_2_0_uses_stq}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_uses_stq_0 = _GEN_240[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_241 = {{rob_uop_2_31_is_sys_pc2epc}, {rob_uop_2_30_is_sys_pc2epc}, {rob_uop_2_29_is_sys_pc2epc}, {rob_uop_2_28_is_sys_pc2epc}, {rob_uop_2_27_is_sys_pc2epc}, {rob_uop_2_26_is_sys_pc2epc}, {rob_uop_2_25_is_sys_pc2epc}, {rob_uop_2_24_is_sys_pc2epc}, {rob_uop_2_23_is_sys_pc2epc}, {rob_uop_2_22_is_sys_pc2epc}, {rob_uop_2_21_is_sys_pc2epc}, {rob_uop_2_20_is_sys_pc2epc}, {rob_uop_2_19_is_sys_pc2epc}, {rob_uop_2_18_is_sys_pc2epc}, {rob_uop_2_17_is_sys_pc2epc}, {rob_uop_2_16_is_sys_pc2epc}, {rob_uop_2_15_is_sys_pc2epc}, {rob_uop_2_14_is_sys_pc2epc}, {rob_uop_2_13_is_sys_pc2epc}, {rob_uop_2_12_is_sys_pc2epc}, {rob_uop_2_11_is_sys_pc2epc}, {rob_uop_2_10_is_sys_pc2epc}, {rob_uop_2_9_is_sys_pc2epc}, {rob_uop_2_8_is_sys_pc2epc}, {rob_uop_2_7_is_sys_pc2epc}, {rob_uop_2_6_is_sys_pc2epc}, {rob_uop_2_5_is_sys_pc2epc}, {rob_uop_2_4_is_sys_pc2epc}, {rob_uop_2_3_is_sys_pc2epc}, {rob_uop_2_2_is_sys_pc2epc}, {rob_uop_2_1_is_sys_pc2epc}, {rob_uop_2_0_is_sys_pc2epc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_sys_pc2epc_0 = _GEN_241[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_242 = {{rob_uop_2_31_is_unique}, {rob_uop_2_30_is_unique}, {rob_uop_2_29_is_unique}, {rob_uop_2_28_is_unique}, {rob_uop_2_27_is_unique}, {rob_uop_2_26_is_unique}, {rob_uop_2_25_is_unique}, {rob_uop_2_24_is_unique}, {rob_uop_2_23_is_unique}, {rob_uop_2_22_is_unique}, {rob_uop_2_21_is_unique}, {rob_uop_2_20_is_unique}, {rob_uop_2_19_is_unique}, {rob_uop_2_18_is_unique}, {rob_uop_2_17_is_unique}, {rob_uop_2_16_is_unique}, {rob_uop_2_15_is_unique}, {rob_uop_2_14_is_unique}, {rob_uop_2_13_is_unique}, {rob_uop_2_12_is_unique}, {rob_uop_2_11_is_unique}, {rob_uop_2_10_is_unique}, {rob_uop_2_9_is_unique}, {rob_uop_2_8_is_unique}, {rob_uop_2_7_is_unique}, {rob_uop_2_6_is_unique}, {rob_uop_2_5_is_unique}, {rob_uop_2_4_is_unique}, {rob_uop_2_3_is_unique}, {rob_uop_2_2_is_unique}, {rob_uop_2_1_is_unique}, {rob_uop_2_0_is_unique}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_is_unique_0 = _GEN_242[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_243 = {{rob_uop_2_31_flush_on_commit}, {rob_uop_2_30_flush_on_commit}, {rob_uop_2_29_flush_on_commit}, {rob_uop_2_28_flush_on_commit}, {rob_uop_2_27_flush_on_commit}, {rob_uop_2_26_flush_on_commit}, {rob_uop_2_25_flush_on_commit}, {rob_uop_2_24_flush_on_commit}, {rob_uop_2_23_flush_on_commit}, {rob_uop_2_22_flush_on_commit}, {rob_uop_2_21_flush_on_commit}, {rob_uop_2_20_flush_on_commit}, {rob_uop_2_19_flush_on_commit}, {rob_uop_2_18_flush_on_commit}, {rob_uop_2_17_flush_on_commit}, {rob_uop_2_16_flush_on_commit}, {rob_uop_2_15_flush_on_commit}, {rob_uop_2_14_flush_on_commit}, {rob_uop_2_13_flush_on_commit}, {rob_uop_2_12_flush_on_commit}, {rob_uop_2_11_flush_on_commit}, {rob_uop_2_10_flush_on_commit}, {rob_uop_2_9_flush_on_commit}, {rob_uop_2_8_flush_on_commit}, {rob_uop_2_7_flush_on_commit}, {rob_uop_2_6_flush_on_commit}, {rob_uop_2_5_flush_on_commit}, {rob_uop_2_4_flush_on_commit}, {rob_uop_2_3_flush_on_commit}, {rob_uop_2_2_flush_on_commit}, {rob_uop_2_1_flush_on_commit}, {rob_uop_2_0_flush_on_commit}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_flush_on_commit_0 = _GEN_243[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_244 = {{rob_uop_2_31_ldst_is_rs1}, {rob_uop_2_30_ldst_is_rs1}, {rob_uop_2_29_ldst_is_rs1}, {rob_uop_2_28_ldst_is_rs1}, {rob_uop_2_27_ldst_is_rs1}, {rob_uop_2_26_ldst_is_rs1}, {rob_uop_2_25_ldst_is_rs1}, {rob_uop_2_24_ldst_is_rs1}, {rob_uop_2_23_ldst_is_rs1}, {rob_uop_2_22_ldst_is_rs1}, {rob_uop_2_21_ldst_is_rs1}, {rob_uop_2_20_ldst_is_rs1}, {rob_uop_2_19_ldst_is_rs1}, {rob_uop_2_18_ldst_is_rs1}, {rob_uop_2_17_ldst_is_rs1}, {rob_uop_2_16_ldst_is_rs1}, {rob_uop_2_15_ldst_is_rs1}, {rob_uop_2_14_ldst_is_rs1}, {rob_uop_2_13_ldst_is_rs1}, {rob_uop_2_12_ldst_is_rs1}, {rob_uop_2_11_ldst_is_rs1}, {rob_uop_2_10_ldst_is_rs1}, {rob_uop_2_9_ldst_is_rs1}, {rob_uop_2_8_ldst_is_rs1}, {rob_uop_2_7_ldst_is_rs1}, {rob_uop_2_6_ldst_is_rs1}, {rob_uop_2_5_ldst_is_rs1}, {rob_uop_2_4_ldst_is_rs1}, {rob_uop_2_3_ldst_is_rs1}, {rob_uop_2_2_ldst_is_rs1}, {rob_uop_2_1_ldst_is_rs1}, {rob_uop_2_0_ldst_is_rs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ldst_is_rs1_0 = _GEN_244[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_245 = {{rob_uop_2_31_ldst}, {rob_uop_2_30_ldst}, {rob_uop_2_29_ldst}, {rob_uop_2_28_ldst}, {rob_uop_2_27_ldst}, {rob_uop_2_26_ldst}, {rob_uop_2_25_ldst}, {rob_uop_2_24_ldst}, {rob_uop_2_23_ldst}, {rob_uop_2_22_ldst}, {rob_uop_2_21_ldst}, {rob_uop_2_20_ldst}, {rob_uop_2_19_ldst}, {rob_uop_2_18_ldst}, {rob_uop_2_17_ldst}, {rob_uop_2_16_ldst}, {rob_uop_2_15_ldst}, {rob_uop_2_14_ldst}, {rob_uop_2_13_ldst}, {rob_uop_2_12_ldst}, {rob_uop_2_11_ldst}, {rob_uop_2_10_ldst}, {rob_uop_2_9_ldst}, {rob_uop_2_8_ldst}, {rob_uop_2_7_ldst}, {rob_uop_2_6_ldst}, {rob_uop_2_5_ldst}, {rob_uop_2_4_ldst}, {rob_uop_2_3_ldst}, {rob_uop_2_2_ldst}, {rob_uop_2_1_ldst}, {rob_uop_2_0_ldst}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ldst_0 = _GEN_245[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_246 = {{rob_uop_2_31_lrs1}, {rob_uop_2_30_lrs1}, {rob_uop_2_29_lrs1}, {rob_uop_2_28_lrs1}, {rob_uop_2_27_lrs1}, {rob_uop_2_26_lrs1}, {rob_uop_2_25_lrs1}, {rob_uop_2_24_lrs1}, {rob_uop_2_23_lrs1}, {rob_uop_2_22_lrs1}, {rob_uop_2_21_lrs1}, {rob_uop_2_20_lrs1}, {rob_uop_2_19_lrs1}, {rob_uop_2_18_lrs1}, {rob_uop_2_17_lrs1}, {rob_uop_2_16_lrs1}, {rob_uop_2_15_lrs1}, {rob_uop_2_14_lrs1}, {rob_uop_2_13_lrs1}, {rob_uop_2_12_lrs1}, {rob_uop_2_11_lrs1}, {rob_uop_2_10_lrs1}, {rob_uop_2_9_lrs1}, {rob_uop_2_8_lrs1}, {rob_uop_2_7_lrs1}, {rob_uop_2_6_lrs1}, {rob_uop_2_5_lrs1}, {rob_uop_2_4_lrs1}, {rob_uop_2_3_lrs1}, {rob_uop_2_2_lrs1}, {rob_uop_2_1_lrs1}, {rob_uop_2_0_lrs1}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_lrs1_0 = _GEN_246[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_247 = {{rob_uop_2_31_lrs2}, {rob_uop_2_30_lrs2}, {rob_uop_2_29_lrs2}, {rob_uop_2_28_lrs2}, {rob_uop_2_27_lrs2}, {rob_uop_2_26_lrs2}, {rob_uop_2_25_lrs2}, {rob_uop_2_24_lrs2}, {rob_uop_2_23_lrs2}, {rob_uop_2_22_lrs2}, {rob_uop_2_21_lrs2}, {rob_uop_2_20_lrs2}, {rob_uop_2_19_lrs2}, {rob_uop_2_18_lrs2}, {rob_uop_2_17_lrs2}, {rob_uop_2_16_lrs2}, {rob_uop_2_15_lrs2}, {rob_uop_2_14_lrs2}, {rob_uop_2_13_lrs2}, {rob_uop_2_12_lrs2}, {rob_uop_2_11_lrs2}, {rob_uop_2_10_lrs2}, {rob_uop_2_9_lrs2}, {rob_uop_2_8_lrs2}, {rob_uop_2_7_lrs2}, {rob_uop_2_6_lrs2}, {rob_uop_2_5_lrs2}, {rob_uop_2_4_lrs2}, {rob_uop_2_3_lrs2}, {rob_uop_2_2_lrs2}, {rob_uop_2_1_lrs2}, {rob_uop_2_0_lrs2}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_lrs2_0 = _GEN_247[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][5:0] _GEN_248 = {{rob_uop_2_31_lrs3}, {rob_uop_2_30_lrs3}, {rob_uop_2_29_lrs3}, {rob_uop_2_28_lrs3}, {rob_uop_2_27_lrs3}, {rob_uop_2_26_lrs3}, {rob_uop_2_25_lrs3}, {rob_uop_2_24_lrs3}, {rob_uop_2_23_lrs3}, {rob_uop_2_22_lrs3}, {rob_uop_2_21_lrs3}, {rob_uop_2_20_lrs3}, {rob_uop_2_19_lrs3}, {rob_uop_2_18_lrs3}, {rob_uop_2_17_lrs3}, {rob_uop_2_16_lrs3}, {rob_uop_2_15_lrs3}, {rob_uop_2_14_lrs3}, {rob_uop_2_13_lrs3}, {rob_uop_2_12_lrs3}, {rob_uop_2_11_lrs3}, {rob_uop_2_10_lrs3}, {rob_uop_2_9_lrs3}, {rob_uop_2_8_lrs3}, {rob_uop_2_7_lrs3}, {rob_uop_2_6_lrs3}, {rob_uop_2_5_lrs3}, {rob_uop_2_4_lrs3}, {rob_uop_2_3_lrs3}, {rob_uop_2_2_lrs3}, {rob_uop_2_1_lrs3}, {rob_uop_2_0_lrs3}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_lrs3_0 = _GEN_248[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_249 = {{rob_uop_2_31_ldst_val}, {rob_uop_2_30_ldst_val}, {rob_uop_2_29_ldst_val}, {rob_uop_2_28_ldst_val}, {rob_uop_2_27_ldst_val}, {rob_uop_2_26_ldst_val}, {rob_uop_2_25_ldst_val}, {rob_uop_2_24_ldst_val}, {rob_uop_2_23_ldst_val}, {rob_uop_2_22_ldst_val}, {rob_uop_2_21_ldst_val}, {rob_uop_2_20_ldst_val}, {rob_uop_2_19_ldst_val}, {rob_uop_2_18_ldst_val}, {rob_uop_2_17_ldst_val}, {rob_uop_2_16_ldst_val}, {rob_uop_2_15_ldst_val}, {rob_uop_2_14_ldst_val}, {rob_uop_2_13_ldst_val}, {rob_uop_2_12_ldst_val}, {rob_uop_2_11_ldst_val}, {rob_uop_2_10_ldst_val}, {rob_uop_2_9_ldst_val}, {rob_uop_2_8_ldst_val}, {rob_uop_2_7_ldst_val}, {rob_uop_2_6_ldst_val}, {rob_uop_2_5_ldst_val}, {rob_uop_2_4_ldst_val}, {rob_uop_2_3_ldst_val}, {rob_uop_2_2_ldst_val}, {rob_uop_2_1_ldst_val}, {rob_uop_2_0_ldst_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_ldst_val_0 = _GEN_249[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_250 = {{rob_uop_2_31_dst_rtype}, {rob_uop_2_30_dst_rtype}, {rob_uop_2_29_dst_rtype}, {rob_uop_2_28_dst_rtype}, {rob_uop_2_27_dst_rtype}, {rob_uop_2_26_dst_rtype}, {rob_uop_2_25_dst_rtype}, {rob_uop_2_24_dst_rtype}, {rob_uop_2_23_dst_rtype}, {rob_uop_2_22_dst_rtype}, {rob_uop_2_21_dst_rtype}, {rob_uop_2_20_dst_rtype}, {rob_uop_2_19_dst_rtype}, {rob_uop_2_18_dst_rtype}, {rob_uop_2_17_dst_rtype}, {rob_uop_2_16_dst_rtype}, {rob_uop_2_15_dst_rtype}, {rob_uop_2_14_dst_rtype}, {rob_uop_2_13_dst_rtype}, {rob_uop_2_12_dst_rtype}, {rob_uop_2_11_dst_rtype}, {rob_uop_2_10_dst_rtype}, {rob_uop_2_9_dst_rtype}, {rob_uop_2_8_dst_rtype}, {rob_uop_2_7_dst_rtype}, {rob_uop_2_6_dst_rtype}, {rob_uop_2_5_dst_rtype}, {rob_uop_2_4_dst_rtype}, {rob_uop_2_3_dst_rtype}, {rob_uop_2_2_dst_rtype}, {rob_uop_2_1_dst_rtype}, {rob_uop_2_0_dst_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_dst_rtype_0 = _GEN_250[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_251 = {{rob_uop_2_31_lrs1_rtype}, {rob_uop_2_30_lrs1_rtype}, {rob_uop_2_29_lrs1_rtype}, {rob_uop_2_28_lrs1_rtype}, {rob_uop_2_27_lrs1_rtype}, {rob_uop_2_26_lrs1_rtype}, {rob_uop_2_25_lrs1_rtype}, {rob_uop_2_24_lrs1_rtype}, {rob_uop_2_23_lrs1_rtype}, {rob_uop_2_22_lrs1_rtype}, {rob_uop_2_21_lrs1_rtype}, {rob_uop_2_20_lrs1_rtype}, {rob_uop_2_19_lrs1_rtype}, {rob_uop_2_18_lrs1_rtype}, {rob_uop_2_17_lrs1_rtype}, {rob_uop_2_16_lrs1_rtype}, {rob_uop_2_15_lrs1_rtype}, {rob_uop_2_14_lrs1_rtype}, {rob_uop_2_13_lrs1_rtype}, {rob_uop_2_12_lrs1_rtype}, {rob_uop_2_11_lrs1_rtype}, {rob_uop_2_10_lrs1_rtype}, {rob_uop_2_9_lrs1_rtype}, {rob_uop_2_8_lrs1_rtype}, {rob_uop_2_7_lrs1_rtype}, {rob_uop_2_6_lrs1_rtype}, {rob_uop_2_5_lrs1_rtype}, {rob_uop_2_4_lrs1_rtype}, {rob_uop_2_3_lrs1_rtype}, {rob_uop_2_2_lrs1_rtype}, {rob_uop_2_1_lrs1_rtype}, {rob_uop_2_0_lrs1_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_lrs1_rtype_0 = _GEN_251[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_252 = {{rob_uop_2_31_lrs2_rtype}, {rob_uop_2_30_lrs2_rtype}, {rob_uop_2_29_lrs2_rtype}, {rob_uop_2_28_lrs2_rtype}, {rob_uop_2_27_lrs2_rtype}, {rob_uop_2_26_lrs2_rtype}, {rob_uop_2_25_lrs2_rtype}, {rob_uop_2_24_lrs2_rtype}, {rob_uop_2_23_lrs2_rtype}, {rob_uop_2_22_lrs2_rtype}, {rob_uop_2_21_lrs2_rtype}, {rob_uop_2_20_lrs2_rtype}, {rob_uop_2_19_lrs2_rtype}, {rob_uop_2_18_lrs2_rtype}, {rob_uop_2_17_lrs2_rtype}, {rob_uop_2_16_lrs2_rtype}, {rob_uop_2_15_lrs2_rtype}, {rob_uop_2_14_lrs2_rtype}, {rob_uop_2_13_lrs2_rtype}, {rob_uop_2_12_lrs2_rtype}, {rob_uop_2_11_lrs2_rtype}, {rob_uop_2_10_lrs2_rtype}, {rob_uop_2_9_lrs2_rtype}, {rob_uop_2_8_lrs2_rtype}, {rob_uop_2_7_lrs2_rtype}, {rob_uop_2_6_lrs2_rtype}, {rob_uop_2_5_lrs2_rtype}, {rob_uop_2_4_lrs2_rtype}, {rob_uop_2_3_lrs2_rtype}, {rob_uop_2_2_lrs2_rtype}, {rob_uop_2_1_lrs2_rtype}, {rob_uop_2_0_lrs2_rtype}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_lrs2_rtype_0 = _GEN_252[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_253 = {{rob_uop_2_31_frs3_en}, {rob_uop_2_30_frs3_en}, {rob_uop_2_29_frs3_en}, {rob_uop_2_28_frs3_en}, {rob_uop_2_27_frs3_en}, {rob_uop_2_26_frs3_en}, {rob_uop_2_25_frs3_en}, {rob_uop_2_24_frs3_en}, {rob_uop_2_23_frs3_en}, {rob_uop_2_22_frs3_en}, {rob_uop_2_21_frs3_en}, {rob_uop_2_20_frs3_en}, {rob_uop_2_19_frs3_en}, {rob_uop_2_18_frs3_en}, {rob_uop_2_17_frs3_en}, {rob_uop_2_16_frs3_en}, {rob_uop_2_15_frs3_en}, {rob_uop_2_14_frs3_en}, {rob_uop_2_13_frs3_en}, {rob_uop_2_12_frs3_en}, {rob_uop_2_11_frs3_en}, {rob_uop_2_10_frs3_en}, {rob_uop_2_9_frs3_en}, {rob_uop_2_8_frs3_en}, {rob_uop_2_7_frs3_en}, {rob_uop_2_6_frs3_en}, {rob_uop_2_5_frs3_en}, {rob_uop_2_4_frs3_en}, {rob_uop_2_3_frs3_en}, {rob_uop_2_2_frs3_en}, {rob_uop_2_1_frs3_en}, {rob_uop_2_0_frs3_en}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_frs3_en_0 = _GEN_253[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_254 = {{rob_uop_2_31_fp_val}, {rob_uop_2_30_fp_val}, {rob_uop_2_29_fp_val}, {rob_uop_2_28_fp_val}, {rob_uop_2_27_fp_val}, {rob_uop_2_26_fp_val}, {rob_uop_2_25_fp_val}, {rob_uop_2_24_fp_val}, {rob_uop_2_23_fp_val}, {rob_uop_2_22_fp_val}, {rob_uop_2_21_fp_val}, {rob_uop_2_20_fp_val}, {rob_uop_2_19_fp_val}, {rob_uop_2_18_fp_val}, {rob_uop_2_17_fp_val}, {rob_uop_2_16_fp_val}, {rob_uop_2_15_fp_val}, {rob_uop_2_14_fp_val}, {rob_uop_2_13_fp_val}, {rob_uop_2_12_fp_val}, {rob_uop_2_11_fp_val}, {rob_uop_2_10_fp_val}, {rob_uop_2_9_fp_val}, {rob_uop_2_8_fp_val}, {rob_uop_2_7_fp_val}, {rob_uop_2_6_fp_val}, {rob_uop_2_5_fp_val}, {rob_uop_2_4_fp_val}, {rob_uop_2_3_fp_val}, {rob_uop_2_2_fp_val}, {rob_uop_2_1_fp_val}, {rob_uop_2_0_fp_val}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_fp_val_0 = _GEN_254[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_255 = {{rob_uop_2_31_fp_single}, {rob_uop_2_30_fp_single}, {rob_uop_2_29_fp_single}, {rob_uop_2_28_fp_single}, {rob_uop_2_27_fp_single}, {rob_uop_2_26_fp_single}, {rob_uop_2_25_fp_single}, {rob_uop_2_24_fp_single}, {rob_uop_2_23_fp_single}, {rob_uop_2_22_fp_single}, {rob_uop_2_21_fp_single}, {rob_uop_2_20_fp_single}, {rob_uop_2_19_fp_single}, {rob_uop_2_18_fp_single}, {rob_uop_2_17_fp_single}, {rob_uop_2_16_fp_single}, {rob_uop_2_15_fp_single}, {rob_uop_2_14_fp_single}, {rob_uop_2_13_fp_single}, {rob_uop_2_12_fp_single}, {rob_uop_2_11_fp_single}, {rob_uop_2_10_fp_single}, {rob_uop_2_9_fp_single}, {rob_uop_2_8_fp_single}, {rob_uop_2_7_fp_single}, {rob_uop_2_6_fp_single}, {rob_uop_2_5_fp_single}, {rob_uop_2_4_fp_single}, {rob_uop_2_3_fp_single}, {rob_uop_2_2_fp_single}, {rob_uop_2_1_fp_single}, {rob_uop_2_0_fp_single}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_fp_single_0 = _GEN_255[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_256 = {{rob_uop_2_31_xcpt_pf_if}, {rob_uop_2_30_xcpt_pf_if}, {rob_uop_2_29_xcpt_pf_if}, {rob_uop_2_28_xcpt_pf_if}, {rob_uop_2_27_xcpt_pf_if}, {rob_uop_2_26_xcpt_pf_if}, {rob_uop_2_25_xcpt_pf_if}, {rob_uop_2_24_xcpt_pf_if}, {rob_uop_2_23_xcpt_pf_if}, {rob_uop_2_22_xcpt_pf_if}, {rob_uop_2_21_xcpt_pf_if}, {rob_uop_2_20_xcpt_pf_if}, {rob_uop_2_19_xcpt_pf_if}, {rob_uop_2_18_xcpt_pf_if}, {rob_uop_2_17_xcpt_pf_if}, {rob_uop_2_16_xcpt_pf_if}, {rob_uop_2_15_xcpt_pf_if}, {rob_uop_2_14_xcpt_pf_if}, {rob_uop_2_13_xcpt_pf_if}, {rob_uop_2_12_xcpt_pf_if}, {rob_uop_2_11_xcpt_pf_if}, {rob_uop_2_10_xcpt_pf_if}, {rob_uop_2_9_xcpt_pf_if}, {rob_uop_2_8_xcpt_pf_if}, {rob_uop_2_7_xcpt_pf_if}, {rob_uop_2_6_xcpt_pf_if}, {rob_uop_2_5_xcpt_pf_if}, {rob_uop_2_4_xcpt_pf_if}, {rob_uop_2_3_xcpt_pf_if}, {rob_uop_2_2_xcpt_pf_if}, {rob_uop_2_1_xcpt_pf_if}, {rob_uop_2_0_xcpt_pf_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_xcpt_pf_if_0 = _GEN_256[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_257 = {{rob_uop_2_31_xcpt_ae_if}, {rob_uop_2_30_xcpt_ae_if}, {rob_uop_2_29_xcpt_ae_if}, {rob_uop_2_28_xcpt_ae_if}, {rob_uop_2_27_xcpt_ae_if}, {rob_uop_2_26_xcpt_ae_if}, {rob_uop_2_25_xcpt_ae_if}, {rob_uop_2_24_xcpt_ae_if}, {rob_uop_2_23_xcpt_ae_if}, {rob_uop_2_22_xcpt_ae_if}, {rob_uop_2_21_xcpt_ae_if}, {rob_uop_2_20_xcpt_ae_if}, {rob_uop_2_19_xcpt_ae_if}, {rob_uop_2_18_xcpt_ae_if}, {rob_uop_2_17_xcpt_ae_if}, {rob_uop_2_16_xcpt_ae_if}, {rob_uop_2_15_xcpt_ae_if}, {rob_uop_2_14_xcpt_ae_if}, {rob_uop_2_13_xcpt_ae_if}, {rob_uop_2_12_xcpt_ae_if}, {rob_uop_2_11_xcpt_ae_if}, {rob_uop_2_10_xcpt_ae_if}, {rob_uop_2_9_xcpt_ae_if}, {rob_uop_2_8_xcpt_ae_if}, {rob_uop_2_7_xcpt_ae_if}, {rob_uop_2_6_xcpt_ae_if}, {rob_uop_2_5_xcpt_ae_if}, {rob_uop_2_4_xcpt_ae_if}, {rob_uop_2_3_xcpt_ae_if}, {rob_uop_2_2_xcpt_ae_if}, {rob_uop_2_1_xcpt_ae_if}, {rob_uop_2_0_xcpt_ae_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_xcpt_ae_if_0 = _GEN_257[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_258 = {{rob_uop_2_31_xcpt_ma_if}, {rob_uop_2_30_xcpt_ma_if}, {rob_uop_2_29_xcpt_ma_if}, {rob_uop_2_28_xcpt_ma_if}, {rob_uop_2_27_xcpt_ma_if}, {rob_uop_2_26_xcpt_ma_if}, {rob_uop_2_25_xcpt_ma_if}, {rob_uop_2_24_xcpt_ma_if}, {rob_uop_2_23_xcpt_ma_if}, {rob_uop_2_22_xcpt_ma_if}, {rob_uop_2_21_xcpt_ma_if}, {rob_uop_2_20_xcpt_ma_if}, {rob_uop_2_19_xcpt_ma_if}, {rob_uop_2_18_xcpt_ma_if}, {rob_uop_2_17_xcpt_ma_if}, {rob_uop_2_16_xcpt_ma_if}, {rob_uop_2_15_xcpt_ma_if}, {rob_uop_2_14_xcpt_ma_if}, {rob_uop_2_13_xcpt_ma_if}, {rob_uop_2_12_xcpt_ma_if}, {rob_uop_2_11_xcpt_ma_if}, {rob_uop_2_10_xcpt_ma_if}, {rob_uop_2_9_xcpt_ma_if}, {rob_uop_2_8_xcpt_ma_if}, {rob_uop_2_7_xcpt_ma_if}, {rob_uop_2_6_xcpt_ma_if}, {rob_uop_2_5_xcpt_ma_if}, {rob_uop_2_4_xcpt_ma_if}, {rob_uop_2_3_xcpt_ma_if}, {rob_uop_2_2_xcpt_ma_if}, {rob_uop_2_1_xcpt_ma_if}, {rob_uop_2_0_xcpt_ma_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_xcpt_ma_if_0 = _GEN_258[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_259 = {{rob_uop_2_31_bp_debug_if}, {rob_uop_2_30_bp_debug_if}, {rob_uop_2_29_bp_debug_if}, {rob_uop_2_28_bp_debug_if}, {rob_uop_2_27_bp_debug_if}, {rob_uop_2_26_bp_debug_if}, {rob_uop_2_25_bp_debug_if}, {rob_uop_2_24_bp_debug_if}, {rob_uop_2_23_bp_debug_if}, {rob_uop_2_22_bp_debug_if}, {rob_uop_2_21_bp_debug_if}, {rob_uop_2_20_bp_debug_if}, {rob_uop_2_19_bp_debug_if}, {rob_uop_2_18_bp_debug_if}, {rob_uop_2_17_bp_debug_if}, {rob_uop_2_16_bp_debug_if}, {rob_uop_2_15_bp_debug_if}, {rob_uop_2_14_bp_debug_if}, {rob_uop_2_13_bp_debug_if}, {rob_uop_2_12_bp_debug_if}, {rob_uop_2_11_bp_debug_if}, {rob_uop_2_10_bp_debug_if}, {rob_uop_2_9_bp_debug_if}, {rob_uop_2_8_bp_debug_if}, {rob_uop_2_7_bp_debug_if}, {rob_uop_2_6_bp_debug_if}, {rob_uop_2_5_bp_debug_if}, {rob_uop_2_4_bp_debug_if}, {rob_uop_2_3_bp_debug_if}, {rob_uop_2_2_bp_debug_if}, {rob_uop_2_1_bp_debug_if}, {rob_uop_2_0_bp_debug_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_bp_debug_if_0 = _GEN_259[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0] _GEN_260 = {{rob_uop_2_31_bp_xcpt_if}, {rob_uop_2_30_bp_xcpt_if}, {rob_uop_2_29_bp_xcpt_if}, {rob_uop_2_28_bp_xcpt_if}, {rob_uop_2_27_bp_xcpt_if}, {rob_uop_2_26_bp_xcpt_if}, {rob_uop_2_25_bp_xcpt_if}, {rob_uop_2_24_bp_xcpt_if}, {rob_uop_2_23_bp_xcpt_if}, {rob_uop_2_22_bp_xcpt_if}, {rob_uop_2_21_bp_xcpt_if}, {rob_uop_2_20_bp_xcpt_if}, {rob_uop_2_19_bp_xcpt_if}, {rob_uop_2_18_bp_xcpt_if}, {rob_uop_2_17_bp_xcpt_if}, {rob_uop_2_16_bp_xcpt_if}, {rob_uop_2_15_bp_xcpt_if}, {rob_uop_2_14_bp_xcpt_if}, {rob_uop_2_13_bp_xcpt_if}, {rob_uop_2_12_bp_xcpt_if}, {rob_uop_2_11_bp_xcpt_if}, {rob_uop_2_10_bp_xcpt_if}, {rob_uop_2_9_bp_xcpt_if}, {rob_uop_2_8_bp_xcpt_if}, {rob_uop_2_7_bp_xcpt_if}, {rob_uop_2_6_bp_xcpt_if}, {rob_uop_2_5_bp_xcpt_if}, {rob_uop_2_4_bp_xcpt_if}, {rob_uop_2_3_bp_xcpt_if}, {rob_uop_2_2_bp_xcpt_if}, {rob_uop_2_1_bp_xcpt_if}, {rob_uop_2_0_bp_xcpt_if}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_bp_xcpt_if_0 = _GEN_260[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire [31:0][1:0] _GEN_261 = {{rob_uop_2_31_debug_fsrc}, {rob_uop_2_30_debug_fsrc}, {rob_uop_2_29_debug_fsrc}, {rob_uop_2_28_debug_fsrc}, {rob_uop_2_27_debug_fsrc}, {rob_uop_2_26_debug_fsrc}, {rob_uop_2_25_debug_fsrc}, {rob_uop_2_24_debug_fsrc}, {rob_uop_2_23_debug_fsrc}, {rob_uop_2_22_debug_fsrc}, {rob_uop_2_21_debug_fsrc}, {rob_uop_2_20_debug_fsrc}, {rob_uop_2_19_debug_fsrc}, {rob_uop_2_18_debug_fsrc}, {rob_uop_2_17_debug_fsrc}, {rob_uop_2_16_debug_fsrc}, {rob_uop_2_15_debug_fsrc}, {rob_uop_2_14_debug_fsrc}, {rob_uop_2_13_debug_fsrc}, {rob_uop_2_12_debug_fsrc}, {rob_uop_2_11_debug_fsrc}, {rob_uop_2_10_debug_fsrc}, {rob_uop_2_9_debug_fsrc}, {rob_uop_2_8_debug_fsrc}, {rob_uop_2_7_debug_fsrc}, {rob_uop_2_6_debug_fsrc}, {rob_uop_2_5_debug_fsrc}, {rob_uop_2_4_debug_fsrc}, {rob_uop_2_3_debug_fsrc}, {rob_uop_2_2_debug_fsrc}, {rob_uop_2_1_debug_fsrc}, {rob_uop_2_0_debug_fsrc}}; // @[rob.scala:311:28, :415:25]
wire [31:0][1:0] _GEN_262 = {{rob_uop_2_31_debug_tsrc}, {rob_uop_2_30_debug_tsrc}, {rob_uop_2_29_debug_tsrc}, {rob_uop_2_28_debug_tsrc}, {rob_uop_2_27_debug_tsrc}, {rob_uop_2_26_debug_tsrc}, {rob_uop_2_25_debug_tsrc}, {rob_uop_2_24_debug_tsrc}, {rob_uop_2_23_debug_tsrc}, {rob_uop_2_22_debug_tsrc}, {rob_uop_2_21_debug_tsrc}, {rob_uop_2_20_debug_tsrc}, {rob_uop_2_19_debug_tsrc}, {rob_uop_2_18_debug_tsrc}, {rob_uop_2_17_debug_tsrc}, {rob_uop_2_16_debug_tsrc}, {rob_uop_2_15_debug_tsrc}, {rob_uop_2_14_debug_tsrc}, {rob_uop_2_13_debug_tsrc}, {rob_uop_2_12_debug_tsrc}, {rob_uop_2_11_debug_tsrc}, {rob_uop_2_10_debug_tsrc}, {rob_uop_2_9_debug_tsrc}, {rob_uop_2_8_debug_tsrc}, {rob_uop_2_7_debug_tsrc}, {rob_uop_2_6_debug_tsrc}, {rob_uop_2_5_debug_tsrc}, {rob_uop_2_4_debug_tsrc}, {rob_uop_2_3_debug_tsrc}, {rob_uop_2_2_debug_tsrc}, {rob_uop_2_1_debug_tsrc}, {rob_uop_2_0_debug_tsrc}}; // @[rob.scala:311:28, :415:25]
assign io_commit_uops_2_debug_tsrc_0 = _GEN_262[com_idx]; // @[rob.scala:211:7, :235:20, :415:25]
wire _T_948 = io_brupdate_b2_mispredict_0 & io_brupdate_b2_uop_rob_idx_0[1:0] == 2'h2 & io_brupdate_b2_uop_rob_idx_0[6:2] == com_idx; // @[rob.scala:211:7, :235:20, :267:25, :271:36, :305:53, :420:37, :421:57, :422:45]
assign io_commit_uops_2_debug_fsrc_0 = _T_948 ? 2'h3 : _GEN_261[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :423:36]
assign io_commit_uops_2_taken_0 = _T_948 ? io_brupdate_b2_taken_0 : _GEN_215[com_idx]; // @[rob.scala:211:7, :235:20, :415:25, :420:37, :421:57, :422:58, :424:36]
wire _rbk_row_T_5 = ~full; // @[rob.scala:239:26, :429:47]
wire rbk_row_2 = _rbk_row_T_4 & _rbk_row_T_5; // @[rob.scala:429:{29,44,47}]
wire _io_commit_rbk_valids_2_T = rbk_row_2 & _GEN_179[com_idx]; // @[rob.scala:235:20, :324:31, :429:44, :431:40]
assign _io_commit_rbk_valids_2_T_2 = _io_commit_rbk_valids_2_T; // @[rob.scala:431:{40,60}]
assign io_commit_rbk_valids_2_0 = _io_commit_rbk_valids_2_T_2; // @[rob.scala:211:7, :431:60]
assign io_commit_rollback_0 = _io_commit_rollback_T_2; // @[rob.scala:211:7, :432:38]
wire [15:0] _rob_uop_0_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_0_br_mask_T_5 = rob_uop_2_0_br_mask & _rob_uop_0_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_1_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_1_br_mask_T_5 = rob_uop_2_1_br_mask & _rob_uop_1_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_2_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_2_br_mask_T_5 = rob_uop_2_2_br_mask & _rob_uop_2_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_3_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_3_br_mask_T_5 = rob_uop_2_3_br_mask & _rob_uop_3_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_4_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_4_br_mask_T_5 = rob_uop_2_4_br_mask & _rob_uop_4_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_5_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_5_br_mask_T_5 = rob_uop_2_5_br_mask & _rob_uop_5_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_6_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_6_br_mask_T_5 = rob_uop_2_6_br_mask & _rob_uop_6_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_7_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_7_br_mask_T_5 = rob_uop_2_7_br_mask & _rob_uop_7_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_8_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_8_br_mask_T_5 = rob_uop_2_8_br_mask & _rob_uop_8_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_9_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_9_br_mask_T_5 = rob_uop_2_9_br_mask & _rob_uop_9_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_10_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_10_br_mask_T_5 = rob_uop_2_10_br_mask & _rob_uop_10_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_11_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_11_br_mask_T_5 = rob_uop_2_11_br_mask & _rob_uop_11_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_12_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_12_br_mask_T_5 = rob_uop_2_12_br_mask & _rob_uop_12_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_13_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_13_br_mask_T_5 = rob_uop_2_13_br_mask & _rob_uop_13_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_14_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_14_br_mask_T_5 = rob_uop_2_14_br_mask & _rob_uop_14_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_15_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_15_br_mask_T_5 = rob_uop_2_15_br_mask & _rob_uop_15_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_16_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_16_br_mask_T_5 = rob_uop_2_16_br_mask & _rob_uop_16_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_17_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_17_br_mask_T_5 = rob_uop_2_17_br_mask & _rob_uop_17_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_18_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_18_br_mask_T_5 = rob_uop_2_18_br_mask & _rob_uop_18_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_19_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_19_br_mask_T_5 = rob_uop_2_19_br_mask & _rob_uop_19_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_20_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_20_br_mask_T_5 = rob_uop_2_20_br_mask & _rob_uop_20_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_21_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_21_br_mask_T_5 = rob_uop_2_21_br_mask & _rob_uop_21_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_22_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_22_br_mask_T_5 = rob_uop_2_22_br_mask & _rob_uop_22_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_23_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_23_br_mask_T_5 = rob_uop_2_23_br_mask & _rob_uop_23_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_24_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_24_br_mask_T_5 = rob_uop_2_24_br_mask & _rob_uop_24_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_25_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_25_br_mask_T_5 = rob_uop_2_25_br_mask & _rob_uop_25_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_26_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_26_br_mask_T_5 = rob_uop_2_26_br_mask & _rob_uop_26_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_27_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_27_br_mask_T_5 = rob_uop_2_27_br_mask & _rob_uop_27_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_28_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_28_br_mask_T_5 = rob_uop_2_28_br_mask & _rob_uop_28_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_29_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_29_br_mask_T_5 = rob_uop_2_29_br_mask & _rob_uop_29_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_30_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_30_br_mask_T_5 = rob_uop_2_30_br_mask & _rob_uop_30_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [15:0] _rob_uop_31_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23]
wire [15:0] _rob_uop_31_br_mask_T_5 = rob_uop_2_31_br_mask & _rob_uop_31_br_mask_T_4; // @[util.scala:89:{21,23}]
wire [31:0][4:0] _GEN_263 = {{rob_fflags_2_31}, {rob_fflags_2_30}, {rob_fflags_2_29}, {rob_fflags_2_28}, {rob_fflags_2_27}, {rob_fflags_2_26}, {rob_fflags_2_25}, {rob_fflags_2_24}, {rob_fflags_2_23}, {rob_fflags_2_22}, {rob_fflags_2_21}, {rob_fflags_2_20}, {rob_fflags_2_19}, {rob_fflags_2_18}, {rob_fflags_2_17}, {rob_fflags_2_16}, {rob_fflags_2_15}, {rob_fflags_2_14}, {rob_fflags_2_13}, {rob_fflags_2_12}, {rob_fflags_2_11}, {rob_fflags_2_10}, {rob_fflags_2_9}, {rob_fflags_2_8}, {rob_fflags_2_7}, {rob_fflags_2_6}, {rob_fflags_2_5}, {rob_fflags_2_4}, {rob_fflags_2_3}, {rob_fflags_2_2}, {rob_fflags_2_1}, {rob_fflags_2_0}}; // @[rob.scala:302:46, :487:26]
assign rob_head_fflags_2 = _GEN_263[rob_head]; // @[rob.scala:223:29, :251:33, :487:26]
assign rob_head_uses_ldq_2 = _GEN_239[rob_head]; // @[rob.scala:223:29, :250:33, :415:25, :488:26]
assign rob_head_uses_stq_2 = _GEN_240[rob_head]; // @[rob.scala:223:29, :249:33, :415:25, :488:26]
wire _rob_unsafe_masked_2_T = rob_unsafe_2_0 | rob_exception_2_0; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_2_T_1 = rob_val_2_0 & _rob_unsafe_masked_2_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_2 = _rob_unsafe_masked_2_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_6_T = rob_unsafe_2_1 | rob_exception_2_1; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_6_T_1 = rob_val_2_1 & _rob_unsafe_masked_6_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_6 = _rob_unsafe_masked_6_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_10_T = rob_unsafe_2_2 | rob_exception_2_2; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_10_T_1 = rob_val_2_2 & _rob_unsafe_masked_10_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_10 = _rob_unsafe_masked_10_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_14_T = rob_unsafe_2_3 | rob_exception_2_3; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_14_T_1 = rob_val_2_3 & _rob_unsafe_masked_14_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_14 = _rob_unsafe_masked_14_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_18_T = rob_unsafe_2_4 | rob_exception_2_4; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_18_T_1 = rob_val_2_4 & _rob_unsafe_masked_18_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_18 = _rob_unsafe_masked_18_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_22_T = rob_unsafe_2_5 | rob_exception_2_5; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_22_T_1 = rob_val_2_5 & _rob_unsafe_masked_22_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_22 = _rob_unsafe_masked_22_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_26_T = rob_unsafe_2_6 | rob_exception_2_6; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_26_T_1 = rob_val_2_6 & _rob_unsafe_masked_26_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_26 = _rob_unsafe_masked_26_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_30_T = rob_unsafe_2_7 | rob_exception_2_7; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_30_T_1 = rob_val_2_7 & _rob_unsafe_masked_30_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_30 = _rob_unsafe_masked_30_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_34_T = rob_unsafe_2_8 | rob_exception_2_8; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_34_T_1 = rob_val_2_8 & _rob_unsafe_masked_34_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_34 = _rob_unsafe_masked_34_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_38_T = rob_unsafe_2_9 | rob_exception_2_9; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_38_T_1 = rob_val_2_9 & _rob_unsafe_masked_38_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_38 = _rob_unsafe_masked_38_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_42_T = rob_unsafe_2_10 | rob_exception_2_10; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_42_T_1 = rob_val_2_10 & _rob_unsafe_masked_42_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_42 = _rob_unsafe_masked_42_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_46_T = rob_unsafe_2_11 | rob_exception_2_11; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_46_T_1 = rob_val_2_11 & _rob_unsafe_masked_46_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_46 = _rob_unsafe_masked_46_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_50_T = rob_unsafe_2_12 | rob_exception_2_12; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_50_T_1 = rob_val_2_12 & _rob_unsafe_masked_50_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_50 = _rob_unsafe_masked_50_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_54_T = rob_unsafe_2_13 | rob_exception_2_13; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_54_T_1 = rob_val_2_13 & _rob_unsafe_masked_54_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_54 = _rob_unsafe_masked_54_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_58_T = rob_unsafe_2_14 | rob_exception_2_14; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_58_T_1 = rob_val_2_14 & _rob_unsafe_masked_58_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_58 = _rob_unsafe_masked_58_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_62_T = rob_unsafe_2_15 | rob_exception_2_15; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_62_T_1 = rob_val_2_15 & _rob_unsafe_masked_62_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_62 = _rob_unsafe_masked_62_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_66_T = rob_unsafe_2_16 | rob_exception_2_16; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_66_T_1 = rob_val_2_16 & _rob_unsafe_masked_66_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_66 = _rob_unsafe_masked_66_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_70_T = rob_unsafe_2_17 | rob_exception_2_17; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_70_T_1 = rob_val_2_17 & _rob_unsafe_masked_70_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_70 = _rob_unsafe_masked_70_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_74_T = rob_unsafe_2_18 | rob_exception_2_18; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_74_T_1 = rob_val_2_18 & _rob_unsafe_masked_74_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_74 = _rob_unsafe_masked_74_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_78_T = rob_unsafe_2_19 | rob_exception_2_19; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_78_T_1 = rob_val_2_19 & _rob_unsafe_masked_78_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_78 = _rob_unsafe_masked_78_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_82_T = rob_unsafe_2_20 | rob_exception_2_20; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_82_T_1 = rob_val_2_20 & _rob_unsafe_masked_82_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_82 = _rob_unsafe_masked_82_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_86_T = rob_unsafe_2_21 | rob_exception_2_21; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_86_T_1 = rob_val_2_21 & _rob_unsafe_masked_86_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_86 = _rob_unsafe_masked_86_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_90_T = rob_unsafe_2_22 | rob_exception_2_22; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_90_T_1 = rob_val_2_22 & _rob_unsafe_masked_90_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_90 = _rob_unsafe_masked_90_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_94_T = rob_unsafe_2_23 | rob_exception_2_23; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_94_T_1 = rob_val_2_23 & _rob_unsafe_masked_94_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_94 = _rob_unsafe_masked_94_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_98_T = rob_unsafe_2_24 | rob_exception_2_24; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_98_T_1 = rob_val_2_24 & _rob_unsafe_masked_98_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_98 = _rob_unsafe_masked_98_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_102_T = rob_unsafe_2_25 | rob_exception_2_25; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_102_T_1 = rob_val_2_25 & _rob_unsafe_masked_102_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_102 = _rob_unsafe_masked_102_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_106_T = rob_unsafe_2_26 | rob_exception_2_26; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_106_T_1 = rob_val_2_26 & _rob_unsafe_masked_106_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_106 = _rob_unsafe_masked_106_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_110_T = rob_unsafe_2_27 | rob_exception_2_27; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_110_T_1 = rob_val_2_27 & _rob_unsafe_masked_110_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_110 = _rob_unsafe_masked_110_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_114_T = rob_unsafe_2_28 | rob_exception_2_28; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_114_T_1 = rob_val_2_28 & _rob_unsafe_masked_114_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_114 = _rob_unsafe_masked_114_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_118_T = rob_unsafe_2_29 | rob_exception_2_29; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_118_T_1 = rob_val_2_29 & _rob_unsafe_masked_118_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_118 = _rob_unsafe_masked_118_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_122_T = rob_unsafe_2_30 | rob_exception_2_30; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_122_T_1 = rob_val_2_30 & _rob_unsafe_masked_122_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_122 = _rob_unsafe_masked_122_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_unsafe_masked_126_T = rob_unsafe_2_31 | rob_exception_2_31; // @[rob.scala:310:28, :312:28, :494:89]
assign _rob_unsafe_masked_126_T_1 = rob_val_2_31 & _rob_unsafe_masked_126_T; // @[rob.scala:308:32, :494:{71,89}]
assign rob_unsafe_masked_126 = _rob_unsafe_masked_126_T_1; // @[rob.scala:293:35, :494:71]
wire _rob_pnr_unsafe_2_T = _GEN_182[rob_pnr] | _GEN_184[rob_pnr]; // @[rob.scala:231:29, :394:15, :402:49, :497:67]
assign _rob_pnr_unsafe_2_T_1 = _GEN_179[rob_pnr] & _rob_pnr_unsafe_2_T; // @[rob.scala:231:29, :324:31, :497:{43,67}]
assign rob_pnr_unsafe_2 = _rob_pnr_unsafe_2_T_1; // @[rob.scala:246:33, :497:43]
wire [4:0] _temp_uop_T_25 = _temp_uop_T_24[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_27 = _temp_uop_T_26[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_29 = _temp_uop_T_28[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_31 = _temp_uop_T_30[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_33 = _temp_uop_T_32[4:0]; // @[rob.scala:267:25]
wire [4:0] _temp_uop_T_35 = _temp_uop_T_34[4:0]; // @[rob.scala:267:25]
wire _block_commit_T = rob_state != 2'h1; // @[rob.scala:220:26, :544:33]
wire _block_commit_T_1 = rob_state != 2'h3; // @[rob.scala:220:26, :544:61]
wire _block_commit_T_2 = _block_commit_T & _block_commit_T_1; // @[rob.scala:544:{33,47,61}]
reg block_commit_REG; // @[rob.scala:544:94]
wire _block_commit_T_3 = _block_commit_T_2 | block_commit_REG; // @[rob.scala:544:{47,84,94}]
reg block_commit_REG_1; // @[rob.scala:544:131]
reg block_commit_REG_2; // @[rob.scala:544:123]
wire block_commit = _block_commit_T_3 | block_commit_REG_2; // @[rob.scala:544:{84,113,123}]
wire _will_commit_0_T = ~can_throw_exception_0; // @[rob.scala:244:33, :551:46]
wire _will_commit_0_T_1 = can_commit_0 & _will_commit_0_T; // @[rob.scala:243:33, :551:{43,46}]
wire _will_commit_0_T_2 = ~block_commit; // @[rob.scala:544:113, :549:55, :551:73]
assign _will_commit_0_T_3 = _will_commit_0_T_1 & _will_commit_0_T_2; // @[rob.scala:551:{43,70,73}]
assign will_commit_0 = _will_commit_0_T_3; // @[rob.scala:242:33, :551:70]
wire _T_1259 = rob_head_vals_0 & (~can_commit_0 | can_throw_exception_0) | block_commit; // @[rob.scala:243:33, :244:33, :247:33, :544:113, :552:46, :553:{29,44,72}]
wire _will_commit_1_T = ~can_throw_exception_1; // @[rob.scala:244:33, :551:46]
wire _will_commit_1_T_1 = can_commit_1 & _will_commit_1_T; // @[rob.scala:243:33, :551:{43,46}]
wire _will_commit_1_T_2 = ~_T_1259; // @[rob.scala:549:55, :551:73, :553:72]
assign _will_commit_1_T_3 = _will_commit_1_T_1 & _will_commit_1_T_2; // @[rob.scala:551:{43,70,73}]
assign will_commit_1 = _will_commit_1_T_3; // @[rob.scala:242:33, :551:70]
wire _T_1268 = rob_head_vals_1 & (~can_commit_1 | can_throw_exception_1) | _T_1259; // @[rob.scala:243:33, :244:33, :247:33, :552:46, :553:{29,44,72}]
assign exception_thrown = can_throw_exception_2 & ~_T_1268 & ~will_commit_1 | can_throw_exception_1 & ~_T_1259 & ~will_commit_0 | can_throw_exception_0 & ~block_commit; // @[rob.scala:242:33, :244:33, :253:30, :544:113, :549:{52,55,69,72,85}, :553:72]
wire _will_commit_2_T = ~can_throw_exception_2; // @[rob.scala:244:33, :551:46]
wire _will_commit_2_T_1 = can_commit_2 & _will_commit_2_T; // @[rob.scala:243:33, :551:{43,46}]
wire _will_commit_2_T_2 = ~_T_1268; // @[rob.scala:549:55, :551:73, :553:72]
assign _will_commit_2_T_3 = _will_commit_2_T_1 & _will_commit_2_T_2; // @[rob.scala:551:{43,70,73}]
assign will_commit_2 = _will_commit_2_T_3; // @[rob.scala:242:33, :551:70]
wire _is_mini_exception_T = io_com_xcpt_bits_cause_0 == 64'h10; // @[package.scala:16:47]
wire _is_mini_exception_T_1 = io_com_xcpt_bits_cause_0 == 64'h11; // @[package.scala:16:47]
wire is_mini_exception = _is_mini_exception_T | _is_mini_exception_T_1; // @[package.scala:16:47, :81:59]
wire _io_com_xcpt_valid_T = ~is_mini_exception; // @[package.scala:81:59]
assign _io_com_xcpt_valid_T_1 = exception_thrown & _io_com_xcpt_valid_T; // @[rob.scala:253:30, :561:{41,44}]
assign io_com_xcpt_valid_0 = _io_com_xcpt_valid_T_1; // @[rob.scala:211:7, :561:41]
wire _io_com_xcpt_bits_badvaddr_T = r_xcpt_badvaddr[39]; // @[util.scala:261:46]
wire [23:0] _io_com_xcpt_bits_badvaddr_T_1 = {24{_io_com_xcpt_bits_badvaddr_T}}; // @[util.scala:261:{25,46}]
assign _io_com_xcpt_bits_badvaddr_T_2 = {_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr}; // @[util.scala:261:{20,25}]
assign io_com_xcpt_bits_badvaddr_0 = _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:261:20]
wire _insn_sys_pc2epc_T = rob_head_vals_0 | rob_head_vals_1; // @[rob.scala:247:33, :567:27]
wire _insn_sys_pc2epc_T_1 = _insn_sys_pc2epc_T | rob_head_vals_2; // @[rob.scala:247:33, :567:27]
wire _GEN_264 = rob_head_vals_1 ? io_commit_uops_1_is_sys_pc2epc_0 : io_commit_uops_2_is_sys_pc2epc_0; // @[Mux.scala:50:70]
wire _insn_sys_pc2epc_T_2; // @[Mux.scala:50:70]
assign _insn_sys_pc2epc_T_2 = _GEN_264; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
assign _com_xcpt_uop_T_is_sys_pc2epc = _GEN_264; // @[Mux.scala:50:70]
wire _insn_sys_pc2epc_T_3 = rob_head_vals_0 ? io_commit_uops_0_is_sys_pc2epc_0 : _insn_sys_pc2epc_T_2; // @[Mux.scala:50:70]
wire insn_sys_pc2epc = _insn_sys_pc2epc_T_1 & _insn_sys_pc2epc_T_3; // @[Mux.scala:50:70]
wire refetch_inst = exception_thrown | insn_sys_pc2epc; // @[rob.scala:253:30, :567:31, :569:39]
wire [6:0] _com_xcpt_uop_T_uopc = rob_head_vals_1 ? io_commit_uops_1_uopc_0 : io_commit_uops_2_uopc_0; // @[Mux.scala:50:70]
wire [31:0] _com_xcpt_uop_T_inst = rob_head_vals_1 ? io_commit_uops_1_inst_0 : io_commit_uops_2_inst_0; // @[Mux.scala:50:70]
wire [31:0] _com_xcpt_uop_T_debug_inst = rob_head_vals_1 ? io_commit_uops_1_debug_inst_0 : io_commit_uops_2_debug_inst_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_rvc = rob_head_vals_1 ? io_commit_uops_1_is_rvc_0 : io_commit_uops_2_is_rvc_0; // @[Mux.scala:50:70]
wire [39:0] _com_xcpt_uop_T_debug_pc = rob_head_vals_1 ? io_commit_uops_1_debug_pc_0 : io_commit_uops_2_debug_pc_0; // @[Mux.scala:50:70]
wire [2:0] _com_xcpt_uop_T_iq_type = rob_head_vals_1 ? io_commit_uops_1_iq_type_0 : io_commit_uops_2_iq_type_0; // @[Mux.scala:50:70]
wire [9:0] _com_xcpt_uop_T_fu_code = rob_head_vals_1 ? io_commit_uops_1_fu_code_0 : io_commit_uops_2_fu_code_0; // @[Mux.scala:50:70]
wire [3:0] _com_xcpt_uop_T_ctrl_br_type = rob_head_vals_1 ? io_commit_uops_1_ctrl_br_type_0 : io_commit_uops_2_ctrl_br_type_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_ctrl_op1_sel = rob_head_vals_1 ? io_commit_uops_1_ctrl_op1_sel_0 : io_commit_uops_2_ctrl_op1_sel_0; // @[Mux.scala:50:70]
wire [2:0] _com_xcpt_uop_T_ctrl_op2_sel = rob_head_vals_1 ? io_commit_uops_1_ctrl_op2_sel_0 : io_commit_uops_2_ctrl_op2_sel_0; // @[Mux.scala:50:70]
wire [2:0] _com_xcpt_uop_T_ctrl_imm_sel = rob_head_vals_1 ? io_commit_uops_1_ctrl_imm_sel_0 : io_commit_uops_2_ctrl_imm_sel_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_ctrl_op_fcn = rob_head_vals_1 ? io_commit_uops_1_ctrl_op_fcn_0 : io_commit_uops_2_ctrl_op_fcn_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ctrl_fcn_dw = rob_head_vals_1 ? io_commit_uops_1_ctrl_fcn_dw_0 : io_commit_uops_2_ctrl_fcn_dw_0; // @[Mux.scala:50:70]
wire [2:0] _com_xcpt_uop_T_ctrl_csr_cmd = rob_head_vals_1 ? io_commit_uops_1_ctrl_csr_cmd_0 : io_commit_uops_2_ctrl_csr_cmd_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ctrl_is_load = rob_head_vals_1 ? io_commit_uops_1_ctrl_is_load_0 : io_commit_uops_2_ctrl_is_load_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ctrl_is_sta = rob_head_vals_1 ? io_commit_uops_1_ctrl_is_sta_0 : io_commit_uops_2_ctrl_is_sta_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ctrl_is_std = rob_head_vals_1 ? io_commit_uops_1_ctrl_is_std_0 : io_commit_uops_2_ctrl_is_std_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_iw_state = rob_head_vals_1 ? io_commit_uops_1_iw_state_0 : io_commit_uops_2_iw_state_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_iw_p1_poisoned = rob_head_vals_1 ? io_commit_uops_1_iw_p1_poisoned_0 : io_commit_uops_2_iw_p1_poisoned_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_iw_p2_poisoned = rob_head_vals_1 ? io_commit_uops_1_iw_p2_poisoned_0 : io_commit_uops_2_iw_p2_poisoned_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_br = rob_head_vals_1 ? io_commit_uops_1_is_br_0 : io_commit_uops_2_is_br_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_jalr = rob_head_vals_1 ? io_commit_uops_1_is_jalr_0 : io_commit_uops_2_is_jalr_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_jal = rob_head_vals_1 ? io_commit_uops_1_is_jal_0 : io_commit_uops_2_is_jal_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_sfb = rob_head_vals_1 ? io_commit_uops_1_is_sfb_0 : io_commit_uops_2_is_sfb_0; // @[Mux.scala:50:70]
wire [15:0] _com_xcpt_uop_T_br_mask = rob_head_vals_1 ? io_commit_uops_1_br_mask_0 : io_commit_uops_2_br_mask_0; // @[Mux.scala:50:70]
wire [3:0] _com_xcpt_uop_T_br_tag = rob_head_vals_1 ? io_commit_uops_1_br_tag_0 : io_commit_uops_2_br_tag_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_ftq_idx = rob_head_vals_1 ? io_commit_uops_1_ftq_idx_0 : io_commit_uops_2_ftq_idx_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_edge_inst = rob_head_vals_1 ? io_commit_uops_1_edge_inst_0 : io_commit_uops_2_edge_inst_0; // @[Mux.scala:50:70]
wire [5:0] _com_xcpt_uop_T_pc_lob = rob_head_vals_1 ? io_commit_uops_1_pc_lob_0 : io_commit_uops_2_pc_lob_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_taken = rob_head_vals_1 ? io_commit_uops_1_taken_0 : io_commit_uops_2_taken_0; // @[Mux.scala:50:70]
wire [19:0] _com_xcpt_uop_T_imm_packed = rob_head_vals_1 ? io_commit_uops_1_imm_packed_0 : io_commit_uops_2_imm_packed_0; // @[Mux.scala:50:70]
wire [11:0] _com_xcpt_uop_T_csr_addr = rob_head_vals_1 ? io_commit_uops_1_csr_addr_0 : io_commit_uops_2_csr_addr_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_rob_idx = rob_head_vals_1 ? io_commit_uops_1_rob_idx_0 : io_commit_uops_2_rob_idx_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_ldq_idx = rob_head_vals_1 ? io_commit_uops_1_ldq_idx_0 : io_commit_uops_2_ldq_idx_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_stq_idx = rob_head_vals_1 ? io_commit_uops_1_stq_idx_0 : io_commit_uops_2_stq_idx_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_rxq_idx = rob_head_vals_1 ? io_commit_uops_1_rxq_idx_0 : io_commit_uops_2_rxq_idx_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_pdst = rob_head_vals_1 ? io_commit_uops_1_pdst_0 : io_commit_uops_2_pdst_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_prs1 = rob_head_vals_1 ? io_commit_uops_1_prs1_0 : io_commit_uops_2_prs1_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_prs2 = rob_head_vals_1 ? io_commit_uops_1_prs2_0 : io_commit_uops_2_prs2_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_prs3 = rob_head_vals_1 ? io_commit_uops_1_prs3_0 : io_commit_uops_2_prs3_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_ppred = rob_head_vals_1 ? io_commit_uops_1_ppred_0 : io_commit_uops_2_ppred_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_prs1_busy = rob_head_vals_1 ? io_commit_uops_1_prs1_busy_0 : io_commit_uops_2_prs1_busy_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_prs2_busy = rob_head_vals_1 ? io_commit_uops_1_prs2_busy_0 : io_commit_uops_2_prs2_busy_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_prs3_busy = rob_head_vals_1 ? io_commit_uops_1_prs3_busy_0 : io_commit_uops_2_prs3_busy_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ppred_busy = rob_head_vals_1 ? io_commit_uops_1_ppred_busy_0 : io_commit_uops_2_ppred_busy_0; // @[Mux.scala:50:70]
wire [6:0] _com_xcpt_uop_T_stale_pdst = rob_head_vals_1 ? io_commit_uops_1_stale_pdst_0 : io_commit_uops_2_stale_pdst_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_exception = rob_head_vals_1 ? io_commit_uops_1_exception_0 : io_commit_uops_2_exception_0; // @[Mux.scala:50:70]
wire [63:0] _com_xcpt_uop_T_exc_cause = rob_head_vals_1 ? io_commit_uops_1_exc_cause_0 : io_commit_uops_2_exc_cause_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_bypassable = rob_head_vals_1 ? io_commit_uops_1_bypassable_0 : io_commit_uops_2_bypassable_0; // @[Mux.scala:50:70]
wire [4:0] _com_xcpt_uop_T_mem_cmd = rob_head_vals_1 ? io_commit_uops_1_mem_cmd_0 : io_commit_uops_2_mem_cmd_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_mem_size = rob_head_vals_1 ? io_commit_uops_1_mem_size_0 : io_commit_uops_2_mem_size_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_mem_signed = rob_head_vals_1 ? io_commit_uops_1_mem_signed_0 : io_commit_uops_2_mem_signed_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_fence = rob_head_vals_1 ? io_commit_uops_1_is_fence_0 : io_commit_uops_2_is_fence_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_fencei = rob_head_vals_1 ? io_commit_uops_1_is_fencei_0 : io_commit_uops_2_is_fencei_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_amo = rob_head_vals_1 ? io_commit_uops_1_is_amo_0 : io_commit_uops_2_is_amo_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_uses_ldq = rob_head_vals_1 ? io_commit_uops_1_uses_ldq_0 : io_commit_uops_2_uses_ldq_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_uses_stq = rob_head_vals_1 ? io_commit_uops_1_uses_stq_0 : io_commit_uops_2_uses_stq_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_is_unique = rob_head_vals_1 ? io_commit_uops_1_is_unique_0 : io_commit_uops_2_is_unique_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_flush_on_commit = rob_head_vals_1 ? io_commit_uops_1_flush_on_commit_0 : io_commit_uops_2_flush_on_commit_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ldst_is_rs1 = rob_head_vals_1 ? io_commit_uops_1_ldst_is_rs1_0 : io_commit_uops_2_ldst_is_rs1_0; // @[Mux.scala:50:70]
wire [5:0] _com_xcpt_uop_T_ldst = rob_head_vals_1 ? io_commit_uops_1_ldst_0 : io_commit_uops_2_ldst_0; // @[Mux.scala:50:70]
wire [5:0] _com_xcpt_uop_T_lrs1 = rob_head_vals_1 ? io_commit_uops_1_lrs1_0 : io_commit_uops_2_lrs1_0; // @[Mux.scala:50:70]
wire [5:0] _com_xcpt_uop_T_lrs2 = rob_head_vals_1 ? io_commit_uops_1_lrs2_0 : io_commit_uops_2_lrs2_0; // @[Mux.scala:50:70]
wire [5:0] _com_xcpt_uop_T_lrs3 = rob_head_vals_1 ? io_commit_uops_1_lrs3_0 : io_commit_uops_2_lrs3_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_ldst_val = rob_head_vals_1 ? io_commit_uops_1_ldst_val_0 : io_commit_uops_2_ldst_val_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_dst_rtype = rob_head_vals_1 ? io_commit_uops_1_dst_rtype_0 : io_commit_uops_2_dst_rtype_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_lrs1_rtype = rob_head_vals_1 ? io_commit_uops_1_lrs1_rtype_0 : io_commit_uops_2_lrs1_rtype_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_lrs2_rtype = rob_head_vals_1 ? io_commit_uops_1_lrs2_rtype_0 : io_commit_uops_2_lrs2_rtype_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_frs3_en = rob_head_vals_1 ? io_commit_uops_1_frs3_en_0 : io_commit_uops_2_frs3_en_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_fp_val = rob_head_vals_1 ? io_commit_uops_1_fp_val_0 : io_commit_uops_2_fp_val_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_fp_single = rob_head_vals_1 ? io_commit_uops_1_fp_single_0 : io_commit_uops_2_fp_single_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_xcpt_pf_if = rob_head_vals_1 ? io_commit_uops_1_xcpt_pf_if_0 : io_commit_uops_2_xcpt_pf_if_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_xcpt_ae_if = rob_head_vals_1 ? io_commit_uops_1_xcpt_ae_if_0 : io_commit_uops_2_xcpt_ae_if_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_xcpt_ma_if = rob_head_vals_1 ? io_commit_uops_1_xcpt_ma_if_0 : io_commit_uops_2_xcpt_ma_if_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_bp_debug_if = rob_head_vals_1 ? io_commit_uops_1_bp_debug_if_0 : io_commit_uops_2_bp_debug_if_0; // @[Mux.scala:50:70]
wire _com_xcpt_uop_T_bp_xcpt_if = rob_head_vals_1 ? io_commit_uops_1_bp_xcpt_if_0 : io_commit_uops_2_bp_xcpt_if_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_debug_fsrc = rob_head_vals_1 ? io_commit_uops_1_debug_fsrc_0 : io_commit_uops_2_debug_fsrc_0; // @[Mux.scala:50:70]
wire [1:0] _com_xcpt_uop_T_debug_tsrc = rob_head_vals_1 ? io_commit_uops_1_debug_tsrc_0 : io_commit_uops_2_debug_tsrc_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_uopc = rob_head_vals_0 ? io_commit_uops_0_uopc_0 : _com_xcpt_uop_T_uopc; // @[Mux.scala:50:70]
wire [31:0] com_xcpt_uop_inst = rob_head_vals_0 ? io_commit_uops_0_inst_0 : _com_xcpt_uop_T_inst; // @[Mux.scala:50:70]
wire [31:0] com_xcpt_uop_debug_inst = rob_head_vals_0 ? io_commit_uops_0_debug_inst_0 : _com_xcpt_uop_T_debug_inst; // @[Mux.scala:50:70]
assign com_xcpt_uop_is_rvc = rob_head_vals_0 ? io_commit_uops_0_is_rvc_0 : _com_xcpt_uop_T_is_rvc; // @[Mux.scala:50:70]
wire [39:0] com_xcpt_uop_debug_pc = rob_head_vals_0 ? io_commit_uops_0_debug_pc_0 : _com_xcpt_uop_T_debug_pc; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_iq_type = rob_head_vals_0 ? io_commit_uops_0_iq_type_0 : _com_xcpt_uop_T_iq_type; // @[Mux.scala:50:70]
wire [9:0] com_xcpt_uop_fu_code = rob_head_vals_0 ? io_commit_uops_0_fu_code_0 : _com_xcpt_uop_T_fu_code; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_ctrl_br_type = rob_head_vals_0 ? io_commit_uops_0_ctrl_br_type_0 : _com_xcpt_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_ctrl_op1_sel = rob_head_vals_0 ? io_commit_uops_0_ctrl_op1_sel_0 : _com_xcpt_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_ctrl_op2_sel = rob_head_vals_0 ? io_commit_uops_0_ctrl_op2_sel_0 : _com_xcpt_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_ctrl_imm_sel = rob_head_vals_0 ? io_commit_uops_0_ctrl_imm_sel_0 : _com_xcpt_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_ctrl_op_fcn = rob_head_vals_0 ? io_commit_uops_0_ctrl_op_fcn_0 : _com_xcpt_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
wire com_xcpt_uop_ctrl_fcn_dw = rob_head_vals_0 ? io_commit_uops_0_ctrl_fcn_dw_0 : _com_xcpt_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_ctrl_csr_cmd = rob_head_vals_0 ? io_commit_uops_0_ctrl_csr_cmd_0 : _com_xcpt_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70]
wire com_xcpt_uop_ctrl_is_load = rob_head_vals_0 ? io_commit_uops_0_ctrl_is_load_0 : _com_xcpt_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
wire com_xcpt_uop_ctrl_is_sta = rob_head_vals_0 ? io_commit_uops_0_ctrl_is_sta_0 : _com_xcpt_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
wire com_xcpt_uop_ctrl_is_std = rob_head_vals_0 ? io_commit_uops_0_ctrl_is_std_0 : _com_xcpt_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_iw_state = rob_head_vals_0 ? io_commit_uops_0_iw_state_0 : _com_xcpt_uop_T_iw_state; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_p1_poisoned = rob_head_vals_0 ? io_commit_uops_0_iw_p1_poisoned_0 : _com_xcpt_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_p2_poisoned = rob_head_vals_0 ? io_commit_uops_0_iw_p2_poisoned_0 : _com_xcpt_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_br = rob_head_vals_0 ? io_commit_uops_0_is_br_0 : _com_xcpt_uop_T_is_br; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_jalr = rob_head_vals_0 ? io_commit_uops_0_is_jalr_0 : _com_xcpt_uop_T_is_jalr; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_jal = rob_head_vals_0 ? io_commit_uops_0_is_jal_0 : _com_xcpt_uop_T_is_jal; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_sfb = rob_head_vals_0 ? io_commit_uops_0_is_sfb_0 : _com_xcpt_uop_T_is_sfb; // @[Mux.scala:50:70]
wire [15:0] com_xcpt_uop_br_mask = rob_head_vals_0 ? io_commit_uops_0_br_mask_0 : _com_xcpt_uop_T_br_mask; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_br_tag = rob_head_vals_0 ? io_commit_uops_0_br_tag_0 : _com_xcpt_uop_T_br_tag; // @[Mux.scala:50:70]
assign com_xcpt_uop_ftq_idx = rob_head_vals_0 ? io_commit_uops_0_ftq_idx_0 : _com_xcpt_uop_T_ftq_idx; // @[Mux.scala:50:70]
assign com_xcpt_uop_edge_inst = rob_head_vals_0 ? io_commit_uops_0_edge_inst_0 : _com_xcpt_uop_T_edge_inst; // @[Mux.scala:50:70]
assign com_xcpt_uop_pc_lob = rob_head_vals_0 ? io_commit_uops_0_pc_lob_0 : _com_xcpt_uop_T_pc_lob; // @[Mux.scala:50:70]
wire com_xcpt_uop_taken = rob_head_vals_0 ? io_commit_uops_0_taken_0 : _com_xcpt_uop_T_taken; // @[Mux.scala:50:70]
wire [19:0] com_xcpt_uop_imm_packed = rob_head_vals_0 ? io_commit_uops_0_imm_packed_0 : _com_xcpt_uop_T_imm_packed; // @[Mux.scala:50:70]
wire [11:0] com_xcpt_uop_csr_addr = rob_head_vals_0 ? io_commit_uops_0_csr_addr_0 : _com_xcpt_uop_T_csr_addr; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_rob_idx = rob_head_vals_0 ? io_commit_uops_0_rob_idx_0 : _com_xcpt_uop_T_rob_idx; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_ldq_idx = rob_head_vals_0 ? io_commit_uops_0_ldq_idx_0 : _com_xcpt_uop_T_ldq_idx; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_stq_idx = rob_head_vals_0 ? io_commit_uops_0_stq_idx_0 : _com_xcpt_uop_T_stq_idx; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_rxq_idx = rob_head_vals_0 ? io_commit_uops_0_rxq_idx_0 : _com_xcpt_uop_T_rxq_idx; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_pdst = rob_head_vals_0 ? io_commit_uops_0_pdst_0 : _com_xcpt_uop_T_pdst; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs1 = rob_head_vals_0 ? io_commit_uops_0_prs1_0 : _com_xcpt_uop_T_prs1; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs2 = rob_head_vals_0 ? io_commit_uops_0_prs2_0 : _com_xcpt_uop_T_prs2; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs3 = rob_head_vals_0 ? io_commit_uops_0_prs3_0 : _com_xcpt_uop_T_prs3; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_ppred = rob_head_vals_0 ? io_commit_uops_0_ppred_0 : _com_xcpt_uop_T_ppred; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs1_busy = rob_head_vals_0 ? io_commit_uops_0_prs1_busy_0 : _com_xcpt_uop_T_prs1_busy; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs2_busy = rob_head_vals_0 ? io_commit_uops_0_prs2_busy_0 : _com_xcpt_uop_T_prs2_busy; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs3_busy = rob_head_vals_0 ? io_commit_uops_0_prs3_busy_0 : _com_xcpt_uop_T_prs3_busy; // @[Mux.scala:50:70]
wire com_xcpt_uop_ppred_busy = rob_head_vals_0 ? io_commit_uops_0_ppred_busy_0 : _com_xcpt_uop_T_ppred_busy; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_stale_pdst = rob_head_vals_0 ? io_commit_uops_0_stale_pdst_0 : _com_xcpt_uop_T_stale_pdst; // @[Mux.scala:50:70]
wire com_xcpt_uop_exception = rob_head_vals_0 ? io_commit_uops_0_exception_0 : _com_xcpt_uop_T_exception; // @[Mux.scala:50:70]
wire [63:0] com_xcpt_uop_exc_cause = rob_head_vals_0 ? io_commit_uops_0_exc_cause_0 : _com_xcpt_uop_T_exc_cause; // @[Mux.scala:50:70]
wire com_xcpt_uop_bypassable = rob_head_vals_0 ? io_commit_uops_0_bypassable_0 : _com_xcpt_uop_T_bypassable; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_mem_cmd = rob_head_vals_0 ? io_commit_uops_0_mem_cmd_0 : _com_xcpt_uop_T_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_mem_size = rob_head_vals_0 ? io_commit_uops_0_mem_size_0 : _com_xcpt_uop_T_mem_size; // @[Mux.scala:50:70]
wire com_xcpt_uop_mem_signed = rob_head_vals_0 ? io_commit_uops_0_mem_signed_0 : _com_xcpt_uop_T_mem_signed; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_fence = rob_head_vals_0 ? io_commit_uops_0_is_fence_0 : _com_xcpt_uop_T_is_fence; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_fencei = rob_head_vals_0 ? io_commit_uops_0_is_fencei_0 : _com_xcpt_uop_T_is_fencei; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_amo = rob_head_vals_0 ? io_commit_uops_0_is_amo_0 : _com_xcpt_uop_T_is_amo; // @[Mux.scala:50:70]
wire com_xcpt_uop_uses_ldq = rob_head_vals_0 ? io_commit_uops_0_uses_ldq_0 : _com_xcpt_uop_T_uses_ldq; // @[Mux.scala:50:70]
wire com_xcpt_uop_uses_stq = rob_head_vals_0 ? io_commit_uops_0_uses_stq_0 : _com_xcpt_uop_T_uses_stq; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_sys_pc2epc = rob_head_vals_0 ? io_commit_uops_0_is_sys_pc2epc_0 : _com_xcpt_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_unique = rob_head_vals_0 ? io_commit_uops_0_is_unique_0 : _com_xcpt_uop_T_is_unique; // @[Mux.scala:50:70]
wire com_xcpt_uop_flush_on_commit = rob_head_vals_0 ? io_commit_uops_0_flush_on_commit_0 : _com_xcpt_uop_T_flush_on_commit; // @[Mux.scala:50:70]
wire com_xcpt_uop_ldst_is_rs1 = rob_head_vals_0 ? io_commit_uops_0_ldst_is_rs1_0 : _com_xcpt_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_ldst = rob_head_vals_0 ? io_commit_uops_0_ldst_0 : _com_xcpt_uop_T_ldst; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs1 = rob_head_vals_0 ? io_commit_uops_0_lrs1_0 : _com_xcpt_uop_T_lrs1; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs2 = rob_head_vals_0 ? io_commit_uops_0_lrs2_0 : _com_xcpt_uop_T_lrs2; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs3 = rob_head_vals_0 ? io_commit_uops_0_lrs3_0 : _com_xcpt_uop_T_lrs3; // @[Mux.scala:50:70]
wire com_xcpt_uop_ldst_val = rob_head_vals_0 ? io_commit_uops_0_ldst_val_0 : _com_xcpt_uop_T_ldst_val; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_dst_rtype = rob_head_vals_0 ? io_commit_uops_0_dst_rtype_0 : _com_xcpt_uop_T_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_lrs1_rtype = rob_head_vals_0 ? io_commit_uops_0_lrs1_rtype_0 : _com_xcpt_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_lrs2_rtype = rob_head_vals_0 ? io_commit_uops_0_lrs2_rtype_0 : _com_xcpt_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
wire com_xcpt_uop_frs3_en = rob_head_vals_0 ? io_commit_uops_0_frs3_en_0 : _com_xcpt_uop_T_frs3_en; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_val = rob_head_vals_0 ? io_commit_uops_0_fp_val_0 : _com_xcpt_uop_T_fp_val; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_single = rob_head_vals_0 ? io_commit_uops_0_fp_single_0 : _com_xcpt_uop_T_fp_single; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_pf_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_pf_if_0 : _com_xcpt_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_ae_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_ae_if_0 : _com_xcpt_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_ma_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_ma_if_0 : _com_xcpt_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
wire com_xcpt_uop_bp_debug_if = rob_head_vals_0 ? io_commit_uops_0_bp_debug_if_0 : _com_xcpt_uop_T_bp_debug_if; // @[Mux.scala:50:70]
wire com_xcpt_uop_bp_xcpt_if = rob_head_vals_0 ? io_commit_uops_0_bp_xcpt_if_0 : _com_xcpt_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_debug_fsrc = rob_head_vals_0 ? io_commit_uops_0_debug_fsrc_0 : _com_xcpt_uop_T_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_debug_tsrc = rob_head_vals_0 ? io_commit_uops_0_debug_tsrc_0 : _com_xcpt_uop_T_debug_tsrc; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_is_rvc = com_xcpt_uop_is_rvc; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_ftq_idx_0 = com_xcpt_uop_ftq_idx; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_edge_inst_0 = com_xcpt_uop_edge_inst; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_pc_lob_0 = com_xcpt_uop_pc_lob; // @[Mux.scala:50:70]
wire flush_commit_mask_0 = io_commit_valids_0_0 & io_commit_uops_0_flush_on_commit_0; // @[rob.scala:211:7, :576:75]
wire flush_commit_mask_1 = io_commit_valids_1_0 & io_commit_uops_1_flush_on_commit_0; // @[rob.scala:211:7, :576:75]
wire flush_commit_mask_2 = io_commit_valids_2_0 & io_commit_uops_2_flush_on_commit_0; // @[rob.scala:211:7, :576:75]
wire _flush_commit_T = flush_commit_mask_0 | flush_commit_mask_1; // @[rob.scala:576:75, :577:48]
wire flush_commit = _flush_commit_T | flush_commit_mask_2; // @[rob.scala:576:75, :577:48]
assign flush_val = exception_thrown | flush_commit; // @[rob.scala:253:30, :577:48, :578:36]
assign io_flush_valid_0 = flush_val; // @[rob.scala:211:7, :578:36]
wire [6:0] _flush_uop_WIRE_80; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_79; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_78; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_77; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_WIRE_76; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_75; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_WIRE_74; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_63_br_type; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_63_op1_sel; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_63_op2_sel; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_63_imm_sel; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_63_op_fcn; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_63_fcn_dw; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_63_csr_cmd; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_63_is_load; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_63_is_sta; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_63_is_std; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_62; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_61; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_60; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_59; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_58; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_57; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_56; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_WIRE_55; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_54; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_53; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_52; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_51; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_50; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_WIRE_49; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_WIRE_48; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_47; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_46; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_45; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_44; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_43; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_42; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_41; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_40; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_39; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_38; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_37; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_36; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_35; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_34; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_33; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_WIRE_32; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_31; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_30; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_29; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_28; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_27; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_26; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_25; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_24; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_23; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_22; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_21; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_20; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_19; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_18; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_17; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_16; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_15; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_14; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_13; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_12; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_11; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_10; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_9; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_8; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_7; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_6; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_5; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_4; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T = flush_commit_mask_0 ? io_commit_uops_0_debug_tsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_1 = flush_commit_mask_1 ? io_commit_uops_1_debug_tsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_2 = flush_commit_mask_2 ? io_commit_uops_2_debug_tsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_3 = _flush_uop_T | _flush_uop_T_1; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_4 = _flush_uop_T_3 | _flush_uop_T_2; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_1 = _flush_uop_T_4; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_debug_tsrc = _flush_uop_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_5 = flush_commit_mask_0 ? io_commit_uops_0_debug_fsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_6 = flush_commit_mask_1 ? io_commit_uops_1_debug_fsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_7 = flush_commit_mask_2 ? io_commit_uops_2_debug_fsrc_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_8 = _flush_uop_T_5 | _flush_uop_T_6; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_9 = _flush_uop_T_8 | _flush_uop_T_7; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_2 = _flush_uop_T_9; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_debug_fsrc = _flush_uop_WIRE_2; // @[Mux.scala:30:73]
wire _flush_uop_T_10 = flush_commit_mask_0 & io_commit_uops_0_bp_xcpt_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_11 = flush_commit_mask_1 & io_commit_uops_1_bp_xcpt_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_12 = flush_commit_mask_2 & io_commit_uops_2_bp_xcpt_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_13 = _flush_uop_T_10 | _flush_uop_T_11; // @[Mux.scala:30:73]
wire _flush_uop_T_14 = _flush_uop_T_13 | _flush_uop_T_12; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_3 = _flush_uop_T_14; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_bp_xcpt_if = _flush_uop_WIRE_3; // @[Mux.scala:30:73]
wire _flush_uop_T_15 = flush_commit_mask_0 & io_commit_uops_0_bp_debug_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_16 = flush_commit_mask_1 & io_commit_uops_1_bp_debug_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_17 = flush_commit_mask_2 & io_commit_uops_2_bp_debug_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_18 = _flush_uop_T_15 | _flush_uop_T_16; // @[Mux.scala:30:73]
wire _flush_uop_T_19 = _flush_uop_T_18 | _flush_uop_T_17; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_4 = _flush_uop_T_19; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_bp_debug_if = _flush_uop_WIRE_4; // @[Mux.scala:30:73]
wire _flush_uop_T_20 = flush_commit_mask_0 & io_commit_uops_0_xcpt_ma_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_21 = flush_commit_mask_1 & io_commit_uops_1_xcpt_ma_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_22 = flush_commit_mask_2 & io_commit_uops_2_xcpt_ma_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_23 = _flush_uop_T_20 | _flush_uop_T_21; // @[Mux.scala:30:73]
wire _flush_uop_T_24 = _flush_uop_T_23 | _flush_uop_T_22; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_5 = _flush_uop_T_24; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_ma_if = _flush_uop_WIRE_5; // @[Mux.scala:30:73]
wire _flush_uop_T_25 = flush_commit_mask_0 & io_commit_uops_0_xcpt_ae_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_26 = flush_commit_mask_1 & io_commit_uops_1_xcpt_ae_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_27 = flush_commit_mask_2 & io_commit_uops_2_xcpt_ae_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_28 = _flush_uop_T_25 | _flush_uop_T_26; // @[Mux.scala:30:73]
wire _flush_uop_T_29 = _flush_uop_T_28 | _flush_uop_T_27; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_6 = _flush_uop_T_29; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_ae_if = _flush_uop_WIRE_6; // @[Mux.scala:30:73]
wire _flush_uop_T_30 = flush_commit_mask_0 & io_commit_uops_0_xcpt_pf_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_31 = flush_commit_mask_1 & io_commit_uops_1_xcpt_pf_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_32 = flush_commit_mask_2 & io_commit_uops_2_xcpt_pf_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_33 = _flush_uop_T_30 | _flush_uop_T_31; // @[Mux.scala:30:73]
wire _flush_uop_T_34 = _flush_uop_T_33 | _flush_uop_T_32; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_7 = _flush_uop_T_34; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_pf_if = _flush_uop_WIRE_7; // @[Mux.scala:30:73]
wire _flush_uop_T_35 = flush_commit_mask_0 & io_commit_uops_0_fp_single_0; // @[Mux.scala:30:73]
wire _flush_uop_T_36 = flush_commit_mask_1 & io_commit_uops_1_fp_single_0; // @[Mux.scala:30:73]
wire _flush_uop_T_37 = flush_commit_mask_2 & io_commit_uops_2_fp_single_0; // @[Mux.scala:30:73]
wire _flush_uop_T_38 = _flush_uop_T_35 | _flush_uop_T_36; // @[Mux.scala:30:73]
wire _flush_uop_T_39 = _flush_uop_T_38 | _flush_uop_T_37; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_8 = _flush_uop_T_39; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_single = _flush_uop_WIRE_8; // @[Mux.scala:30:73]
wire _flush_uop_T_40 = flush_commit_mask_0 & io_commit_uops_0_fp_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_41 = flush_commit_mask_1 & io_commit_uops_1_fp_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_42 = flush_commit_mask_2 & io_commit_uops_2_fp_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_43 = _flush_uop_T_40 | _flush_uop_T_41; // @[Mux.scala:30:73]
wire _flush_uop_T_44 = _flush_uop_T_43 | _flush_uop_T_42; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_9 = _flush_uop_T_44; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_val = _flush_uop_WIRE_9; // @[Mux.scala:30:73]
wire _flush_uop_T_45 = flush_commit_mask_0 & io_commit_uops_0_frs3_en_0; // @[Mux.scala:30:73]
wire _flush_uop_T_46 = flush_commit_mask_1 & io_commit_uops_1_frs3_en_0; // @[Mux.scala:30:73]
wire _flush_uop_T_47 = flush_commit_mask_2 & io_commit_uops_2_frs3_en_0; // @[Mux.scala:30:73]
wire _flush_uop_T_48 = _flush_uop_T_45 | _flush_uop_T_46; // @[Mux.scala:30:73]
wire _flush_uop_T_49 = _flush_uop_T_48 | _flush_uop_T_47; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_10 = _flush_uop_T_49; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_frs3_en = _flush_uop_WIRE_10; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_50 = flush_commit_mask_0 ? io_commit_uops_0_lrs2_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_51 = flush_commit_mask_1 ? io_commit_uops_1_lrs2_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_52 = flush_commit_mask_2 ? io_commit_uops_2_lrs2_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_53 = _flush_uop_T_50 | _flush_uop_T_51; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_54 = _flush_uop_T_53 | _flush_uop_T_52; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_11 = _flush_uop_T_54; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_lrs2_rtype = _flush_uop_WIRE_11; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_55 = flush_commit_mask_0 ? io_commit_uops_0_lrs1_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_56 = flush_commit_mask_1 ? io_commit_uops_1_lrs1_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_57 = flush_commit_mask_2 ? io_commit_uops_2_lrs1_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_58 = _flush_uop_T_55 | _flush_uop_T_56; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_59 = _flush_uop_T_58 | _flush_uop_T_57; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_12 = _flush_uop_T_59; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_lrs1_rtype = _flush_uop_WIRE_12; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_60 = flush_commit_mask_0 ? io_commit_uops_0_dst_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_61 = flush_commit_mask_1 ? io_commit_uops_1_dst_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_62 = flush_commit_mask_2 ? io_commit_uops_2_dst_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_63 = _flush_uop_T_60 | _flush_uop_T_61; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_64 = _flush_uop_T_63 | _flush_uop_T_62; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_13 = _flush_uop_T_64; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_dst_rtype = _flush_uop_WIRE_13; // @[Mux.scala:30:73]
wire _flush_uop_T_65 = flush_commit_mask_0 & io_commit_uops_0_ldst_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_66 = flush_commit_mask_1 & io_commit_uops_1_ldst_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_67 = flush_commit_mask_2 & io_commit_uops_2_ldst_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_68 = _flush_uop_T_65 | _flush_uop_T_66; // @[Mux.scala:30:73]
wire _flush_uop_T_69 = _flush_uop_T_68 | _flush_uop_T_67; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_14 = _flush_uop_T_69; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ldst_val = _flush_uop_WIRE_14; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_70 = flush_commit_mask_0 ? io_commit_uops_0_lrs3_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_71 = flush_commit_mask_1 ? io_commit_uops_1_lrs3_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_72 = flush_commit_mask_2 ? io_commit_uops_2_lrs3_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_73 = _flush_uop_T_70 | _flush_uop_T_71; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_74 = _flush_uop_T_73 | _flush_uop_T_72; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_15 = _flush_uop_T_74; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs3 = _flush_uop_WIRE_15; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_75 = flush_commit_mask_0 ? io_commit_uops_0_lrs2_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_76 = flush_commit_mask_1 ? io_commit_uops_1_lrs2_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_77 = flush_commit_mask_2 ? io_commit_uops_2_lrs2_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_78 = _flush_uop_T_75 | _flush_uop_T_76; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_79 = _flush_uop_T_78 | _flush_uop_T_77; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_16 = _flush_uop_T_79; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs2 = _flush_uop_WIRE_16; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_80 = flush_commit_mask_0 ? io_commit_uops_0_lrs1_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_81 = flush_commit_mask_1 ? io_commit_uops_1_lrs1_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_82 = flush_commit_mask_2 ? io_commit_uops_2_lrs1_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_83 = _flush_uop_T_80 | _flush_uop_T_81; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_84 = _flush_uop_T_83 | _flush_uop_T_82; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_17 = _flush_uop_T_84; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs1 = _flush_uop_WIRE_17; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_85 = flush_commit_mask_0 ? io_commit_uops_0_ldst_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_86 = flush_commit_mask_1 ? io_commit_uops_1_ldst_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_87 = flush_commit_mask_2 ? io_commit_uops_2_ldst_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_88 = _flush_uop_T_85 | _flush_uop_T_86; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_89 = _flush_uop_T_88 | _flush_uop_T_87; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_18 = _flush_uop_T_89; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_ldst = _flush_uop_WIRE_18; // @[Mux.scala:30:73]
wire _flush_uop_T_90 = flush_commit_mask_0 & io_commit_uops_0_ldst_is_rs1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_91 = flush_commit_mask_1 & io_commit_uops_1_ldst_is_rs1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_92 = flush_commit_mask_2 & io_commit_uops_2_ldst_is_rs1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_93 = _flush_uop_T_90 | _flush_uop_T_91; // @[Mux.scala:30:73]
wire _flush_uop_T_94 = _flush_uop_T_93 | _flush_uop_T_92; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_19 = _flush_uop_T_94; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ldst_is_rs1 = _flush_uop_WIRE_19; // @[Mux.scala:30:73]
wire _flush_uop_T_95 = flush_commit_mask_0 & io_commit_uops_0_flush_on_commit_0; // @[Mux.scala:30:73]
wire _flush_uop_T_96 = flush_commit_mask_1 & io_commit_uops_1_flush_on_commit_0; // @[Mux.scala:30:73]
wire _flush_uop_T_97 = flush_commit_mask_2 & io_commit_uops_2_flush_on_commit_0; // @[Mux.scala:30:73]
wire _flush_uop_T_98 = _flush_uop_T_95 | _flush_uop_T_96; // @[Mux.scala:30:73]
wire _flush_uop_T_99 = _flush_uop_T_98 | _flush_uop_T_97; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_20 = _flush_uop_T_99; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_flush_on_commit = _flush_uop_WIRE_20; // @[Mux.scala:30:73]
wire _flush_uop_T_100 = flush_commit_mask_0 & io_commit_uops_0_is_unique_0; // @[Mux.scala:30:73]
wire _flush_uop_T_101 = flush_commit_mask_1 & io_commit_uops_1_is_unique_0; // @[Mux.scala:30:73]
wire _flush_uop_T_102 = flush_commit_mask_2 & io_commit_uops_2_is_unique_0; // @[Mux.scala:30:73]
wire _flush_uop_T_103 = _flush_uop_T_100 | _flush_uop_T_101; // @[Mux.scala:30:73]
wire _flush_uop_T_104 = _flush_uop_T_103 | _flush_uop_T_102; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_21 = _flush_uop_T_104; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_unique = _flush_uop_WIRE_21; // @[Mux.scala:30:73]
wire _flush_uop_T_105 = flush_commit_mask_0 & io_commit_uops_0_is_sys_pc2epc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_106 = flush_commit_mask_1 & io_commit_uops_1_is_sys_pc2epc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_107 = flush_commit_mask_2 & io_commit_uops_2_is_sys_pc2epc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_108 = _flush_uop_T_105 | _flush_uop_T_106; // @[Mux.scala:30:73]
wire _flush_uop_T_109 = _flush_uop_T_108 | _flush_uop_T_107; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_22 = _flush_uop_T_109; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_sys_pc2epc = _flush_uop_WIRE_22; // @[Mux.scala:30:73]
wire _flush_uop_T_110 = flush_commit_mask_0 & io_commit_uops_0_uses_stq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_111 = flush_commit_mask_1 & io_commit_uops_1_uses_stq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_112 = flush_commit_mask_2 & io_commit_uops_2_uses_stq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_113 = _flush_uop_T_110 | _flush_uop_T_111; // @[Mux.scala:30:73]
wire _flush_uop_T_114 = _flush_uop_T_113 | _flush_uop_T_112; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_23 = _flush_uop_T_114; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_uses_stq = _flush_uop_WIRE_23; // @[Mux.scala:30:73]
wire _flush_uop_T_115 = flush_commit_mask_0 & io_commit_uops_0_uses_ldq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_116 = flush_commit_mask_1 & io_commit_uops_1_uses_ldq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_117 = flush_commit_mask_2 & io_commit_uops_2_uses_ldq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_118 = _flush_uop_T_115 | _flush_uop_T_116; // @[Mux.scala:30:73]
wire _flush_uop_T_119 = _flush_uop_T_118 | _flush_uop_T_117; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_24 = _flush_uop_T_119; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_uses_ldq = _flush_uop_WIRE_24; // @[Mux.scala:30:73]
wire _flush_uop_T_120 = flush_commit_mask_0 & io_commit_uops_0_is_amo_0; // @[Mux.scala:30:73]
wire _flush_uop_T_121 = flush_commit_mask_1 & io_commit_uops_1_is_amo_0; // @[Mux.scala:30:73]
wire _flush_uop_T_122 = flush_commit_mask_2 & io_commit_uops_2_is_amo_0; // @[Mux.scala:30:73]
wire _flush_uop_T_123 = _flush_uop_T_120 | _flush_uop_T_121; // @[Mux.scala:30:73]
wire _flush_uop_T_124 = _flush_uop_T_123 | _flush_uop_T_122; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_25 = _flush_uop_T_124; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_amo = _flush_uop_WIRE_25; // @[Mux.scala:30:73]
wire _flush_uop_T_125 = flush_commit_mask_0 & io_commit_uops_0_is_fencei_0; // @[Mux.scala:30:73]
wire _flush_uop_T_126 = flush_commit_mask_1 & io_commit_uops_1_is_fencei_0; // @[Mux.scala:30:73]
wire _flush_uop_T_127 = flush_commit_mask_2 & io_commit_uops_2_is_fencei_0; // @[Mux.scala:30:73]
wire _flush_uop_T_128 = _flush_uop_T_125 | _flush_uop_T_126; // @[Mux.scala:30:73]
wire _flush_uop_T_129 = _flush_uop_T_128 | _flush_uop_T_127; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_26 = _flush_uop_T_129; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_fencei = _flush_uop_WIRE_26; // @[Mux.scala:30:73]
wire _flush_uop_T_130 = flush_commit_mask_0 & io_commit_uops_0_is_fence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_131 = flush_commit_mask_1 & io_commit_uops_1_is_fence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_132 = flush_commit_mask_2 & io_commit_uops_2_is_fence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_133 = _flush_uop_T_130 | _flush_uop_T_131; // @[Mux.scala:30:73]
wire _flush_uop_T_134 = _flush_uop_T_133 | _flush_uop_T_132; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_27 = _flush_uop_T_134; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_fence = _flush_uop_WIRE_27; // @[Mux.scala:30:73]
wire _flush_uop_T_135 = flush_commit_mask_0 & io_commit_uops_0_mem_signed_0; // @[Mux.scala:30:73]
wire _flush_uop_T_136 = flush_commit_mask_1 & io_commit_uops_1_mem_signed_0; // @[Mux.scala:30:73]
wire _flush_uop_T_137 = flush_commit_mask_2 & io_commit_uops_2_mem_signed_0; // @[Mux.scala:30:73]
wire _flush_uop_T_138 = _flush_uop_T_135 | _flush_uop_T_136; // @[Mux.scala:30:73]
wire _flush_uop_T_139 = _flush_uop_T_138 | _flush_uop_T_137; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_28 = _flush_uop_T_139; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_mem_signed = _flush_uop_WIRE_28; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_140 = flush_commit_mask_0 ? io_commit_uops_0_mem_size_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_141 = flush_commit_mask_1 ? io_commit_uops_1_mem_size_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_142 = flush_commit_mask_2 ? io_commit_uops_2_mem_size_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_143 = _flush_uop_T_140 | _flush_uop_T_141; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_144 = _flush_uop_T_143 | _flush_uop_T_142; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_29 = _flush_uop_T_144; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_mem_size = _flush_uop_WIRE_29; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_145 = flush_commit_mask_0 ? io_commit_uops_0_mem_cmd_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_146 = flush_commit_mask_1 ? io_commit_uops_1_mem_cmd_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_147 = flush_commit_mask_2 ? io_commit_uops_2_mem_cmd_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_148 = _flush_uop_T_145 | _flush_uop_T_146; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_149 = _flush_uop_T_148 | _flush_uop_T_147; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_30 = _flush_uop_T_149; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_mem_cmd = _flush_uop_WIRE_30; // @[Mux.scala:30:73]
wire _flush_uop_T_150 = flush_commit_mask_0 & io_commit_uops_0_bypassable_0; // @[Mux.scala:30:73]
wire _flush_uop_T_151 = flush_commit_mask_1 & io_commit_uops_1_bypassable_0; // @[Mux.scala:30:73]
wire _flush_uop_T_152 = flush_commit_mask_2 & io_commit_uops_2_bypassable_0; // @[Mux.scala:30:73]
wire _flush_uop_T_153 = _flush_uop_T_150 | _flush_uop_T_151; // @[Mux.scala:30:73]
wire _flush_uop_T_154 = _flush_uop_T_153 | _flush_uop_T_152; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_31 = _flush_uop_T_154; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_bypassable = _flush_uop_WIRE_31; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_155 = flush_commit_mask_0 ? io_commit_uops_0_exc_cause_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_156 = flush_commit_mask_1 ? io_commit_uops_1_exc_cause_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_157 = flush_commit_mask_2 ? io_commit_uops_2_exc_cause_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_158 = _flush_uop_T_155 | _flush_uop_T_156; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_159 = _flush_uop_T_158 | _flush_uop_T_157; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_32 = _flush_uop_T_159; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_WIRE_exc_cause = _flush_uop_WIRE_32; // @[Mux.scala:30:73]
wire _flush_uop_T_160 = flush_commit_mask_0 & io_commit_uops_0_exception_0; // @[Mux.scala:30:73]
wire _flush_uop_T_161 = flush_commit_mask_1 & io_commit_uops_1_exception_0; // @[Mux.scala:30:73]
wire _flush_uop_T_162 = flush_commit_mask_2 & io_commit_uops_2_exception_0; // @[Mux.scala:30:73]
wire _flush_uop_T_163 = _flush_uop_T_160 | _flush_uop_T_161; // @[Mux.scala:30:73]
wire _flush_uop_T_164 = _flush_uop_T_163 | _flush_uop_T_162; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_33 = _flush_uop_T_164; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_exception = _flush_uop_WIRE_33; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_165 = flush_commit_mask_0 ? io_commit_uops_0_stale_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_166 = flush_commit_mask_1 ? io_commit_uops_1_stale_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_167 = flush_commit_mask_2 ? io_commit_uops_2_stale_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_168 = _flush_uop_T_165 | _flush_uop_T_166; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_169 = _flush_uop_T_168 | _flush_uop_T_167; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_34 = _flush_uop_T_169; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_stale_pdst = _flush_uop_WIRE_34; // @[Mux.scala:30:73]
wire _flush_uop_T_170 = flush_commit_mask_0 & io_commit_uops_0_ppred_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_171 = flush_commit_mask_1 & io_commit_uops_1_ppred_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_172 = flush_commit_mask_2 & io_commit_uops_2_ppred_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_173 = _flush_uop_T_170 | _flush_uop_T_171; // @[Mux.scala:30:73]
wire _flush_uop_T_174 = _flush_uop_T_173 | _flush_uop_T_172; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_35 = _flush_uop_T_174; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ppred_busy = _flush_uop_WIRE_35; // @[Mux.scala:30:73]
wire _flush_uop_T_175 = flush_commit_mask_0 & io_commit_uops_0_prs3_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_176 = flush_commit_mask_1 & io_commit_uops_1_prs3_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_177 = flush_commit_mask_2 & io_commit_uops_2_prs3_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_178 = _flush_uop_T_175 | _flush_uop_T_176; // @[Mux.scala:30:73]
wire _flush_uop_T_179 = _flush_uop_T_178 | _flush_uop_T_177; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_36 = _flush_uop_T_179; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs3_busy = _flush_uop_WIRE_36; // @[Mux.scala:30:73]
wire _flush_uop_T_180 = flush_commit_mask_0 & io_commit_uops_0_prs2_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_181 = flush_commit_mask_1 & io_commit_uops_1_prs2_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_182 = flush_commit_mask_2 & io_commit_uops_2_prs2_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_183 = _flush_uop_T_180 | _flush_uop_T_181; // @[Mux.scala:30:73]
wire _flush_uop_T_184 = _flush_uop_T_183 | _flush_uop_T_182; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_37 = _flush_uop_T_184; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs2_busy = _flush_uop_WIRE_37; // @[Mux.scala:30:73]
wire _flush_uop_T_185 = flush_commit_mask_0 & io_commit_uops_0_prs1_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_186 = flush_commit_mask_1 & io_commit_uops_1_prs1_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_187 = flush_commit_mask_2 & io_commit_uops_2_prs1_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_188 = _flush_uop_T_185 | _flush_uop_T_186; // @[Mux.scala:30:73]
wire _flush_uop_T_189 = _flush_uop_T_188 | _flush_uop_T_187; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_38 = _flush_uop_T_189; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs1_busy = _flush_uop_WIRE_38; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_190 = flush_commit_mask_0 ? io_commit_uops_0_ppred_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_191 = flush_commit_mask_1 ? io_commit_uops_1_ppred_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_192 = flush_commit_mask_2 ? io_commit_uops_2_ppred_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_193 = _flush_uop_T_190 | _flush_uop_T_191; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_194 = _flush_uop_T_193 | _flush_uop_T_192; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_39 = _flush_uop_T_194; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ppred = _flush_uop_WIRE_39; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_195 = flush_commit_mask_0 ? io_commit_uops_0_prs3_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_196 = flush_commit_mask_1 ? io_commit_uops_1_prs3_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_197 = flush_commit_mask_2 ? io_commit_uops_2_prs3_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_198 = _flush_uop_T_195 | _flush_uop_T_196; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_199 = _flush_uop_T_198 | _flush_uop_T_197; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_40 = _flush_uop_T_199; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs3 = _flush_uop_WIRE_40; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_200 = flush_commit_mask_0 ? io_commit_uops_0_prs2_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_201 = flush_commit_mask_1 ? io_commit_uops_1_prs2_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_202 = flush_commit_mask_2 ? io_commit_uops_2_prs2_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_203 = _flush_uop_T_200 | _flush_uop_T_201; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_204 = _flush_uop_T_203 | _flush_uop_T_202; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_41 = _flush_uop_T_204; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs2 = _flush_uop_WIRE_41; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_205 = flush_commit_mask_0 ? io_commit_uops_0_prs1_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_206 = flush_commit_mask_1 ? io_commit_uops_1_prs1_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_207 = flush_commit_mask_2 ? io_commit_uops_2_prs1_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_208 = _flush_uop_T_205 | _flush_uop_T_206; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_209 = _flush_uop_T_208 | _flush_uop_T_207; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_42 = _flush_uop_T_209; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs1 = _flush_uop_WIRE_42; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_210 = flush_commit_mask_0 ? io_commit_uops_0_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_211 = flush_commit_mask_1 ? io_commit_uops_1_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_212 = flush_commit_mask_2 ? io_commit_uops_2_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_213 = _flush_uop_T_210 | _flush_uop_T_211; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_214 = _flush_uop_T_213 | _flush_uop_T_212; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_43 = _flush_uop_T_214; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_pdst = _flush_uop_WIRE_43; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_215 = flush_commit_mask_0 ? io_commit_uops_0_rxq_idx_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_216 = flush_commit_mask_1 ? io_commit_uops_1_rxq_idx_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_217 = flush_commit_mask_2 ? io_commit_uops_2_rxq_idx_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_218 = _flush_uop_T_215 | _flush_uop_T_216; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_219 = _flush_uop_T_218 | _flush_uop_T_217; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_44 = _flush_uop_T_219; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_rxq_idx = _flush_uop_WIRE_44; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_220 = flush_commit_mask_0 ? io_commit_uops_0_stq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_221 = flush_commit_mask_1 ? io_commit_uops_1_stq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_222 = flush_commit_mask_2 ? io_commit_uops_2_stq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_223 = _flush_uop_T_220 | _flush_uop_T_221; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_224 = _flush_uop_T_223 | _flush_uop_T_222; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_45 = _flush_uop_T_224; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_stq_idx = _flush_uop_WIRE_45; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_225 = flush_commit_mask_0 ? io_commit_uops_0_ldq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_226 = flush_commit_mask_1 ? io_commit_uops_1_ldq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_227 = flush_commit_mask_2 ? io_commit_uops_2_ldq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_228 = _flush_uop_T_225 | _flush_uop_T_226; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_229 = _flush_uop_T_228 | _flush_uop_T_227; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46 = _flush_uop_T_229; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ldq_idx = _flush_uop_WIRE_46; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_230 = flush_commit_mask_0 ? io_commit_uops_0_rob_idx_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_231 = flush_commit_mask_1 ? io_commit_uops_1_rob_idx_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_232 = flush_commit_mask_2 ? io_commit_uops_2_rob_idx_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_233 = _flush_uop_T_230 | _flush_uop_T_231; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_234 = _flush_uop_T_233 | _flush_uop_T_232; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_47 = _flush_uop_T_234; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_rob_idx = _flush_uop_WIRE_47; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_235 = flush_commit_mask_0 ? io_commit_uops_0_csr_addr_0 : 12'h0; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_236 = flush_commit_mask_1 ? io_commit_uops_1_csr_addr_0 : 12'h0; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_237 = flush_commit_mask_2 ? io_commit_uops_2_csr_addr_0 : 12'h0; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_238 = _flush_uop_T_235 | _flush_uop_T_236; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_239 = _flush_uop_T_238 | _flush_uop_T_237; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_48 = _flush_uop_T_239; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_WIRE_csr_addr = _flush_uop_WIRE_48; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_240 = flush_commit_mask_0 ? io_commit_uops_0_imm_packed_0 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_241 = flush_commit_mask_1 ? io_commit_uops_1_imm_packed_0 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_242 = flush_commit_mask_2 ? io_commit_uops_2_imm_packed_0 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_243 = _flush_uop_T_240 | _flush_uop_T_241; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_244 = _flush_uop_T_243 | _flush_uop_T_242; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_49 = _flush_uop_T_244; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_WIRE_imm_packed = _flush_uop_WIRE_49; // @[Mux.scala:30:73]
wire _flush_uop_T_245 = flush_commit_mask_0 & io_commit_uops_0_taken_0; // @[Mux.scala:30:73]
wire _flush_uop_T_246 = flush_commit_mask_1 & io_commit_uops_1_taken_0; // @[Mux.scala:30:73]
wire _flush_uop_T_247 = flush_commit_mask_2 & io_commit_uops_2_taken_0; // @[Mux.scala:30:73]
wire _flush_uop_T_248 = _flush_uop_T_245 | _flush_uop_T_246; // @[Mux.scala:30:73]
wire _flush_uop_T_249 = _flush_uop_T_248 | _flush_uop_T_247; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_50 = _flush_uop_T_249; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_taken = _flush_uop_WIRE_50; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_250 = flush_commit_mask_0 ? io_commit_uops_0_pc_lob_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_251 = flush_commit_mask_1 ? io_commit_uops_1_pc_lob_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_252 = flush_commit_mask_2 ? io_commit_uops_2_pc_lob_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_253 = _flush_uop_T_250 | _flush_uop_T_251; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_254 = _flush_uop_T_253 | _flush_uop_T_252; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_51 = _flush_uop_T_254; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_pc_lob = _flush_uop_WIRE_51; // @[Mux.scala:30:73]
wire _flush_uop_T_255 = flush_commit_mask_0 & io_commit_uops_0_edge_inst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_256 = flush_commit_mask_1 & io_commit_uops_1_edge_inst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_257 = flush_commit_mask_2 & io_commit_uops_2_edge_inst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_258 = _flush_uop_T_255 | _flush_uop_T_256; // @[Mux.scala:30:73]
wire _flush_uop_T_259 = _flush_uop_T_258 | _flush_uop_T_257; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_52 = _flush_uop_T_259; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_edge_inst = _flush_uop_WIRE_52; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_260 = flush_commit_mask_0 ? io_commit_uops_0_ftq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_261 = flush_commit_mask_1 ? io_commit_uops_1_ftq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_262 = flush_commit_mask_2 ? io_commit_uops_2_ftq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_263 = _flush_uop_T_260 | _flush_uop_T_261; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_264 = _flush_uop_T_263 | _flush_uop_T_262; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_53 = _flush_uop_T_264; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ftq_idx = _flush_uop_WIRE_53; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_265 = flush_commit_mask_0 ? io_commit_uops_0_br_tag_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_266 = flush_commit_mask_1 ? io_commit_uops_1_br_tag_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_267 = flush_commit_mask_2 ? io_commit_uops_2_br_tag_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_268 = _flush_uop_T_265 | _flush_uop_T_266; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_269 = _flush_uop_T_268 | _flush_uop_T_267; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_54 = _flush_uop_T_269; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_br_tag = _flush_uop_WIRE_54; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_T_270 = flush_commit_mask_0 ? io_commit_uops_0_br_mask_0 : 16'h0; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_T_271 = flush_commit_mask_1 ? io_commit_uops_1_br_mask_0 : 16'h0; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_T_272 = flush_commit_mask_2 ? io_commit_uops_2_br_mask_0 : 16'h0; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_T_273 = _flush_uop_T_270 | _flush_uop_T_271; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_T_274 = _flush_uop_T_273 | _flush_uop_T_272; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_55 = _flush_uop_T_274; // @[Mux.scala:30:73]
wire [15:0] _flush_uop_WIRE_br_mask = _flush_uop_WIRE_55; // @[Mux.scala:30:73]
wire _flush_uop_T_275 = flush_commit_mask_0 & io_commit_uops_0_is_sfb_0; // @[Mux.scala:30:73]
wire _flush_uop_T_276 = flush_commit_mask_1 & io_commit_uops_1_is_sfb_0; // @[Mux.scala:30:73]
wire _flush_uop_T_277 = flush_commit_mask_2 & io_commit_uops_2_is_sfb_0; // @[Mux.scala:30:73]
wire _flush_uop_T_278 = _flush_uop_T_275 | _flush_uop_T_276; // @[Mux.scala:30:73]
wire _flush_uop_T_279 = _flush_uop_T_278 | _flush_uop_T_277; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_56 = _flush_uop_T_279; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_sfb = _flush_uop_WIRE_56; // @[Mux.scala:30:73]
wire _flush_uop_T_280 = flush_commit_mask_0 & io_commit_uops_0_is_jal_0; // @[Mux.scala:30:73]
wire _flush_uop_T_281 = flush_commit_mask_1 & io_commit_uops_1_is_jal_0; // @[Mux.scala:30:73]
wire _flush_uop_T_282 = flush_commit_mask_2 & io_commit_uops_2_is_jal_0; // @[Mux.scala:30:73]
wire _flush_uop_T_283 = _flush_uop_T_280 | _flush_uop_T_281; // @[Mux.scala:30:73]
wire _flush_uop_T_284 = _flush_uop_T_283 | _flush_uop_T_282; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_57 = _flush_uop_T_284; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_jal = _flush_uop_WIRE_57; // @[Mux.scala:30:73]
wire _flush_uop_T_285 = flush_commit_mask_0 & io_commit_uops_0_is_jalr_0; // @[Mux.scala:30:73]
wire _flush_uop_T_286 = flush_commit_mask_1 & io_commit_uops_1_is_jalr_0; // @[Mux.scala:30:73]
wire _flush_uop_T_287 = flush_commit_mask_2 & io_commit_uops_2_is_jalr_0; // @[Mux.scala:30:73]
wire _flush_uop_T_288 = _flush_uop_T_285 | _flush_uop_T_286; // @[Mux.scala:30:73]
wire _flush_uop_T_289 = _flush_uop_T_288 | _flush_uop_T_287; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_58 = _flush_uop_T_289; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_jalr = _flush_uop_WIRE_58; // @[Mux.scala:30:73]
wire _flush_uop_T_290 = flush_commit_mask_0 & io_commit_uops_0_is_br_0; // @[Mux.scala:30:73]
wire _flush_uop_T_291 = flush_commit_mask_1 & io_commit_uops_1_is_br_0; // @[Mux.scala:30:73]
wire _flush_uop_T_292 = flush_commit_mask_2 & io_commit_uops_2_is_br_0; // @[Mux.scala:30:73]
wire _flush_uop_T_293 = _flush_uop_T_290 | _flush_uop_T_291; // @[Mux.scala:30:73]
wire _flush_uop_T_294 = _flush_uop_T_293 | _flush_uop_T_292; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_59 = _flush_uop_T_294; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_br = _flush_uop_WIRE_59; // @[Mux.scala:30:73]
wire _flush_uop_T_295 = flush_commit_mask_0 & io_commit_uops_0_iw_p2_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_296 = flush_commit_mask_1 & io_commit_uops_1_iw_p2_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_297 = flush_commit_mask_2 & io_commit_uops_2_iw_p2_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_298 = _flush_uop_T_295 | _flush_uop_T_296; // @[Mux.scala:30:73]
wire _flush_uop_T_299 = _flush_uop_T_298 | _flush_uop_T_297; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_60 = _flush_uop_T_299; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_p2_poisoned = _flush_uop_WIRE_60; // @[Mux.scala:30:73]
wire _flush_uop_T_300 = flush_commit_mask_0 & io_commit_uops_0_iw_p1_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_301 = flush_commit_mask_1 & io_commit_uops_1_iw_p1_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_302 = flush_commit_mask_2 & io_commit_uops_2_iw_p1_poisoned_0; // @[Mux.scala:30:73]
wire _flush_uop_T_303 = _flush_uop_T_300 | _flush_uop_T_301; // @[Mux.scala:30:73]
wire _flush_uop_T_304 = _flush_uop_T_303 | _flush_uop_T_302; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_61 = _flush_uop_T_304; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_p1_poisoned = _flush_uop_WIRE_61; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_305 = flush_commit_mask_0 ? io_commit_uops_0_iw_state_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_306 = flush_commit_mask_1 ? io_commit_uops_1_iw_state_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_307 = flush_commit_mask_2 ? io_commit_uops_2_iw_state_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_308 = _flush_uop_T_305 | _flush_uop_T_306; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_309 = _flush_uop_T_308 | _flush_uop_T_307; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_62 = _flush_uop_T_309; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_iw_state = _flush_uop_WIRE_62; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_73; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_ctrl_br_type = _flush_uop_WIRE_63_br_type; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_72; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_ctrl_op1_sel = _flush_uop_WIRE_63_op1_sel; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_71; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_ctrl_op2_sel = _flush_uop_WIRE_63_op2_sel; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_70; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_ctrl_imm_sel = _flush_uop_WIRE_63_imm_sel; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_69; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ctrl_op_fcn = _flush_uop_WIRE_63_op_fcn; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_68; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ctrl_fcn_dw = _flush_uop_WIRE_63_fcn_dw; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_67; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_ctrl_csr_cmd = _flush_uop_WIRE_63_csr_cmd; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_66; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ctrl_is_load = _flush_uop_WIRE_63_is_load; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_65; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ctrl_is_sta = _flush_uop_WIRE_63_is_sta; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_64; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ctrl_is_std = _flush_uop_WIRE_63_is_std; // @[Mux.scala:30:73]
wire _flush_uop_T_310 = flush_commit_mask_0 & io_commit_uops_0_ctrl_is_std_0; // @[Mux.scala:30:73]
wire _flush_uop_T_311 = flush_commit_mask_1 & io_commit_uops_1_ctrl_is_std_0; // @[Mux.scala:30:73]
wire _flush_uop_T_312 = flush_commit_mask_2 & io_commit_uops_2_ctrl_is_std_0; // @[Mux.scala:30:73]
wire _flush_uop_T_313 = _flush_uop_T_310 | _flush_uop_T_311; // @[Mux.scala:30:73]
wire _flush_uop_T_314 = _flush_uop_T_313 | _flush_uop_T_312; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_64 = _flush_uop_T_314; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_is_std = _flush_uop_WIRE_64; // @[Mux.scala:30:73]
wire _flush_uop_T_315 = flush_commit_mask_0 & io_commit_uops_0_ctrl_is_sta_0; // @[Mux.scala:30:73]
wire _flush_uop_T_316 = flush_commit_mask_1 & io_commit_uops_1_ctrl_is_sta_0; // @[Mux.scala:30:73]
wire _flush_uop_T_317 = flush_commit_mask_2 & io_commit_uops_2_ctrl_is_sta_0; // @[Mux.scala:30:73]
wire _flush_uop_T_318 = _flush_uop_T_315 | _flush_uop_T_316; // @[Mux.scala:30:73]
wire _flush_uop_T_319 = _flush_uop_T_318 | _flush_uop_T_317; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_65 = _flush_uop_T_319; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_is_sta = _flush_uop_WIRE_65; // @[Mux.scala:30:73]
wire _flush_uop_T_320 = flush_commit_mask_0 & io_commit_uops_0_ctrl_is_load_0; // @[Mux.scala:30:73]
wire _flush_uop_T_321 = flush_commit_mask_1 & io_commit_uops_1_ctrl_is_load_0; // @[Mux.scala:30:73]
wire _flush_uop_T_322 = flush_commit_mask_2 & io_commit_uops_2_ctrl_is_load_0; // @[Mux.scala:30:73]
wire _flush_uop_T_323 = _flush_uop_T_320 | _flush_uop_T_321; // @[Mux.scala:30:73]
wire _flush_uop_T_324 = _flush_uop_T_323 | _flush_uop_T_322; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_66 = _flush_uop_T_324; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_is_load = _flush_uop_WIRE_66; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_325 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_csr_cmd_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_326 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_csr_cmd_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_327 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_csr_cmd_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_328 = _flush_uop_T_325 | _flush_uop_T_326; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_329 = _flush_uop_T_328 | _flush_uop_T_327; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_67 = _flush_uop_T_329; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_csr_cmd = _flush_uop_WIRE_67; // @[Mux.scala:30:73]
wire _flush_uop_T_330 = flush_commit_mask_0 & io_commit_uops_0_ctrl_fcn_dw_0; // @[Mux.scala:30:73]
wire _flush_uop_T_331 = flush_commit_mask_1 & io_commit_uops_1_ctrl_fcn_dw_0; // @[Mux.scala:30:73]
wire _flush_uop_T_332 = flush_commit_mask_2 & io_commit_uops_2_ctrl_fcn_dw_0; // @[Mux.scala:30:73]
wire _flush_uop_T_333 = _flush_uop_T_330 | _flush_uop_T_331; // @[Mux.scala:30:73]
wire _flush_uop_T_334 = _flush_uop_T_333 | _flush_uop_T_332; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_68 = _flush_uop_T_334; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_fcn_dw = _flush_uop_WIRE_68; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_335 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_op_fcn_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_336 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_op_fcn_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_337 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_op_fcn_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_338 = _flush_uop_T_335 | _flush_uop_T_336; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_339 = _flush_uop_T_338 | _flush_uop_T_337; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_69 = _flush_uop_T_339; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_op_fcn = _flush_uop_WIRE_69; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_340 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_imm_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_341 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_imm_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_342 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_imm_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_343 = _flush_uop_T_340 | _flush_uop_T_341; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_344 = _flush_uop_T_343 | _flush_uop_T_342; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_70 = _flush_uop_T_344; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_imm_sel = _flush_uop_WIRE_70; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_345 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_op2_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_346 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_op2_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_347 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_op2_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_348 = _flush_uop_T_345 | _flush_uop_T_346; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_349 = _flush_uop_T_348 | _flush_uop_T_347; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_71 = _flush_uop_T_349; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_op2_sel = _flush_uop_WIRE_71; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_350 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_op1_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_351 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_op1_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_352 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_op1_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_353 = _flush_uop_T_350 | _flush_uop_T_351; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_354 = _flush_uop_T_353 | _flush_uop_T_352; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_72 = _flush_uop_T_354; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_op1_sel = _flush_uop_WIRE_72; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_355 = flush_commit_mask_0 ? io_commit_uops_0_ctrl_br_type_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_356 = flush_commit_mask_1 ? io_commit_uops_1_ctrl_br_type_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_357 = flush_commit_mask_2 ? io_commit_uops_2_ctrl_br_type_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_358 = _flush_uop_T_355 | _flush_uop_T_356; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_359 = _flush_uop_T_358 | _flush_uop_T_357; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_73 = _flush_uop_T_359; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63_br_type = _flush_uop_WIRE_73; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_T_360 = flush_commit_mask_0 ? io_commit_uops_0_fu_code_0 : 10'h0; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_T_361 = flush_commit_mask_1 ? io_commit_uops_1_fu_code_0 : 10'h0; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_T_362 = flush_commit_mask_2 ? io_commit_uops_2_fu_code_0 : 10'h0; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_T_363 = _flush_uop_T_360 | _flush_uop_T_361; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_T_364 = _flush_uop_T_363 | _flush_uop_T_362; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_74 = _flush_uop_T_364; // @[Mux.scala:30:73]
wire [9:0] _flush_uop_WIRE_fu_code = _flush_uop_WIRE_74; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_365 = flush_commit_mask_0 ? io_commit_uops_0_iq_type_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_366 = flush_commit_mask_1 ? io_commit_uops_1_iq_type_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_367 = flush_commit_mask_2 ? io_commit_uops_2_iq_type_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_368 = _flush_uop_T_365 | _flush_uop_T_366; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_369 = _flush_uop_T_368 | _flush_uop_T_367; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_75 = _flush_uop_T_369; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_iq_type = _flush_uop_WIRE_75; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_370 = flush_commit_mask_0 ? io_commit_uops_0_debug_pc_0 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_371 = flush_commit_mask_1 ? io_commit_uops_1_debug_pc_0 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_372 = flush_commit_mask_2 ? io_commit_uops_2_debug_pc_0 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_373 = _flush_uop_T_370 | _flush_uop_T_371; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_374 = _flush_uop_T_373 | _flush_uop_T_372; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_76 = _flush_uop_T_374; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_WIRE_debug_pc = _flush_uop_WIRE_76; // @[Mux.scala:30:73]
wire _flush_uop_T_375 = flush_commit_mask_0 & io_commit_uops_0_is_rvc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_376 = flush_commit_mask_1 & io_commit_uops_1_is_rvc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_377 = flush_commit_mask_2 & io_commit_uops_2_is_rvc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_378 = _flush_uop_T_375 | _flush_uop_T_376; // @[Mux.scala:30:73]
wire _flush_uop_T_379 = _flush_uop_T_378 | _flush_uop_T_377; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_77 = _flush_uop_T_379; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_rvc = _flush_uop_WIRE_77; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_380 = flush_commit_mask_0 ? io_commit_uops_0_debug_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_381 = flush_commit_mask_1 ? io_commit_uops_1_debug_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_382 = flush_commit_mask_2 ? io_commit_uops_2_debug_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_383 = _flush_uop_T_380 | _flush_uop_T_381; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_384 = _flush_uop_T_383 | _flush_uop_T_382; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_78 = _flush_uop_T_384; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_debug_inst = _flush_uop_WIRE_78; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_385 = flush_commit_mask_0 ? io_commit_uops_0_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_386 = flush_commit_mask_1 ? io_commit_uops_1_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_387 = flush_commit_mask_2 ? io_commit_uops_2_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_388 = _flush_uop_T_385 | _flush_uop_T_386; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_389 = _flush_uop_T_388 | _flush_uop_T_387; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_79 = _flush_uop_T_389; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_inst = _flush_uop_WIRE_79; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_390 = flush_commit_mask_0 ? io_commit_uops_0_uopc_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_391 = flush_commit_mask_1 ? io_commit_uops_1_uopc_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_392 = flush_commit_mask_2 ? io_commit_uops_2_uopc_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_393 = _flush_uop_T_390 | _flush_uop_T_391; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_394 = _flush_uop_T_393 | _flush_uop_T_392; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_80 = _flush_uop_T_394; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_uopc = _flush_uop_WIRE_80; // @[Mux.scala:30:73]
wire [6:0] flush_uop_uopc = exception_thrown ? com_xcpt_uop_uopc : _flush_uop_WIRE_uopc; // @[Mux.scala:30:73, :50:70]
wire [31:0] flush_uop_inst = exception_thrown ? com_xcpt_uop_inst : _flush_uop_WIRE_inst; // @[Mux.scala:30:73, :50:70]
wire [31:0] flush_uop_debug_inst = exception_thrown ? com_xcpt_uop_debug_inst : _flush_uop_WIRE_debug_inst; // @[Mux.scala:30:73, :50:70]
assign flush_uop_is_rvc = exception_thrown ? com_xcpt_uop_is_rvc : _flush_uop_WIRE_is_rvc; // @[Mux.scala:30:73, :50:70]
wire [39:0] flush_uop_debug_pc = exception_thrown ? com_xcpt_uop_debug_pc : _flush_uop_WIRE_debug_pc; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_iq_type = exception_thrown ? com_xcpt_uop_iq_type : _flush_uop_WIRE_iq_type; // @[Mux.scala:30:73, :50:70]
wire [9:0] flush_uop_fu_code = exception_thrown ? com_xcpt_uop_fu_code : _flush_uop_WIRE_fu_code; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_ctrl_br_type = exception_thrown ? com_xcpt_uop_ctrl_br_type : _flush_uop_WIRE_ctrl_br_type; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_ctrl_op1_sel = exception_thrown ? com_xcpt_uop_ctrl_op1_sel : _flush_uop_WIRE_ctrl_op1_sel; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_ctrl_op2_sel = exception_thrown ? com_xcpt_uop_ctrl_op2_sel : _flush_uop_WIRE_ctrl_op2_sel; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_ctrl_imm_sel = exception_thrown ? com_xcpt_uop_ctrl_imm_sel : _flush_uop_WIRE_ctrl_imm_sel; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_ctrl_op_fcn = exception_thrown ? com_xcpt_uop_ctrl_op_fcn : _flush_uop_WIRE_ctrl_op_fcn; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ctrl_fcn_dw = exception_thrown ? com_xcpt_uop_ctrl_fcn_dw : _flush_uop_WIRE_ctrl_fcn_dw; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_ctrl_csr_cmd = exception_thrown ? com_xcpt_uop_ctrl_csr_cmd : _flush_uop_WIRE_ctrl_csr_cmd; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ctrl_is_load = exception_thrown ? com_xcpt_uop_ctrl_is_load : _flush_uop_WIRE_ctrl_is_load; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ctrl_is_sta = exception_thrown ? com_xcpt_uop_ctrl_is_sta : _flush_uop_WIRE_ctrl_is_sta; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ctrl_is_std = exception_thrown ? com_xcpt_uop_ctrl_is_std : _flush_uop_WIRE_ctrl_is_std; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_iw_state = exception_thrown ? com_xcpt_uop_iw_state : _flush_uop_WIRE_iw_state; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_p1_poisoned = exception_thrown ? com_xcpt_uop_iw_p1_poisoned : _flush_uop_WIRE_iw_p1_poisoned; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_p2_poisoned = exception_thrown ? com_xcpt_uop_iw_p2_poisoned : _flush_uop_WIRE_iw_p2_poisoned; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_br = exception_thrown ? com_xcpt_uop_is_br : _flush_uop_WIRE_is_br; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_jalr = exception_thrown ? com_xcpt_uop_is_jalr : _flush_uop_WIRE_is_jalr; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_jal = exception_thrown ? com_xcpt_uop_is_jal : _flush_uop_WIRE_is_jal; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_sfb = exception_thrown ? com_xcpt_uop_is_sfb : _flush_uop_WIRE_is_sfb; // @[Mux.scala:30:73, :50:70]
wire [15:0] flush_uop_br_mask = exception_thrown ? com_xcpt_uop_br_mask : _flush_uop_WIRE_br_mask; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_br_tag = exception_thrown ? com_xcpt_uop_br_tag : _flush_uop_WIRE_br_tag; // @[Mux.scala:30:73, :50:70]
assign flush_uop_ftq_idx = exception_thrown ? com_xcpt_uop_ftq_idx : _flush_uop_WIRE_ftq_idx; // @[Mux.scala:30:73, :50:70]
assign flush_uop_edge_inst = exception_thrown ? com_xcpt_uop_edge_inst : _flush_uop_WIRE_edge_inst; // @[Mux.scala:30:73, :50:70]
assign flush_uop_pc_lob = exception_thrown ? com_xcpt_uop_pc_lob : _flush_uop_WIRE_pc_lob; // @[Mux.scala:30:73, :50:70]
wire flush_uop_taken = exception_thrown ? com_xcpt_uop_taken : _flush_uop_WIRE_taken; // @[Mux.scala:30:73, :50:70]
wire [19:0] flush_uop_imm_packed = exception_thrown ? com_xcpt_uop_imm_packed : _flush_uop_WIRE_imm_packed; // @[Mux.scala:30:73, :50:70]
wire [11:0] flush_uop_csr_addr = exception_thrown ? com_xcpt_uop_csr_addr : _flush_uop_WIRE_csr_addr; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_rob_idx = exception_thrown ? com_xcpt_uop_rob_idx : _flush_uop_WIRE_rob_idx; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_ldq_idx = exception_thrown ? com_xcpt_uop_ldq_idx : _flush_uop_WIRE_ldq_idx; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_stq_idx = exception_thrown ? com_xcpt_uop_stq_idx : _flush_uop_WIRE_stq_idx; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_rxq_idx = exception_thrown ? com_xcpt_uop_rxq_idx : _flush_uop_WIRE_rxq_idx; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_pdst = exception_thrown ? com_xcpt_uop_pdst : _flush_uop_WIRE_pdst; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs1 = exception_thrown ? com_xcpt_uop_prs1 : _flush_uop_WIRE_prs1; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs2 = exception_thrown ? com_xcpt_uop_prs2 : _flush_uop_WIRE_prs2; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs3 = exception_thrown ? com_xcpt_uop_prs3 : _flush_uop_WIRE_prs3; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_ppred = exception_thrown ? com_xcpt_uop_ppred : _flush_uop_WIRE_ppred; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs1_busy = exception_thrown ? com_xcpt_uop_prs1_busy : _flush_uop_WIRE_prs1_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs2_busy = exception_thrown ? com_xcpt_uop_prs2_busy : _flush_uop_WIRE_prs2_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs3_busy = exception_thrown ? com_xcpt_uop_prs3_busy : _flush_uop_WIRE_prs3_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ppred_busy = exception_thrown ? com_xcpt_uop_ppred_busy : _flush_uop_WIRE_ppred_busy; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_stale_pdst = exception_thrown ? com_xcpt_uop_stale_pdst : _flush_uop_WIRE_stale_pdst; // @[Mux.scala:30:73, :50:70]
wire flush_uop_exception = exception_thrown ? com_xcpt_uop_exception : _flush_uop_WIRE_exception; // @[Mux.scala:30:73, :50:70]
wire [63:0] flush_uop_exc_cause = exception_thrown ? com_xcpt_uop_exc_cause : _flush_uop_WIRE_exc_cause; // @[Mux.scala:30:73, :50:70]
wire flush_uop_bypassable = exception_thrown ? com_xcpt_uop_bypassable : _flush_uop_WIRE_bypassable; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_mem_cmd = exception_thrown ? com_xcpt_uop_mem_cmd : _flush_uop_WIRE_mem_cmd; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_mem_size = exception_thrown ? com_xcpt_uop_mem_size : _flush_uop_WIRE_mem_size; // @[Mux.scala:30:73, :50:70]
wire flush_uop_mem_signed = exception_thrown ? com_xcpt_uop_mem_signed : _flush_uop_WIRE_mem_signed; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_fence = exception_thrown ? com_xcpt_uop_is_fence : _flush_uop_WIRE_is_fence; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_fencei = exception_thrown ? com_xcpt_uop_is_fencei : _flush_uop_WIRE_is_fencei; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_amo = exception_thrown ? com_xcpt_uop_is_amo : _flush_uop_WIRE_is_amo; // @[Mux.scala:30:73, :50:70]
wire flush_uop_uses_ldq = exception_thrown ? com_xcpt_uop_uses_ldq : _flush_uop_WIRE_uses_ldq; // @[Mux.scala:30:73, :50:70]
wire flush_uop_uses_stq = exception_thrown ? com_xcpt_uop_uses_stq : _flush_uop_WIRE_uses_stq; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_sys_pc2epc = exception_thrown ? com_xcpt_uop_is_sys_pc2epc : _flush_uop_WIRE_is_sys_pc2epc; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_unique = exception_thrown ? com_xcpt_uop_is_unique : _flush_uop_WIRE_is_unique; // @[Mux.scala:30:73, :50:70]
wire flush_uop_flush_on_commit = exception_thrown ? com_xcpt_uop_flush_on_commit : _flush_uop_WIRE_flush_on_commit; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ldst_is_rs1 = exception_thrown ? com_xcpt_uop_ldst_is_rs1 : _flush_uop_WIRE_ldst_is_rs1; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_ldst = exception_thrown ? com_xcpt_uop_ldst : _flush_uop_WIRE_ldst; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs1 = exception_thrown ? com_xcpt_uop_lrs1 : _flush_uop_WIRE_lrs1; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs2 = exception_thrown ? com_xcpt_uop_lrs2 : _flush_uop_WIRE_lrs2; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs3 = exception_thrown ? com_xcpt_uop_lrs3 : _flush_uop_WIRE_lrs3; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ldst_val = exception_thrown ? com_xcpt_uop_ldst_val : _flush_uop_WIRE_ldst_val; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_dst_rtype = exception_thrown ? com_xcpt_uop_dst_rtype : _flush_uop_WIRE_dst_rtype; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_lrs1_rtype = exception_thrown ? com_xcpt_uop_lrs1_rtype : _flush_uop_WIRE_lrs1_rtype; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_lrs2_rtype = exception_thrown ? com_xcpt_uop_lrs2_rtype : _flush_uop_WIRE_lrs2_rtype; // @[Mux.scala:30:73, :50:70]
wire flush_uop_frs3_en = exception_thrown ? com_xcpt_uop_frs3_en : _flush_uop_WIRE_frs3_en; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_val = exception_thrown ? com_xcpt_uop_fp_val : _flush_uop_WIRE_fp_val; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_single = exception_thrown ? com_xcpt_uop_fp_single : _flush_uop_WIRE_fp_single; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_pf_if = exception_thrown ? com_xcpt_uop_xcpt_pf_if : _flush_uop_WIRE_xcpt_pf_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_ae_if = exception_thrown ? com_xcpt_uop_xcpt_ae_if : _flush_uop_WIRE_xcpt_ae_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_ma_if = exception_thrown ? com_xcpt_uop_xcpt_ma_if : _flush_uop_WIRE_xcpt_ma_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_bp_debug_if = exception_thrown ? com_xcpt_uop_bp_debug_if : _flush_uop_WIRE_bp_debug_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_bp_xcpt_if = exception_thrown ? com_xcpt_uop_bp_xcpt_if : _flush_uop_WIRE_bp_xcpt_if; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_debug_fsrc = exception_thrown ? com_xcpt_uop_debug_fsrc : _flush_uop_WIRE_debug_fsrc; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_debug_tsrc = exception_thrown ? com_xcpt_uop_debug_tsrc : _flush_uop_WIRE_debug_tsrc; // @[Mux.scala:30:73, :50:70]
assign io_flush_bits_is_rvc_0 = flush_uop_is_rvc; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_ftq_idx_0 = flush_uop_ftq_idx; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_edge_inst_0 = flush_uop_edge_inst; // @[rob.scala:211:7, :583:22]
assign io_flush_bits_pc_lob_0 = flush_uop_pc_lob; // @[rob.scala:211:7, :583:22]
wire _io_flush_bits_flush_typ_T = ~is_mini_exception; // @[package.scala:81:59]
wire _io_flush_bits_flush_typ_T_1 = exception_thrown & _io_flush_bits_flush_typ_T; // @[rob.scala:253:30, :593:{66,69}]
wire _io_flush_bits_flush_typ_T_2 = flush_uop_uopc == 7'h6A; // @[rob.scala:583:22, :594:80]
wire _io_flush_bits_flush_typ_T_3 = flush_commit & _io_flush_bits_flush_typ_T_2; // @[rob.scala:577:48, :594:{62,80}]
wire _io_flush_bits_flush_typ_ret_T = ~flush_val; // @[rob.scala:172:11, :578:36]
wire [2:0] _io_flush_bits_flush_typ_ret_T_1 = refetch_inst ? 3'h2 : 3'h4; // @[rob.scala:175:10, :569:39]
wire [2:0] _io_flush_bits_flush_typ_ret_T_2 = _io_flush_bits_flush_typ_T_1 ? 3'h1 : _io_flush_bits_flush_typ_ret_T_1; // @[rob.scala:174:10, :175:10, :593:66]
wire [2:0] _io_flush_bits_flush_typ_ret_T_3 = _io_flush_bits_flush_typ_T_3 ? 3'h3 : _io_flush_bits_flush_typ_ret_T_2; // @[rob.scala:173:10, :174:10, :594:62]
assign io_flush_bits_flush_typ_ret = _io_flush_bits_flush_typ_ret_T ? 3'h0 : _io_flush_bits_flush_typ_ret_T_3; // @[rob.scala:172:{10,11}, :173:10]
assign io_flush_bits_flush_typ_0 = io_flush_bits_flush_typ_ret; // @[rob.scala:172:10, :211:7]
wire _fflags_val_0_T_2; // @[rob.scala:608:32]
wire _fflags_val_1_T_2; // @[rob.scala:608:32]
wire _fflags_val_2_T_2; // @[rob.scala:608:32]
wire fflags_val_0; // @[rob.scala:602:24]
wire fflags_val_1; // @[rob.scala:602:24]
wire fflags_val_2; // @[rob.scala:602:24]
wire [4:0] _fflags_0_T; // @[rob.scala:611:21]
wire [4:0] _fflags_1_T; // @[rob.scala:611:21]
wire [4:0] _fflags_2_T; // @[rob.scala:611:21]
wire [4:0] fflags_0; // @[rob.scala:603:24]
wire [4:0] fflags_1; // @[rob.scala:603:24]
wire [4:0] fflags_2; // @[rob.scala:603:24]
wire _fflags_val_0_T = io_commit_valids_0_0 & io_commit_uops_0_fp_val_0; // @[rob.scala:211:7, :607:27]
wire _fflags_val_0_T_1 = ~io_commit_uops_0_uses_stq_0; // @[rob.scala:211:7, :609:7]
assign _fflags_val_0_T_2 = _fflags_val_0_T & _fflags_val_0_T_1; // @[rob.scala:607:27, :608:32, :609:7]
assign fflags_val_0 = _fflags_val_0_T_2; // @[rob.scala:602:24, :608:32]
assign _fflags_0_T = fflags_val_0 ? rob_head_fflags_0 : 5'h0; // @[rob.scala:251:33, :602:24, :611:21]
assign fflags_0 = _fflags_0_T; // @[rob.scala:603:24, :611:21]
wire _fflags_val_1_T = io_commit_valids_1_0 & io_commit_uops_1_fp_val_0; // @[rob.scala:211:7, :607:27]
wire _fflags_val_1_T_1 = ~io_commit_uops_1_uses_stq_0; // @[rob.scala:211:7, :609:7]
assign _fflags_val_1_T_2 = _fflags_val_1_T & _fflags_val_1_T_1; // @[rob.scala:607:27, :608:32, :609:7]
assign fflags_val_1 = _fflags_val_1_T_2; // @[rob.scala:602:24, :608:32]
assign _fflags_1_T = fflags_val_1 ? rob_head_fflags_1 : 5'h0; // @[rob.scala:251:33, :602:24, :611:21]
assign fflags_1 = _fflags_1_T; // @[rob.scala:603:24, :611:21]
wire _fflags_val_2_T = io_commit_valids_2_0 & io_commit_uops_2_fp_val_0; // @[rob.scala:211:7, :607:27]
wire _fflags_val_2_T_1 = ~io_commit_uops_2_uses_stq_0; // @[rob.scala:211:7, :609:7]
assign _fflags_val_2_T_2 = _fflags_val_2_T & _fflags_val_2_T_1; // @[rob.scala:607:27, :608:32, :609:7]
assign fflags_val_2 = _fflags_val_2_T_2; // @[rob.scala:602:24, :608:32]
assign _fflags_2_T = fflags_val_2 ? rob_head_fflags_2 : 5'h0; // @[rob.scala:251:33, :602:24, :611:21]
assign fflags_2 = _fflags_2_T; // @[rob.scala:603:24, :611:21]
wire _io_commit_fflags_valid_T = fflags_val_0 | fflags_val_1; // @[rob.scala:602:24, :623:48]
assign _io_commit_fflags_valid_T_1 = _io_commit_fflags_valid_T | fflags_val_2; // @[rob.scala:602:24, :623:48]
assign io_commit_fflags_valid_0 = _io_commit_fflags_valid_T_1; // @[rob.scala:211:7, :623:48]
wire [4:0] _io_commit_fflags_bits_T = fflags_0 | fflags_1; // @[rob.scala:603:24, :624:44]
assign _io_commit_fflags_bits_T_1 = _io_commit_fflags_bits_T | fflags_2; // @[rob.scala:603:24, :624:44]
assign io_commit_fflags_bits_0 = _io_commit_fflags_bits_T_1; // @[rob.scala:211:7, :624:44]
wire [3:0] next_xcpt_uop_ctrl_br_type; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_ctrl_op1_sel; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_op2_sel; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_imm_sel; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_ctrl_op_fcn; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_load; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_sta; // @[rob.scala:630:27]
wire next_xcpt_uop_ctrl_is_std; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_uopc; // @[rob.scala:630:27]
wire [31:0] next_xcpt_uop_inst; // @[rob.scala:630:27]
wire [31:0] next_xcpt_uop_debug_inst; // @[rob.scala:630:27]
wire next_xcpt_uop_is_rvc; // @[rob.scala:630:27]
wire [39:0] next_xcpt_uop_debug_pc; // @[rob.scala:630:27]
wire [2:0] next_xcpt_uop_iq_type; // @[rob.scala:630:27]
wire [9:0] next_xcpt_uop_fu_code; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_iw_state; // @[rob.scala:630:27]
wire next_xcpt_uop_iw_p1_poisoned; // @[rob.scala:630:27]
wire next_xcpt_uop_iw_p2_poisoned; // @[rob.scala:630:27]
wire next_xcpt_uop_is_br; // @[rob.scala:630:27]
wire next_xcpt_uop_is_jalr; // @[rob.scala:630:27]
wire next_xcpt_uop_is_jal; // @[rob.scala:630:27]
wire next_xcpt_uop_is_sfb; // @[rob.scala:630:27]
wire [15:0] next_xcpt_uop_br_mask; // @[rob.scala:630:27]
wire [3:0] next_xcpt_uop_br_tag; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_ftq_idx; // @[rob.scala:630:27]
wire next_xcpt_uop_edge_inst; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_pc_lob; // @[rob.scala:630:27]
wire next_xcpt_uop_taken; // @[rob.scala:630:27]
wire [19:0] next_xcpt_uop_imm_packed; // @[rob.scala:630:27]
wire [11:0] next_xcpt_uop_csr_addr; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_rob_idx; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_ldq_idx; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_stq_idx; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_rxq_idx; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_pdst; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_prs1; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_prs2; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_prs3; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_ppred; // @[rob.scala:630:27]
wire next_xcpt_uop_prs1_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_prs2_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_prs3_busy; // @[rob.scala:630:27]
wire next_xcpt_uop_ppred_busy; // @[rob.scala:630:27]
wire [6:0] next_xcpt_uop_stale_pdst; // @[rob.scala:630:27]
wire next_xcpt_uop_exception; // @[rob.scala:630:27]
wire [63:0] next_xcpt_uop_exc_cause; // @[rob.scala:630:27]
wire next_xcpt_uop_bypassable; // @[rob.scala:630:27]
wire [4:0] next_xcpt_uop_mem_cmd; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_mem_size; // @[rob.scala:630:27]
wire next_xcpt_uop_mem_signed; // @[rob.scala:630:27]
wire next_xcpt_uop_is_fence; // @[rob.scala:630:27]
wire next_xcpt_uop_is_fencei; // @[rob.scala:630:27]
wire next_xcpt_uop_is_amo; // @[rob.scala:630:27]
wire next_xcpt_uop_uses_ldq; // @[rob.scala:630:27]
wire next_xcpt_uop_uses_stq; // @[rob.scala:630:27]
wire next_xcpt_uop_is_sys_pc2epc; // @[rob.scala:630:27]
wire next_xcpt_uop_is_unique; // @[rob.scala:630:27]
wire next_xcpt_uop_flush_on_commit; // @[rob.scala:630:27]
wire next_xcpt_uop_ldst_is_rs1; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_ldst; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs1; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs2; // @[rob.scala:630:27]
wire [5:0] next_xcpt_uop_lrs3; // @[rob.scala:630:27]
wire next_xcpt_uop_ldst_val; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_dst_rtype; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_lrs1_rtype; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_lrs2_rtype; // @[rob.scala:630:27]
wire next_xcpt_uop_frs3_en; // @[rob.scala:630:27]
wire next_xcpt_uop_fp_val; // @[rob.scala:630:27]
wire next_xcpt_uop_fp_single; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_pf_if; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_ae_if; // @[rob.scala:630:27]
wire next_xcpt_uop_xcpt_ma_if; // @[rob.scala:630:27]
wire next_xcpt_uop_bp_debug_if; // @[rob.scala:630:27]
wire next_xcpt_uop_bp_xcpt_if; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_debug_fsrc; // @[rob.scala:630:27]
wire [1:0] next_xcpt_uop_debug_tsrc; // @[rob.scala:630:27]
wire _enq_xcpts_0_T; // @[rob.scala:634:38]
wire _enq_xcpts_1_T; // @[rob.scala:634:38]
wire _enq_xcpts_2_T; // @[rob.scala:634:38]
wire enq_xcpts_0; // @[rob.scala:632:23]
wire enq_xcpts_1; // @[rob.scala:632:23]
wire enq_xcpts_2; // @[rob.scala:632:23]
assign _enq_xcpts_0_T = io_enq_valids_0_0 & io_enq_uops_0_exception_0; // @[rob.scala:211:7, :634:38]
assign enq_xcpts_0 = _enq_xcpts_0_T; // @[rob.scala:632:23, :634:38]
assign _enq_xcpts_1_T = io_enq_valids_1_0 & io_enq_uops_1_exception_0; // @[rob.scala:211:7, :634:38]
assign enq_xcpts_1 = _enq_xcpts_1_T; // @[rob.scala:632:23, :634:38]
assign _enq_xcpts_2_T = io_enq_valids_2_0 & io_enq_uops_2_exception_0; // @[rob.scala:211:7, :634:38]
assign enq_xcpts_2 = _enq_xcpts_2_T; // @[rob.scala:632:23, :634:38]
wire _T_1341 = ~(io_flush_valid_0 | exception_thrown) & rob_state != 2'h2; // @[rob.scala:211:7, :220:26, :253:30, :637:{9,26,47,60}]
wire _lxcpt_older_T_1 = io_lxcpt_bits_uop_rob_idx_0 < io_csr_replay_bits_uop_rob_idx_0; // @[util.scala:363:52]
wire _lxcpt_older_T_2 = io_lxcpt_bits_uop_rob_idx_0 < rob_head_idx; // @[util.scala:363:64]
wire _lxcpt_older_T_3 = _lxcpt_older_T_1 ^ _lxcpt_older_T_2; // @[util.scala:363:{52,58,64}]
wire _lxcpt_older_T_4 = io_csr_replay_bits_uop_rob_idx_0 < rob_head_idx; // @[util.scala:363:78]
wire _lxcpt_older_T_5 = _lxcpt_older_T_3 ^ _lxcpt_older_T_4; // @[util.scala:363:{58,72,78}]
wire _lxcpt_older_T_6 = _lxcpt_older_T_5 & io_lxcpt_valid_0; // @[util.scala:363:72]
wire _T_1348 = ~r_xcpt_val | new_xcpt_uop_rob_idx < r_xcpt_uop_rob_idx ^ new_xcpt_uop_rob_idx < rob_head_idx ^ r_xcpt_uop_rob_idx < rob_head_idx; // @[util.scala:363:{52,58,64,72,78}]
wire _T_1352 = ~r_xcpt_val & (enq_xcpts_0 | enq_xcpts_1 | enq_xcpts_2); // @[rob.scala:257:33, :632:23, :650:{18,30,51}]
wire [1:0] _idx_T = enq_xcpts_1 ? 2'h1 : 2'h2; // @[rob.scala:632:23, :651:37]
wire [1:0] idx = enq_xcpts_0 ? 2'h0 : _idx_T; // @[rob.scala:632:23, :651:37]
wire [3:0][6:0] _GEN_265 = {{io_enq_uops_0_uopc_0}, {io_enq_uops_2_uopc_0}, {io_enq_uops_1_uopc_0}, {io_enq_uops_0_uopc_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][31:0] _GEN_266 = {{io_enq_uops_0_inst_0}, {io_enq_uops_2_inst_0}, {io_enq_uops_1_inst_0}, {io_enq_uops_0_inst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][31:0] _GEN_267 = {{io_enq_uops_0_debug_inst_0}, {io_enq_uops_2_debug_inst_0}, {io_enq_uops_1_debug_inst_0}, {io_enq_uops_0_debug_inst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_268 = {{io_enq_uops_0_is_rvc_0}, {io_enq_uops_2_is_rvc_0}, {io_enq_uops_1_is_rvc_0}, {io_enq_uops_0_is_rvc_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][39:0] _GEN_269 = {{io_enq_uops_0_debug_pc_0}, {io_enq_uops_2_debug_pc_0}, {io_enq_uops_1_debug_pc_0}, {io_enq_uops_0_debug_pc_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][2:0] _GEN_270 = {{io_enq_uops_0_iq_type_0}, {io_enq_uops_2_iq_type_0}, {io_enq_uops_1_iq_type_0}, {io_enq_uops_0_iq_type_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][9:0] _GEN_271 = {{io_enq_uops_0_fu_code_0}, {io_enq_uops_2_fu_code_0}, {io_enq_uops_1_fu_code_0}, {io_enq_uops_0_fu_code_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][3:0] _GEN_272 = {{io_enq_uops_0_ctrl_br_type_0}, {io_enq_uops_2_ctrl_br_type_0}, {io_enq_uops_1_ctrl_br_type_0}, {io_enq_uops_0_ctrl_br_type_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_273 = {{io_enq_uops_0_ctrl_op1_sel_0}, {io_enq_uops_2_ctrl_op1_sel_0}, {io_enq_uops_1_ctrl_op1_sel_0}, {io_enq_uops_0_ctrl_op1_sel_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][2:0] _GEN_274 = {{io_enq_uops_0_ctrl_op2_sel_0}, {io_enq_uops_2_ctrl_op2_sel_0}, {io_enq_uops_1_ctrl_op2_sel_0}, {io_enq_uops_0_ctrl_op2_sel_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][2:0] _GEN_275 = {{io_enq_uops_0_ctrl_imm_sel_0}, {io_enq_uops_2_ctrl_imm_sel_0}, {io_enq_uops_1_ctrl_imm_sel_0}, {io_enq_uops_0_ctrl_imm_sel_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][4:0] _GEN_276 = {{io_enq_uops_0_ctrl_op_fcn_0}, {io_enq_uops_2_ctrl_op_fcn_0}, {io_enq_uops_1_ctrl_op_fcn_0}, {io_enq_uops_0_ctrl_op_fcn_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_277 = {{io_enq_uops_0_ctrl_fcn_dw_0}, {io_enq_uops_2_ctrl_fcn_dw_0}, {io_enq_uops_1_ctrl_fcn_dw_0}, {io_enq_uops_0_ctrl_fcn_dw_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][2:0] _GEN_278 = {{io_enq_uops_0_ctrl_csr_cmd_0}, {io_enq_uops_2_ctrl_csr_cmd_0}, {io_enq_uops_1_ctrl_csr_cmd_0}, {io_enq_uops_0_ctrl_csr_cmd_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_279 = {{io_enq_uops_0_ctrl_is_load_0}, {io_enq_uops_2_ctrl_is_load_0}, {io_enq_uops_1_ctrl_is_load_0}, {io_enq_uops_0_ctrl_is_load_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_280 = {{io_enq_uops_0_ctrl_is_sta_0}, {io_enq_uops_2_ctrl_is_sta_0}, {io_enq_uops_1_ctrl_is_sta_0}, {io_enq_uops_0_ctrl_is_sta_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_281 = {{io_enq_uops_0_ctrl_is_std_0}, {io_enq_uops_2_ctrl_is_std_0}, {io_enq_uops_1_ctrl_is_std_0}, {io_enq_uops_0_ctrl_is_std_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_282 = {{io_enq_uops_0_iw_state_0}, {io_enq_uops_2_iw_state_0}, {io_enq_uops_1_iw_state_0}, {io_enq_uops_0_iw_state_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_283 = {{io_enq_uops_0_iw_p1_poisoned_0}, {io_enq_uops_2_iw_p1_poisoned_0}, {io_enq_uops_1_iw_p1_poisoned_0}, {io_enq_uops_0_iw_p1_poisoned_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_284 = {{io_enq_uops_0_iw_p2_poisoned_0}, {io_enq_uops_2_iw_p2_poisoned_0}, {io_enq_uops_1_iw_p2_poisoned_0}, {io_enq_uops_0_iw_p2_poisoned_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_285 = {{io_enq_uops_0_is_br_0}, {io_enq_uops_2_is_br_0}, {io_enq_uops_1_is_br_0}, {io_enq_uops_0_is_br_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_286 = {{io_enq_uops_0_is_jalr_0}, {io_enq_uops_2_is_jalr_0}, {io_enq_uops_1_is_jalr_0}, {io_enq_uops_0_is_jalr_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_287 = {{io_enq_uops_0_is_jal_0}, {io_enq_uops_2_is_jal_0}, {io_enq_uops_1_is_jal_0}, {io_enq_uops_0_is_jal_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_288 = {{io_enq_uops_0_is_sfb_0}, {io_enq_uops_2_is_sfb_0}, {io_enq_uops_1_is_sfb_0}, {io_enq_uops_0_is_sfb_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][15:0] _GEN_289 = {{io_enq_uops_0_br_mask_0}, {io_enq_uops_2_br_mask_0}, {io_enq_uops_1_br_mask_0}, {io_enq_uops_0_br_mask_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][3:0] _GEN_290 = {{io_enq_uops_0_br_tag_0}, {io_enq_uops_2_br_tag_0}, {io_enq_uops_1_br_tag_0}, {io_enq_uops_0_br_tag_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][4:0] _GEN_291 = {{io_enq_uops_0_ftq_idx_0}, {io_enq_uops_2_ftq_idx_0}, {io_enq_uops_1_ftq_idx_0}, {io_enq_uops_0_ftq_idx_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_292 = {{io_enq_uops_0_edge_inst_0}, {io_enq_uops_2_edge_inst_0}, {io_enq_uops_1_edge_inst_0}, {io_enq_uops_0_edge_inst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][5:0] _GEN_293 = {{io_enq_uops_0_pc_lob_0}, {io_enq_uops_2_pc_lob_0}, {io_enq_uops_1_pc_lob_0}, {io_enq_uops_0_pc_lob_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_294 = {{io_enq_uops_0_taken_0}, {io_enq_uops_2_taken_0}, {io_enq_uops_1_taken_0}, {io_enq_uops_0_taken_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][19:0] _GEN_295 = {{io_enq_uops_0_imm_packed_0}, {io_enq_uops_2_imm_packed_0}, {io_enq_uops_1_imm_packed_0}, {io_enq_uops_0_imm_packed_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][11:0] _GEN_296 = {{io_enq_uops_0_csr_addr_0}, {io_enq_uops_2_csr_addr_0}, {io_enq_uops_1_csr_addr_0}, {io_enq_uops_0_csr_addr_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_297 = {{io_enq_uops_0_rob_idx_0}, {io_enq_uops_2_rob_idx_0}, {io_enq_uops_1_rob_idx_0}, {io_enq_uops_0_rob_idx_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][4:0] _GEN_298 = {{io_enq_uops_0_ldq_idx_0}, {io_enq_uops_2_ldq_idx_0}, {io_enq_uops_1_ldq_idx_0}, {io_enq_uops_0_ldq_idx_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][4:0] _GEN_299 = {{io_enq_uops_0_stq_idx_0}, {io_enq_uops_2_stq_idx_0}, {io_enq_uops_1_stq_idx_0}, {io_enq_uops_0_stq_idx_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_300 = {{io_enq_uops_0_rxq_idx_0}, {io_enq_uops_2_rxq_idx_0}, {io_enq_uops_1_rxq_idx_0}, {io_enq_uops_0_rxq_idx_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_301 = {{io_enq_uops_0_pdst_0}, {io_enq_uops_2_pdst_0}, {io_enq_uops_1_pdst_0}, {io_enq_uops_0_pdst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_302 = {{io_enq_uops_0_prs1_0}, {io_enq_uops_2_prs1_0}, {io_enq_uops_1_prs1_0}, {io_enq_uops_0_prs1_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_303 = {{io_enq_uops_0_prs2_0}, {io_enq_uops_2_prs2_0}, {io_enq_uops_1_prs2_0}, {io_enq_uops_0_prs2_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_304 = {{io_enq_uops_0_prs3_0}, {io_enq_uops_2_prs3_0}, {io_enq_uops_1_prs3_0}, {io_enq_uops_0_prs3_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_305 = {{io_enq_uops_0_prs1_busy_0}, {io_enq_uops_2_prs1_busy_0}, {io_enq_uops_1_prs1_busy_0}, {io_enq_uops_0_prs1_busy_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_306 = {{io_enq_uops_0_prs2_busy_0}, {io_enq_uops_2_prs2_busy_0}, {io_enq_uops_1_prs2_busy_0}, {io_enq_uops_0_prs2_busy_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_307 = {{io_enq_uops_0_prs3_busy_0}, {io_enq_uops_2_prs3_busy_0}, {io_enq_uops_1_prs3_busy_0}, {io_enq_uops_0_prs3_busy_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][6:0] _GEN_308 = {{io_enq_uops_0_stale_pdst_0}, {io_enq_uops_2_stale_pdst_0}, {io_enq_uops_1_stale_pdst_0}, {io_enq_uops_0_stale_pdst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_309 = {{io_enq_uops_0_exception_0}, {io_enq_uops_2_exception_0}, {io_enq_uops_1_exception_0}, {io_enq_uops_0_exception_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][63:0] _GEN_310 = {{io_enq_uops_0_exc_cause_0}, {io_enq_uops_2_exc_cause_0}, {io_enq_uops_1_exc_cause_0}, {io_enq_uops_0_exc_cause_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_311 = {{io_enq_uops_0_bypassable_0}, {io_enq_uops_2_bypassable_0}, {io_enq_uops_1_bypassable_0}, {io_enq_uops_0_bypassable_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][4:0] _GEN_312 = {{io_enq_uops_0_mem_cmd_0}, {io_enq_uops_2_mem_cmd_0}, {io_enq_uops_1_mem_cmd_0}, {io_enq_uops_0_mem_cmd_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_313 = {{io_enq_uops_0_mem_size_0}, {io_enq_uops_2_mem_size_0}, {io_enq_uops_1_mem_size_0}, {io_enq_uops_0_mem_size_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_314 = {{io_enq_uops_0_mem_signed_0}, {io_enq_uops_2_mem_signed_0}, {io_enq_uops_1_mem_signed_0}, {io_enq_uops_0_mem_signed_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_315 = {{io_enq_uops_0_is_fence_0}, {io_enq_uops_2_is_fence_0}, {io_enq_uops_1_is_fence_0}, {io_enq_uops_0_is_fence_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_316 = {{io_enq_uops_0_is_fencei_0}, {io_enq_uops_2_is_fencei_0}, {io_enq_uops_1_is_fencei_0}, {io_enq_uops_0_is_fencei_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_317 = {{io_enq_uops_0_is_amo_0}, {io_enq_uops_2_is_amo_0}, {io_enq_uops_1_is_amo_0}, {io_enq_uops_0_is_amo_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_318 = {{io_enq_uops_0_uses_ldq_0}, {io_enq_uops_2_uses_ldq_0}, {io_enq_uops_1_uses_ldq_0}, {io_enq_uops_0_uses_ldq_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_319 = {{io_enq_uops_0_uses_stq_0}, {io_enq_uops_2_uses_stq_0}, {io_enq_uops_1_uses_stq_0}, {io_enq_uops_0_uses_stq_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_320 = {{io_enq_uops_0_is_sys_pc2epc_0}, {io_enq_uops_2_is_sys_pc2epc_0}, {io_enq_uops_1_is_sys_pc2epc_0}, {io_enq_uops_0_is_sys_pc2epc_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_321 = {{io_enq_uops_0_is_unique_0}, {io_enq_uops_2_is_unique_0}, {io_enq_uops_1_is_unique_0}, {io_enq_uops_0_is_unique_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_322 = {{io_enq_uops_0_flush_on_commit_0}, {io_enq_uops_2_flush_on_commit_0}, {io_enq_uops_1_flush_on_commit_0}, {io_enq_uops_0_flush_on_commit_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_323 = {{io_enq_uops_0_ldst_is_rs1_0}, {io_enq_uops_2_ldst_is_rs1_0}, {io_enq_uops_1_ldst_is_rs1_0}, {io_enq_uops_0_ldst_is_rs1_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][5:0] _GEN_324 = {{io_enq_uops_0_ldst_0}, {io_enq_uops_2_ldst_0}, {io_enq_uops_1_ldst_0}, {io_enq_uops_0_ldst_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][5:0] _GEN_325 = {{io_enq_uops_0_lrs1_0}, {io_enq_uops_2_lrs1_0}, {io_enq_uops_1_lrs1_0}, {io_enq_uops_0_lrs1_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][5:0] _GEN_326 = {{io_enq_uops_0_lrs2_0}, {io_enq_uops_2_lrs2_0}, {io_enq_uops_1_lrs2_0}, {io_enq_uops_0_lrs2_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][5:0] _GEN_327 = {{io_enq_uops_0_lrs3_0}, {io_enq_uops_2_lrs3_0}, {io_enq_uops_1_lrs3_0}, {io_enq_uops_0_lrs3_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_328 = {{io_enq_uops_0_ldst_val_0}, {io_enq_uops_2_ldst_val_0}, {io_enq_uops_1_ldst_val_0}, {io_enq_uops_0_ldst_val_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_329 = {{io_enq_uops_0_dst_rtype_0}, {io_enq_uops_2_dst_rtype_0}, {io_enq_uops_1_dst_rtype_0}, {io_enq_uops_0_dst_rtype_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_330 = {{io_enq_uops_0_lrs1_rtype_0}, {io_enq_uops_2_lrs1_rtype_0}, {io_enq_uops_1_lrs1_rtype_0}, {io_enq_uops_0_lrs1_rtype_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_331 = {{io_enq_uops_0_lrs2_rtype_0}, {io_enq_uops_2_lrs2_rtype_0}, {io_enq_uops_1_lrs2_rtype_0}, {io_enq_uops_0_lrs2_rtype_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_332 = {{io_enq_uops_0_frs3_en_0}, {io_enq_uops_2_frs3_en_0}, {io_enq_uops_1_frs3_en_0}, {io_enq_uops_0_frs3_en_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_333 = {{io_enq_uops_0_fp_val_0}, {io_enq_uops_2_fp_val_0}, {io_enq_uops_1_fp_val_0}, {io_enq_uops_0_fp_val_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_334 = {{io_enq_uops_0_fp_single_0}, {io_enq_uops_2_fp_single_0}, {io_enq_uops_1_fp_single_0}, {io_enq_uops_0_fp_single_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_335 = {{io_enq_uops_0_xcpt_pf_if_0}, {io_enq_uops_2_xcpt_pf_if_0}, {io_enq_uops_1_xcpt_pf_if_0}, {io_enq_uops_0_xcpt_pf_if_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_336 = {{io_enq_uops_0_xcpt_ae_if_0}, {io_enq_uops_2_xcpt_ae_if_0}, {io_enq_uops_1_xcpt_ae_if_0}, {io_enq_uops_0_xcpt_ae_if_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_337 = {{io_enq_uops_0_xcpt_ma_if_0}, {io_enq_uops_2_xcpt_ma_if_0}, {io_enq_uops_1_xcpt_ma_if_0}, {io_enq_uops_0_xcpt_ma_if_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_338 = {{io_enq_uops_0_bp_debug_if_0}, {io_enq_uops_2_bp_debug_if_0}, {io_enq_uops_1_bp_debug_if_0}, {io_enq_uops_0_bp_debug_if_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0] _GEN_339 = {{io_enq_uops_0_bp_xcpt_if_0}, {io_enq_uops_2_bp_xcpt_if_0}, {io_enq_uops_1_bp_xcpt_if_0}, {io_enq_uops_0_bp_xcpt_if_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_340 = {{io_enq_uops_0_debug_fsrc_0}, {io_enq_uops_2_debug_fsrc_0}, {io_enq_uops_1_debug_fsrc_0}, {io_enq_uops_0_debug_fsrc_0}}; // @[rob.scala:211:7, :655:23]
wire [3:0][1:0] _GEN_341 = {{io_enq_uops_0_debug_tsrc_0}, {io_enq_uops_2_debug_tsrc_0}, {io_enq_uops_1_debug_tsrc_0}, {io_enq_uops_0_debug_tsrc_0}}; // @[rob.scala:211:7, :655:23]
assign next_xcpt_uop_uopc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_uopc : r_xcpt_uop_uopc) : _T_1352 ? _GEN_265[idx] : r_xcpt_uop_uopc) : r_xcpt_uop_uopc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_inst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_inst : r_xcpt_uop_inst) : _T_1352 ? _GEN_266[idx] : r_xcpt_uop_inst) : r_xcpt_uop_inst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_debug_inst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_debug_inst : r_xcpt_uop_debug_inst) : _T_1352 ? _GEN_267[idx] : r_xcpt_uop_debug_inst) : r_xcpt_uop_debug_inst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_rvc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_rvc : r_xcpt_uop_is_rvc) : _T_1352 ? _GEN_268[idx] : r_xcpt_uop_is_rvc) : r_xcpt_uop_is_rvc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_debug_pc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_debug_pc : r_xcpt_uop_debug_pc) : _T_1352 ? _GEN_269[idx] : r_xcpt_uop_debug_pc) : r_xcpt_uop_debug_pc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_iq_type = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_iq_type : r_xcpt_uop_iq_type) : _T_1352 ? _GEN_270[idx] : r_xcpt_uop_iq_type) : r_xcpt_uop_iq_type; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_fu_code = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_fu_code : r_xcpt_uop_fu_code) : _T_1352 ? _GEN_271[idx] : r_xcpt_uop_fu_code) : r_xcpt_uop_fu_code; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_br_type = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_br_type : r_xcpt_uop_ctrl_br_type) : _T_1352 ? _GEN_272[idx] : r_xcpt_uop_ctrl_br_type) : r_xcpt_uop_ctrl_br_type; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_op1_sel = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_op1_sel : r_xcpt_uop_ctrl_op1_sel) : _T_1352 ? _GEN_273[idx] : r_xcpt_uop_ctrl_op1_sel) : r_xcpt_uop_ctrl_op1_sel; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_op2_sel = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_op2_sel : r_xcpt_uop_ctrl_op2_sel) : _T_1352 ? _GEN_274[idx] : r_xcpt_uop_ctrl_op2_sel) : r_xcpt_uop_ctrl_op2_sel; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_imm_sel = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_imm_sel : r_xcpt_uop_ctrl_imm_sel) : _T_1352 ? _GEN_275[idx] : r_xcpt_uop_ctrl_imm_sel) : r_xcpt_uop_ctrl_imm_sel; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_op_fcn = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_op_fcn : r_xcpt_uop_ctrl_op_fcn) : _T_1352 ? _GEN_276[idx] : r_xcpt_uop_ctrl_op_fcn) : r_xcpt_uop_ctrl_op_fcn; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_fcn_dw = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_fcn_dw : r_xcpt_uop_ctrl_fcn_dw) : _T_1352 ? _GEN_277[idx] : r_xcpt_uop_ctrl_fcn_dw) : r_xcpt_uop_ctrl_fcn_dw; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_csr_cmd = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_csr_cmd : r_xcpt_uop_ctrl_csr_cmd) : _T_1352 ? _GEN_278[idx] : r_xcpt_uop_ctrl_csr_cmd) : r_xcpt_uop_ctrl_csr_cmd; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_is_load = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_is_load : r_xcpt_uop_ctrl_is_load) : _T_1352 ? _GEN_279[idx] : r_xcpt_uop_ctrl_is_load) : r_xcpt_uop_ctrl_is_load; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_is_sta = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_is_sta : r_xcpt_uop_ctrl_is_sta) : _T_1352 ? _GEN_280[idx] : r_xcpt_uop_ctrl_is_sta) : r_xcpt_uop_ctrl_is_sta; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ctrl_is_std = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ctrl_is_std : r_xcpt_uop_ctrl_is_std) : _T_1352 ? _GEN_281[idx] : r_xcpt_uop_ctrl_is_std) : r_xcpt_uop_ctrl_is_std; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_iw_state = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_iw_state : r_xcpt_uop_iw_state) : _T_1352 ? _GEN_282[idx] : r_xcpt_uop_iw_state) : r_xcpt_uop_iw_state; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_iw_p1_poisoned = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_iw_p1_poisoned : r_xcpt_uop_iw_p1_poisoned) : _T_1352 ? _GEN_283[idx] : r_xcpt_uop_iw_p1_poisoned) : r_xcpt_uop_iw_p1_poisoned; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_iw_p2_poisoned = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_iw_p2_poisoned : r_xcpt_uop_iw_p2_poisoned) : _T_1352 ? _GEN_284[idx] : r_xcpt_uop_iw_p2_poisoned) : r_xcpt_uop_iw_p2_poisoned; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_br = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_br : r_xcpt_uop_is_br) : _T_1352 ? _GEN_285[idx] : r_xcpt_uop_is_br) : r_xcpt_uop_is_br; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_jalr = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_jalr : r_xcpt_uop_is_jalr) : _T_1352 ? _GEN_286[idx] : r_xcpt_uop_is_jalr) : r_xcpt_uop_is_jalr; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_jal = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_jal : r_xcpt_uop_is_jal) : _T_1352 ? _GEN_287[idx] : r_xcpt_uop_is_jal) : r_xcpt_uop_is_jal; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_sfb = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_sfb : r_xcpt_uop_is_sfb) : _T_1352 ? _GEN_288[idx] : r_xcpt_uop_is_sfb) : r_xcpt_uop_is_sfb; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_br_mask = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_br_mask : r_xcpt_uop_br_mask) : _T_1352 ? _GEN_289[idx] : r_xcpt_uop_br_mask) : r_xcpt_uop_br_mask; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_br_tag = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_br_tag : r_xcpt_uop_br_tag) : _T_1352 ? _GEN_290[idx] : r_xcpt_uop_br_tag) : r_xcpt_uop_br_tag; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ftq_idx = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ftq_idx : r_xcpt_uop_ftq_idx) : _T_1352 ? _GEN_291[idx] : r_xcpt_uop_ftq_idx) : r_xcpt_uop_ftq_idx; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_edge_inst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_edge_inst : r_xcpt_uop_edge_inst) : _T_1352 ? _GEN_292[idx] : r_xcpt_uop_edge_inst) : r_xcpt_uop_edge_inst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_pc_lob = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_pc_lob : r_xcpt_uop_pc_lob) : _T_1352 ? _GEN_293[idx] : r_xcpt_uop_pc_lob) : r_xcpt_uop_pc_lob; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_taken = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_taken : r_xcpt_uop_taken) : _T_1352 ? _GEN_294[idx] : r_xcpt_uop_taken) : r_xcpt_uop_taken; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_imm_packed = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_imm_packed : r_xcpt_uop_imm_packed) : _T_1352 ? _GEN_295[idx] : r_xcpt_uop_imm_packed) : r_xcpt_uop_imm_packed; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_csr_addr = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_csr_addr : r_xcpt_uop_csr_addr) : _T_1352 ? _GEN_296[idx] : r_xcpt_uop_csr_addr) : r_xcpt_uop_csr_addr; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_rob_idx = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_rob_idx : r_xcpt_uop_rob_idx) : _T_1352 ? _GEN_297[idx] : r_xcpt_uop_rob_idx) : r_xcpt_uop_rob_idx; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ldq_idx = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ldq_idx : r_xcpt_uop_ldq_idx) : _T_1352 ? _GEN_298[idx] : r_xcpt_uop_ldq_idx) : r_xcpt_uop_ldq_idx; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_stq_idx = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_stq_idx : r_xcpt_uop_stq_idx) : _T_1352 ? _GEN_299[idx] : r_xcpt_uop_stq_idx) : r_xcpt_uop_stq_idx; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_rxq_idx = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_rxq_idx : r_xcpt_uop_rxq_idx) : _T_1352 ? _GEN_300[idx] : r_xcpt_uop_rxq_idx) : r_xcpt_uop_rxq_idx; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_pdst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_pdst : r_xcpt_uop_pdst) : _T_1352 ? _GEN_301[idx] : r_xcpt_uop_pdst) : r_xcpt_uop_pdst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_prs1 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs1 : r_xcpt_uop_prs1) : _T_1352 ? _GEN_302[idx] : r_xcpt_uop_prs1) : r_xcpt_uop_prs1; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_prs2 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs2 : r_xcpt_uop_prs2) : _T_1352 ? _GEN_303[idx] : r_xcpt_uop_prs2) : r_xcpt_uop_prs2; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_prs3 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs3 : r_xcpt_uop_prs3) : _T_1352 ? _GEN_304[idx] : r_xcpt_uop_prs3) : r_xcpt_uop_prs3; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ppred = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ppred : r_xcpt_uop_ppred) : _T_1352 ? 5'h0 : r_xcpt_uop_ppred) : r_xcpt_uop_ppred; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_prs1_busy = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs1_busy : r_xcpt_uop_prs1_busy) : _T_1352 ? _GEN_305[idx] : r_xcpt_uop_prs1_busy) : r_xcpt_uop_prs1_busy; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_prs2_busy = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs2_busy : r_xcpt_uop_prs2_busy) : _T_1352 ? _GEN_306[idx] : r_xcpt_uop_prs2_busy) : r_xcpt_uop_prs2_busy; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_prs3_busy = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_prs3_busy : r_xcpt_uop_prs3_busy) : _T_1352 ? _GEN_307[idx] : r_xcpt_uop_prs3_busy) : r_xcpt_uop_prs3_busy; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ppred_busy = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ppred_busy : r_xcpt_uop_ppred_busy) : ~_T_1352 & r_xcpt_uop_ppred_busy) : r_xcpt_uop_ppred_busy; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :655:23]
assign next_xcpt_uop_stale_pdst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_stale_pdst : r_xcpt_uop_stale_pdst) : _T_1352 ? _GEN_308[idx] : r_xcpt_uop_stale_pdst) : r_xcpt_uop_stale_pdst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_exception = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_exception : r_xcpt_uop_exception) : _T_1352 ? _GEN_309[idx] : r_xcpt_uop_exception) : r_xcpt_uop_exception; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_exc_cause = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? {59'h0, new_xcpt_cause} : r_xcpt_uop_exc_cause) : _T_1352 ? _GEN_310[idx] : r_xcpt_uop_exc_cause) : r_xcpt_uop_exc_cause; // @[package.scala:16:47]
assign next_xcpt_uop_bypassable = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_bypassable : r_xcpt_uop_bypassable) : _T_1352 ? _GEN_311[idx] : r_xcpt_uop_bypassable) : r_xcpt_uop_bypassable; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_mem_cmd = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_mem_cmd : r_xcpt_uop_mem_cmd) : _T_1352 ? _GEN_312[idx] : r_xcpt_uop_mem_cmd) : r_xcpt_uop_mem_cmd; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_mem_size = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_mem_size : r_xcpt_uop_mem_size) : _T_1352 ? _GEN_313[idx] : r_xcpt_uop_mem_size) : r_xcpt_uop_mem_size; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_mem_signed = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_mem_signed : r_xcpt_uop_mem_signed) : _T_1352 ? _GEN_314[idx] : r_xcpt_uop_mem_signed) : r_xcpt_uop_mem_signed; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_fence = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_fence : r_xcpt_uop_is_fence) : _T_1352 ? _GEN_315[idx] : r_xcpt_uop_is_fence) : r_xcpt_uop_is_fence; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_fencei = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_fencei : r_xcpt_uop_is_fencei) : _T_1352 ? _GEN_316[idx] : r_xcpt_uop_is_fencei) : r_xcpt_uop_is_fencei; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_amo = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_amo : r_xcpt_uop_is_amo) : _T_1352 ? _GEN_317[idx] : r_xcpt_uop_is_amo) : r_xcpt_uop_is_amo; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_uses_ldq = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_uses_ldq : r_xcpt_uop_uses_ldq) : _T_1352 ? _GEN_318[idx] : r_xcpt_uop_uses_ldq) : r_xcpt_uop_uses_ldq; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_uses_stq = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_uses_stq : r_xcpt_uop_uses_stq) : _T_1352 ? _GEN_319[idx] : r_xcpt_uop_uses_stq) : r_xcpt_uop_uses_stq; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_sys_pc2epc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_sys_pc2epc : r_xcpt_uop_is_sys_pc2epc) : _T_1352 ? _GEN_320[idx] : r_xcpt_uop_is_sys_pc2epc) : r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_is_unique = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_is_unique : r_xcpt_uop_is_unique) : _T_1352 ? _GEN_321[idx] : r_xcpt_uop_is_unique) : r_xcpt_uop_is_unique; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_flush_on_commit = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_flush_on_commit : r_xcpt_uop_flush_on_commit) : _T_1352 ? _GEN_322[idx] : r_xcpt_uop_flush_on_commit) : r_xcpt_uop_flush_on_commit; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ldst_is_rs1 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ldst_is_rs1 : r_xcpt_uop_ldst_is_rs1) : _T_1352 ? _GEN_323[idx] : r_xcpt_uop_ldst_is_rs1) : r_xcpt_uop_ldst_is_rs1; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ldst = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ldst : r_xcpt_uop_ldst) : _T_1352 ? _GEN_324[idx] : r_xcpt_uop_ldst) : r_xcpt_uop_ldst; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_lrs1 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_lrs1 : r_xcpt_uop_lrs1) : _T_1352 ? _GEN_325[idx] : r_xcpt_uop_lrs1) : r_xcpt_uop_lrs1; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_lrs2 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_lrs2 : r_xcpt_uop_lrs2) : _T_1352 ? _GEN_326[idx] : r_xcpt_uop_lrs2) : r_xcpt_uop_lrs2; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_lrs3 = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_lrs3 : r_xcpt_uop_lrs3) : _T_1352 ? _GEN_327[idx] : r_xcpt_uop_lrs3) : r_xcpt_uop_lrs3; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_ldst_val = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_ldst_val : r_xcpt_uop_ldst_val) : _T_1352 ? _GEN_328[idx] : r_xcpt_uop_ldst_val) : r_xcpt_uop_ldst_val; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_dst_rtype = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_dst_rtype : r_xcpt_uop_dst_rtype) : _T_1352 ? _GEN_329[idx] : r_xcpt_uop_dst_rtype) : r_xcpt_uop_dst_rtype; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_lrs1_rtype = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_lrs1_rtype : r_xcpt_uop_lrs1_rtype) : _T_1352 ? _GEN_330[idx] : r_xcpt_uop_lrs1_rtype) : r_xcpt_uop_lrs1_rtype; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_lrs2_rtype = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_lrs2_rtype : r_xcpt_uop_lrs2_rtype) : _T_1352 ? _GEN_331[idx] : r_xcpt_uop_lrs2_rtype) : r_xcpt_uop_lrs2_rtype; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_frs3_en = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_frs3_en : r_xcpt_uop_frs3_en) : _T_1352 ? _GEN_332[idx] : r_xcpt_uop_frs3_en) : r_xcpt_uop_frs3_en; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_fp_val = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_fp_val : r_xcpt_uop_fp_val) : _T_1352 ? _GEN_333[idx] : r_xcpt_uop_fp_val) : r_xcpt_uop_fp_val; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_fp_single = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_fp_single : r_xcpt_uop_fp_single) : _T_1352 ? _GEN_334[idx] : r_xcpt_uop_fp_single) : r_xcpt_uop_fp_single; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_xcpt_pf_if = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_xcpt_pf_if : r_xcpt_uop_xcpt_pf_if) : _T_1352 ? _GEN_335[idx] : r_xcpt_uop_xcpt_pf_if) : r_xcpt_uop_xcpt_pf_if; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_xcpt_ae_if = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_xcpt_ae_if : r_xcpt_uop_xcpt_ae_if) : _T_1352 ? _GEN_336[idx] : r_xcpt_uop_xcpt_ae_if) : r_xcpt_uop_xcpt_ae_if; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_xcpt_ma_if = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_xcpt_ma_if : r_xcpt_uop_xcpt_ma_if) : _T_1352 ? _GEN_337[idx] : r_xcpt_uop_xcpt_ma_if) : r_xcpt_uop_xcpt_ma_if; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_bp_debug_if = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_bp_debug_if : r_xcpt_uop_bp_debug_if) : _T_1352 ? _GEN_338[idx] : r_xcpt_uop_bp_debug_if) : r_xcpt_uop_bp_debug_if; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_bp_xcpt_if = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_bp_xcpt_if : r_xcpt_uop_bp_xcpt_if) : _T_1352 ? _GEN_339[idx] : r_xcpt_uop_bp_xcpt_if) : r_xcpt_uop_bp_xcpt_if; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_debug_fsrc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_debug_fsrc : r_xcpt_uop_debug_fsrc) : _T_1352 ? _GEN_340[idx] : r_xcpt_uop_debug_fsrc) : r_xcpt_uop_debug_fsrc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
assign next_xcpt_uop_debug_tsrc = _T_1341 ? (new_xcpt_valid ? (_T_1348 ? new_xcpt_uop_debug_tsrc : r_xcpt_uop_debug_tsrc) : _T_1352 ? _GEN_341[idx] : r_xcpt_uop_debug_tsrc) : r_xcpt_uop_debug_tsrc; // @[rob.scala:258:29, :630:27, :631:17, :637:{47,76}, :639:41, :641:23, :643:27, :644:{25,93}, :646:33, :650:{30,56}, :651:37, :655:23]
wire [39:0] _r_xcpt_badvaddr_T = ~io_xcpt_fetch_pc_0; // @[util.scala:237:7]
wire [39:0] _r_xcpt_badvaddr_T_1 = {_r_xcpt_badvaddr_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] _r_xcpt_badvaddr_T_2 = ~_r_xcpt_badvaddr_T_1; // @[util.scala:237:{5,11}]
wire [39:0] _r_xcpt_badvaddr_T_3 = {_r_xcpt_badvaddr_T_2[39:6], _r_xcpt_badvaddr_T_2[5:0] | _GEN_293[idx]}; // @[util.scala:237:5]
wire [15:0] _r_xcpt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
wire [15:0] _r_xcpt_uop_br_mask_T_1 = next_xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire rob_deq; // @[rob.scala:685:25]
reg r_partial_row; // @[rob.scala:686:30]
wire [1:0] finished_committing_row_hi = {io_commit_valids_2_0, io_commit_valids_1_0}; // @[rob.scala:211:7, :693:23]
wire [2:0] _finished_committing_row_T = {finished_committing_row_hi, io_commit_valids_0_0}; // @[rob.scala:211:7, :693:23]
wire _finished_committing_row_T_1 = |_finished_committing_row_T; // @[rob.scala:693:{23,30}]
wire [1:0] finished_committing_row_hi_1 = {will_commit_2, will_commit_1}; // @[rob.scala:242:33, :694:19]
wire [2:0] _finished_committing_row_T_2 = {finished_committing_row_hi_1, will_commit_0}; // @[rob.scala:242:33, :694:19]
wire [1:0] _GEN_342 = {rob_head_vals_2, rob_head_vals_1}; // @[rob.scala:247:33, :694:42]
wire [1:0] finished_committing_row_hi_2; // @[rob.scala:694:42]
assign finished_committing_row_hi_2 = _GEN_342; // @[rob.scala:694:42]
wire [1:0] rob_head_lsb_hi; // @[rob.scala:702:62]
assign rob_head_lsb_hi = _GEN_342; // @[rob.scala:694:42, :702:62]
wire [1:0] empty_hi; // @[rob.scala:797:59]
assign empty_hi = _GEN_342; // @[rob.scala:694:42, :797:59]
wire [1:0] io_com_load_is_at_rob_head_hi; // @[rob.scala:874:89]
assign io_com_load_is_at_rob_head_hi = _GEN_342; // @[rob.scala:694:42, :874:89]
wire [2:0] _finished_committing_row_T_3 = {finished_committing_row_hi_2, rob_head_vals_0}; // @[rob.scala:247:33, :694:42]
wire [2:0] _finished_committing_row_T_4 = _finished_committing_row_T_2 ^ _finished_committing_row_T_3; // @[rob.scala:694:{19,26,42}]
wire _finished_committing_row_T_5 = _finished_committing_row_T_4 == 3'h0; // @[rob.scala:694:{26,50}]
wire _finished_committing_row_T_6 = _finished_committing_row_T_1 & _finished_committing_row_T_5; // @[rob.scala:693:{30,39}, :694:50]
wire _T_1416 = rob_head == rob_tail; // @[rob.scala:223:29, :227:29, :695:33]
wire _finished_committing_row_T_7; // @[rob.scala:695:33]
assign _finished_committing_row_T_7 = _T_1416; // @[rob.scala:695:33]
wire _full_T; // @[rob.scala:796:26]
assign _full_T = _T_1416; // @[rob.scala:695:33, :796:26]
wire _empty_T; // @[rob.scala:797:27]
assign _empty_T = _T_1416; // @[rob.scala:695:33, :797:27]
wire _finished_committing_row_T_8 = r_partial_row & _finished_committing_row_T_7; // @[rob.scala:686:30, :695:{21,33}]
wire _finished_committing_row_T_9 = ~maybe_full; // @[rob.scala:238:29, :695:49]
wire _finished_committing_row_T_10 = _finished_committing_row_T_8 & _finished_committing_row_T_9; // @[rob.scala:695:{21,46,49}]
wire _finished_committing_row_T_11 = ~_finished_committing_row_T_10; // @[rob.scala:695:{5,46}]
wire finished_committing_row = _finished_committing_row_T_6 & _finished_committing_row_T_11; // @[rob.scala:693:39, :694:59, :695:5]
wire [5:0] _rob_head_T = {1'h0, rob_head} + 6'h1; // @[util.scala:203:14]
wire [4:0] _rob_head_T_1 = _rob_head_T[4:0]; // @[util.scala:203:14]
wire [4:0] _rob_head_T_2 = _rob_head_T_1; // @[util.scala:203:{14,20}]
wire [2:0] _rob_head_lsb_T = {rob_head_lsb_hi, rob_head_vals_0}; // @[rob.scala:247:33, :702:62]
wire _rob_head_lsb_T_1 = _rob_head_lsb_T[0]; // @[OneHot.scala:85:71]
wire _rob_head_lsb_T_2 = _rob_head_lsb_T[1]; // @[OneHot.scala:85:71]
wire _rob_head_lsb_T_3 = _rob_head_lsb_T[2]; // @[OneHot.scala:85:71]
wire [2:0] _rob_head_lsb_T_4 = {_rob_head_lsb_T_3, 2'h0}; // @[OneHot.scala:85:71]
wire [2:0] _rob_head_lsb_T_5 = _rob_head_lsb_T_2 ? 3'h2 : _rob_head_lsb_T_4; // @[OneHot.scala:85:71]
wire [2:0] _rob_head_lsb_T_6 = _rob_head_lsb_T_1 ? 3'h1 : _rob_head_lsb_T_5; // @[OneHot.scala:85:71]
wire rob_head_lsb_hi_1 = _rob_head_lsb_T_6[2]; // @[OneHot.scala:30:18]
wire _rob_head_lsb_T_7 = rob_head_lsb_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] rob_head_lsb_lo = _rob_head_lsb_T_6[1:0]; // @[OneHot.scala:31:18]
wire [1:0] _rob_head_lsb_T_8 = {1'h0, rob_head_lsb_hi_1} | rob_head_lsb_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _rob_head_lsb_T_9 = _rob_head_lsb_T_8[1]; // @[OneHot.scala:32:28]
wire [1:0] _rob_head_lsb_T_10 = {_rob_head_lsb_T_7, _rob_head_lsb_T_9}; // @[OneHot.scala:32:{10,14}]
reg pnr_maybe_at_tail; // @[rob.scala:723:36]
wire _T_1428 = rob_state == 2'h1; // @[rob.scala:220:26, :725:33]
wire _safe_to_inc_T; // @[rob.scala:725:33]
assign _safe_to_inc_T = _T_1428; // @[rob.scala:725:33]
wire _io_ready_T; // @[rob.scala:803:33]
assign _io_ready_T = _T_1428; // @[rob.scala:725:33, :803:33]
wire _safe_to_inc_T_1 = &rob_state; // @[rob.scala:220:26, :725:59]
wire safe_to_inc = _safe_to_inc_T | _safe_to_inc_T_1; // @[rob.scala:725:{33,46,59}]
wire _do_inc_row_T = rob_pnr_unsafe_0 | rob_pnr_unsafe_1; // @[rob.scala:246:33, :726:47]
wire _do_inc_row_T_1 = _do_inc_row_T | rob_pnr_unsafe_2; // @[rob.scala:246:33, :726:47]
wire _do_inc_row_T_2 = ~_do_inc_row_T_1; // @[rob.scala:726:{23,47}]
wire _do_inc_row_T_3 = rob_pnr != rob_tail; // @[rob.scala:227:29, :231:29, :726:64]
wire _do_inc_row_T_4 = ~pnr_maybe_at_tail; // @[rob.scala:723:36, :726:89]
wire _do_inc_row_T_5 = full & _do_inc_row_T_4; // @[rob.scala:239:26, :726:{86,89}]
wire _do_inc_row_T_6 = _do_inc_row_T_3 | _do_inc_row_T_5; // @[rob.scala:726:{64,77,86}]
wire do_inc_row = _do_inc_row_T_2 & _do_inc_row_T_6; // @[rob.scala:726:{23,52,77}]
wire [1:0] _GEN_343 = {io_enq_valids_2_0, io_enq_valids_1_0}; // @[rob.scala:211:7, :727:34]
wire [1:0] hi; // @[rob.scala:727:34]
assign hi = _GEN_343; // @[rob.scala:727:34]
wire [1:0] hi_1; // @[rob.scala:770:30]
assign hi_1 = _GEN_343; // @[rob.scala:727:34, :770:30]
wire [1:0] hi_2; // @[rob.scala:774:30]
assign hi_2 = _GEN_343; // @[rob.scala:727:34, :774:30]
wire [1:0] rob_tail_lsb_hi; // @[rob.scala:775:62]
assign rob_tail_lsb_hi = _GEN_343; // @[rob.scala:727:34, :775:62]
wire [1:0] _rob_pnr_lsb_T = io_enq_valids_1_0 ? 2'h1 : 2'h2; // @[Mux.scala:50:70]
wire [1:0] _rob_pnr_lsb_T_1 = io_enq_valids_0_0 ? 2'h0 : _rob_pnr_lsb_T; // @[Mux.scala:50:70]
wire [5:0] _rob_pnr_T = {1'h0, rob_pnr} + 6'h1; // @[util.scala:203:14]
wire [4:0] _rob_pnr_T_1 = _rob_pnr_T[4:0]; // @[util.scala:203:14]
wire [4:0] _rob_pnr_T_2 = _rob_pnr_T_1; // @[util.scala:203:{14,20}]
wire [1:0] _rob_pnr_lsb_T_2 = rob_pnr_unsafe_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70]
wire [1:0] _rob_pnr_lsb_T_3 = rob_pnr_unsafe_0 ? 2'h0 : _rob_pnr_lsb_T_2; // @[Mux.scala:50:70]
wire [1:0] rob_pnr_lsb_hi = {rob_pnr_unsafe_2, rob_pnr_unsafe_1}; // @[rob.scala:246:33, :740:53]
wire [2:0] _rob_pnr_lsb_T_4 = {rob_pnr_lsb_hi, rob_pnr_unsafe_0}; // @[rob.scala:246:33, :740:53]
wire [1:0] rob_pnr_lsb_hi_1 = {rob_tail_vals_2, rob_tail_vals_1}; // @[rob.scala:248:33, :740:87]
wire [2:0] _rob_pnr_lsb_T_5 = {rob_pnr_lsb_hi_1, rob_tail_vals_0}; // @[rob.scala:248:33, :740:87]
wire [2:0] _rob_pnr_lsb_T_6 = _rob_pnr_lsb_T_5; // @[util.scala:373:29]
wire [2:0] _rob_pnr_lsb_T_7 = {1'h0, _rob_pnr_lsb_T_5[2:1]}; // @[util.scala:373:29]
wire [2:0] _rob_pnr_lsb_T_8 = {2'h0, _rob_pnr_lsb_T_5[2]}; // @[util.scala:373:29]
wire [2:0] _rob_pnr_lsb_T_9 = _rob_pnr_lsb_T_6 | _rob_pnr_lsb_T_7; // @[util.scala:373:{29,45}]
wire [2:0] _rob_pnr_lsb_T_10 = _rob_pnr_lsb_T_9 | _rob_pnr_lsb_T_8; // @[util.scala:373:{29,45}]
wire [2:0] _rob_pnr_lsb_T_11 = ~_rob_pnr_lsb_T_10; // @[util.scala:373:45]
wire [2:0] _rob_pnr_lsb_T_12 = _rob_pnr_lsb_T_4 | _rob_pnr_lsb_T_11; // @[rob.scala:740:{53,60,62}]
wire _rob_pnr_lsb_T_13 = _rob_pnr_lsb_T_12[0]; // @[OneHot.scala:48:45]
wire _rob_pnr_lsb_T_14 = _rob_pnr_lsb_T_12[1]; // @[OneHot.scala:48:45]
wire _rob_pnr_lsb_T_15 = _rob_pnr_lsb_T_12[2]; // @[OneHot.scala:48:45]
wire [1:0] _rob_pnr_lsb_T_16 = _rob_pnr_lsb_T_14 ? 2'h1 : 2'h2; // @[OneHot.scala:48:45]
wire [1:0] _rob_pnr_lsb_T_17 = _rob_pnr_lsb_T_13 ? 2'h0 : _rob_pnr_lsb_T_16; // @[OneHot.scala:48:45]
wire _pnr_maybe_at_tail_T = ~rob_deq; // @[rob.scala:685:25, :745:26]
wire _pnr_maybe_at_tail_T_1 = do_inc_row | pnr_maybe_at_tail; // @[rob.scala:723:36, :726:52, :745:50]
wire _pnr_maybe_at_tail_T_2 = _pnr_maybe_at_tail_T & _pnr_maybe_at_tail_T_1; // @[rob.scala:745:{26,35,50}] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_26( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN = a_first_done & a_first_1; // @[Decoupled.scala:51:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d64s3k3z4c( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_41 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s3k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s3k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s3k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s3k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s3k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_34( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_306 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_308 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_309 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module TLXbar_pbus_out_i1_o2_a29d64s8k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [7:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18]
wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18]
wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [7:0] _addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _requestBOI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_uncommonBits_T_1 = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] requestBOI_uncommonBits_1 = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] _beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_1_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsCOI_filtered_1_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71]
wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [12:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [12:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [7:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [7:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_1_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] out_1_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [7:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [28:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [7:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [7:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [7:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [7:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [7:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign anonOut_a_bits_address = out_0_a_bits_address[12:0]; // @[Xbar.scala:216:19, :222:41]
wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_2 = _requestAIO_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46]
wire _requestAIO_T_4 = _requestAIO_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_5 = in_0_a_bits_address ^ 29'h10000000; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_7 = _requestAIO_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46]
wire _requestAIO_T_9 = _requestAIO_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54]
wire [7:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [7:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73]
assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_24( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_53( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File HellaCacheArbiter.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat,log2Up}
import org.chipsalliance.cde.config.Parameters
class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
{
val io = IO(new Bundle {
val requestor = Flipped(Vec(n, new HellaCacheIO))
val mem = new HellaCacheIO
})
if (n == 1) {
io.mem <> io.requestor.head
} else {
val s1_id = Reg(UInt())
val s2_id = RegNext(s1_id)
io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_)
io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
io.requestor(0).req.ready := io.mem.req.ready
for (i <- 1 until n)
io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
for (i <- n-1 to 0 by -1) {
val req = io.requestor(i).req
def connect_s0() = {
io.mem.req.bits := req.bits
io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W))
s1_id := i.U
}
def connect_s1() = {
io.mem.s1_kill := io.requestor(i).s1_kill
io.mem.s1_data := io.requestor(i).s1_data
}
def connect_s2() = {
io.mem.s2_kill := io.requestor(i).s2_kill
}
if (i == n-1) {
connect_s0()
connect_s1()
connect_s2()
} else {
when (req.valid) { connect_s0() }
when (s1_id === i.U) { connect_s1() }
when (s2_id === i.U) { connect_s2() }
}
}
io.mem.uncached_resp.foreach(_.ready := false.B)
for (i <- 0 until n) {
val resp = io.requestor(i).resp
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U
resp.valid := io.mem.resp.valid && tag_hit
io.requestor(i).s2_xcpt := io.mem.s2_xcpt
io.requestor(i).s2_gpa := io.mem.s2_gpa
io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte
io.requestor(i).ordered := io.mem.ordered
io.requestor(i).store_pending := io.mem.store_pending
io.requestor(i).perf := io.mem.perf
io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U
io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw
io.requestor(i).s2_uncached := io.mem.s2_uncached
io.requestor(i).s2_paddr := io.mem.s2_paddr
io.requestor(i).clock_enabled := io.mem.clock_enabled
resp.bits := io.mem.resp.bits
resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
io.requestor(i).replay_next := io.mem.replay_next
io.requestor(i).uncached_resp.map { uncached_resp =>
val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U
uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit
when (uncached_resp.ready && uncached_tag_hit) {
io.mem.uncached_resp.get.ready := true.B
}
uncached_resp.bits := io.mem.uncached_resp.get.bits
uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n)
}
}
}
}
| module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7]
input clock, // @[HellaCacheArbiter.scala:10:7]
input reset, // @[HellaCacheArbiter.scala:10:7]
output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_gf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_gf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14]
input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_gf_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_gf_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_store_pending // @[HellaCacheArbiter.scala:12:14]
);
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_s2_gpa = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [39:0] io_mem_s2_gpa = 40'h0; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [31:0] io_requestor_0_s2_paddr = 32'h0; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [31:0] io_mem_s2_paddr = 32'h0; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_requestor_0_resp_bits_has_data = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_mem_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_mem_resp_bits_has_data = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_store_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_resp_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_nack_cause_raw = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_uncached = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_replay = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_replay_next = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_ordered = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_acquire = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_grant = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_blocked = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenRMW = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptLoadThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterStore = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_cause_raw = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_uncached = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_replay = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_replay_next = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_ordered = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_acquire = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_grant = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_tlbMiss = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_blocked = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_0_resp_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_requestor_0_resp_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_mem_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_valid_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_req_bits_addr_0 = io_requestor_0_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_dv_0 = io_requestor_0_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s1_kill_0 = io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_nack_0 = io_mem_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_valid_0 = io_mem_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_gf_ld = io_requestor_0_s2_xcpt_gf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_gf_st = io_requestor_0_s2_xcpt_gf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a28d64s3k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_34 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a28d64s3k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a28d64s3k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FPDiv.scala:
package saturn.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import chisel3.util.experimental.decode._
import saturn.common._
import saturn.insns._
class VFREC7(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val rvs2_input = Input(UInt(64.W))
val eew = Input(UInt(2.W))
val frm = Input(UInt(3.W))
val out = Output(UInt(64.W))
val exc = Output(UInt(5.W))
})
val table = Seq(
127, 125, 123, 121, 119, 117, 116, 114, 112, 110, // 0-9
109, 107, 105, 104, 102, 100, 99, 97, 96, 94,
93, 91, 90, 88, 87, 85, 84, 83, 81, 80,
79, 77, 76, 75, 74, 72, 71, 70, 69, 68,
66, 65, 64, 63, 62, 61, 60, 59, 58, 57,
56, 55, 54, 53, 52, 51, 50, 49, 48, 47,
46, 45, 44, 43, 42, 41, 40, 40, 39, 38,
37, 36, 35, 35, 34, 33, 32, 31, 31, 30,
29, 28, 28, 27, 26, 25, 25, 24, 23, 23,
22, 21, 21, 20, 19, 19, 18, 17, 17, 16,
15, 15, 14, 14, 13, 12, 12, 11, 11, 10,
9, 9, 8, 8, 7, 7, 6, 5, 5, 4,
4, 3, 3, 2, 2, 1, 1, 0)
def count_leading_zeros(in: UInt): UInt = {
PriorityEncoder(Reverse(in))
}
val rvs2_bits = io.rvs2_input
val fTypes = Seq(FType.H, FType.S, FType.D)
val eew_sel = (1 to 3).map(_.U === io.eew)
val classify = Mux1H(eew_sel, fTypes.map(f => f.classify(f.recode(rvs2_bits(f.ieeeWidth-1,0)))))
val dz = WireInit(false.B)
val nv = WireInit(false.B)
val of = WireInit(false.B)
val nx = WireInit(false.B)
val ret = Wire(UInt(64.W))
ret := 0.U // it should not be possible to fall into this case
when (classify(0)) { // -inf
ret := Mux1H(eew_sel, fTypes.map(f => 1.U ## 0.U((f.ieeeWidth-1).W)))
} .elsewhen (classify(7)) { // +inf
ret := 0.U
} .elsewhen (classify(3)) { // -0
ret := Mux1H(eew_sel, fTypes.map(f => 1.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W)))
dz := true.B
} .elsewhen (classify(4)) { // +0
ret := Mux1H(eew_sel, fTypes.map(f => 0.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W)))
dz := true.B
} .elsewhen (classify(8)) { // sNaN
ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN))
nv := true.B
} .elsewhen (classify(9)) { // qNaN
ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN))
} .otherwise {
val sub = classify(2) || classify(5)
val exp = Mux1H(eew_sel, fTypes.map(f => (rvs2_bits >> (f.sig - 1))(f.exp-1,0)))
val sig = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.sig-2,0)))
val sign = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.ieeeWidth-1)))
val norm_exp = WireInit(exp)
val norm_sig = WireInit(sig)
val round_abnormal = WireInit(false.B)
when (sub) {
val leading_zeros = Mux1H(eew_sel, fTypes.map(f => count_leading_zeros(sig(f.sig-2,0))))
val exp_new = exp - leading_zeros
val sig_new = (sig << (leading_zeros +& 1.U)) & Mux1H(eew_sel, fTypes.map(f => ~(0.U((f.sig-1).W))))
norm_exp := exp_new
norm_sig := sig_new
when (exp_new =/= 0.U && ~exp_new =/= 0.U) {
round_abnormal := true.B
when (io.frm === 1.U ||
(io.frm === 2.U && !sign) ||
(io.frm === 3.U && sign)) {
ret := Mux1H(eew_sel, fTypes.map(f => (sign << (f.sig + f.exp - 1)) | (~(0.U(f.exp.W)) << (f.sig - 1)))) - 1.U
} .otherwise {
ret := Mux1H(eew_sel, fTypes.map(f => (sign << (f.sig + f.exp - 1)) | (~(0.U(f.exp.W)) << (f.sig - 1))))
}
}
}
when (!round_abnormal) {
val idx = Mux1H(eew_sel, fTypes.map(f => norm_sig >> (f.sig - 1 - 7)))(6,0)
val lookup = VecInit(table.map(_.U(7.W)))(idx)
val default_out_sig = Mux1H(eew_sel, fTypes.map(f => lookup << (f.sig - 1 - 7)))
val biases = fTypes.map(f => (1 << (f.exp - 1)) - 1)
val default_out_exp = Mux1H(eew_sel, fTypes.zip(biases).map { case (f, b) =>
(2 * b).U + ~norm_exp
})
val out_sig = WireInit(default_out_sig)
val out_exp = WireInit(default_out_exp)
when (default_out_exp === 0.U || (~default_out_exp === 0.U)) {
out_sig := (default_out_sig >> 1) | Mux1H(eew_sel, fTypes.map(f => 1.U << (f.sig - 1 - 1)))
when (~default_out_exp === 0.U) {
out_sig := default_out_sig >> 1;
out_exp := 0.U
}
}
ret := Mux1H(eew_sel, fTypes.map(f => sign ## out_exp(f.exp-1,0) ## out_sig(f.sig-2,0)))
}
when (round_abnormal) {
of := true.B
nx := true.B
}
}
io.out := Mux1H(eew_sel, fTypes.map(f => Fill(64 / f.ieeeWidth, ret(f.ieeeWidth-1,0))))
io.exc := nv ## dz ## of ## false.B ## nx
}
class VFRSQRT7(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val rvs2_input = Input(UInt(64.W))
val eew = Input(UInt(2.W))
val out = Output(UInt(64.W))
val exc = Output(UInt(5.W))
})
val table = Seq(
52, 51, 50, 48, 47, 46, 44, 43,
42, 41, 40, 39, 38, 36, 35, 34,
33, 32, 31, 30, 30, 29, 28, 27,
26, 25, 24, 23, 23, 22, 21, 20,
19, 19, 18, 17, 16, 16, 15, 14,
14, 13, 12, 12, 11, 10, 10, 9,
9, 8, 7, 7, 6, 6, 5, 4,
4, 3, 3, 2, 2, 1, 1, 0,
127, 125, 123, 121, 119, 118, 116, 114,
113, 111, 109, 108, 106, 105, 103, 102,
100, 99, 97, 96, 95, 93, 92, 91,
90, 88, 87, 86, 85, 84, 83, 82,
80, 79, 78, 77, 76, 75, 74, 73,
72, 71, 70, 70, 69, 68, 67, 66,
65, 64, 63, 63, 62, 61, 60, 59,
59, 58, 57, 56, 56, 55, 54, 53
)
def count_leading_zeros(in: UInt): UInt = {
PriorityEncoder(Reverse(in))
}
val rvs2_bits = io.rvs2_input
val fTypes = Seq(FType.H, FType.S, FType.D)
val eew_sel = (1 to 3).map(_.U === io.eew)
val classify = Mux1H(eew_sel, fTypes.map(f => f.classify(f.recode(rvs2_bits(f.ieeeWidth-1,0)))))
val dz = WireInit(false.B)
val nv = WireInit(false.B)
val of = WireInit(false.B)
val nx = WireInit(false.B)
val ret = Wire(UInt(64.W))
ret := 0.U // it should not be possible to fall into this case
when (classify(0) || classify(1) || classify(2) || classify(8)) { // -inf, -normal, -subnormal, sNaN
nv := true.B
ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN))
} .elsewhen (classify(9)) { // qNaN
ret := Mux1H(eew_sel, fTypes.map(f => f.ieeeQNaN))
} .elsewhen (classify(3)) { // -0
ret := Mux1H(eew_sel, fTypes.map(f => 1.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W)))
dz := true.B
} .elsewhen (classify(4)) { // +0
ret := Mux1H(eew_sel, fTypes.map(f => 0.U(1.W) ## ~(0.U((f.exp).W)) ## 0.U((f.sig-1).W)))
dz := true.B
} .elsewhen (classify(7)) { // +inf
ret := 0.U
} .otherwise {
val sub = classify(5)
val exp = Mux1H(eew_sel, fTypes.map(f => (rvs2_bits >> (f.sig - 1))(f.exp-1,0)))
val sig = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.sig-2,0)))
val sign = Mux1H(eew_sel, fTypes.map(f => rvs2_bits(f.ieeeWidth-1)))
val norm_exp = Wire(UInt((1+fTypes.map(_.exp).max).W))
norm_exp := exp
val norm_sig = WireInit(sig)
when (sub) {
val leading_zeros = Mux1H(eew_sel, fTypes.map(f => count_leading_zeros(sig(f.sig-2,0))))
val exp_new = (0.U(1.W) ## exp) - leading_zeros
val sig_new = (sig << (leading_zeros +& 1.U)) & Mux1H(eew_sel, fTypes.map(f => ~(0.U((f.sig-1).W))))
norm_exp := exp_new
norm_sig := sig_new
}
val idx = ((norm_exp(0) << 6) | Mux1H(eew_sel, fTypes.map(f => norm_sig >> (f.sig - 1 - 7 + 1))))(6,0)
val lookup = VecInit(table.map(_.U(7.W)))(idx)
val out_sig = Mux1H(eew_sel, fTypes.map(f => lookup << (f.sig - 1 - 7)))
val biases = fTypes.map(f => (1 << (f.exp - 1)) - 1)
val out_exp = Mux1H(eew_sel, fTypes.zip(biases).map { case (f, b) =>
val bias3 = ((3 * b).S((f.exp + 2).W) - norm_exp.asSInt - 1.S).asUInt
bias3 >> 1
})
ret := Mux1H(eew_sel, fTypes.map(f => sign ## out_exp(f.exp-1,0) ## out_sig(f.sig-2,0)))
}
io.out := Mux1H(eew_sel, fTypes.map(f => Fill(64 / f.ieeeWidth, ret(f.ieeeWidth-1,0))))
io.exc := nv ## dz ## of ## false.B ## nx
}
case object FPDivSqrtFactory extends FunctionalUnitFactory {
def insns = Seq(
FDIV.VV, FDIV.VF,
FRDIV.VF,
FSQRT_V,
FRSQRT7_V,
FREC7_V,
FCLASS_V
).map(_.elementWise)
def generate(implicit p: Parameters) = new FPDivSqrt()(p)
}
class FPDivSqrt(implicit p: Parameters) extends IterativeFunctionalUnit()(p) with HasFPUParameters {
val supported_insns = FPDivSqrtFactory.insns
io.set_vxsat := false.B
val divSqrt = Module(new hardfloat.DivSqrtRecF64)
val divSqrt16 = Module(new hardfloat.DivSqrtRecFN_small(FType.H.exp, FType.H.sig, 0))
val accept_inst = new VectorDecoder(
io.iss.op.funct3, io.iss.op.funct6, io.iss.op.rs1, io.iss.op.rs2,
supported_insns,
Seq(FPSwapVdV2))
val ctrl = new VectorDecoder(
op.funct3, op.funct6, op.rs1, op.rs2,
supported_insns,
Seq(FPSwapVdV2))
val ctrl_isDiv = io.iss.op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv)
val divSqrt_ready = (ctrl_isDiv && divSqrt.io.inReady_div) || (!ctrl_isDiv && divSqrt.io.inReady_sqrt)
val divSqrt16_ready = divSqrt16.io.inReady
val div_op = op.opff6.isOneOf(OPFFunct6.fdiv, OPFFunct6.frdiv)
val rvs2_bits = op.rvs2_elem
val rvs1_bits = op.rvs1_elem
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
divSqrt.io.roundingMode := op.frm
divSqrt16.io.detectTininess := hardfloat.consts.tininess_afterRounding
divSqrt16.io.roundingMode := op.frm
val iss_fire_pipe = Reg(Bool())
iss_fire_pipe := io.iss.valid && io.iss.ready
divSqrt.io.inValid := iss_fire_pipe && !(op.rvd_eew === 1.U) && (div_op || (op.opff6 === OPFFunct6.funary1 && op.rs1 === 0.U))
divSqrt.io.sqrtOp := !div_op
divSqrt16.io.inValid := iss_fire_pipe && (op.rvd_eew === 1.U) && (div_op || (op.opff6 === OPFFunct6.funary1 && op.rs1 === 0.U))
divSqrt16.io.sqrtOp := !div_op
io.hazard.valid := valid
io.hazard.bits.eg := op.wvd_eg
when (op.rvs1_eew === 3.U) {
divSqrt.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, FType.D.recode(rvs1_bits), FType.D.recode(rvs2_bits))
divSqrt.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, FType.D.recode(rvs2_bits), FType.D.recode(rvs1_bits))
} .otherwise {
val narrow_rvs2_bits = rvs2_bits(31,0)
val narrow_rvs1_bits = rvs1_bits(31,0)
val widen = Seq(FType.S.recode(narrow_rvs2_bits), FType.S.recode(narrow_rvs1_bits)).zip(
Seq.fill(2)(Module(new hardfloat.RecFNToRecFN(8, 24, 11, 53)))).map { case(input, upconvert) =>
upconvert.io.in := input
upconvert.io.roundingMode := op.frm
upconvert.io.detectTininess := hardfloat.consts.tininess_afterRounding
upconvert
}
divSqrt.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, widen(1).io.out, widen(0).io.out)
divSqrt.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, widen(0).io.out, widen(1).io.out)
}
divSqrt16.io.a := Mux(ctrl.bool(FPSwapVdV2) && div_op, FType.H.recode(rvs1_bits), FType.H.recode(rvs2_bits))
divSqrt16.io.b := Mux(ctrl.bool(FPSwapVdV2) || !div_op, FType.H.recode(rvs2_bits), FType.H.recode(rvs1_bits))
val divSqrt_out_valid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
val divSqrt16_out_valid = divSqrt16.io.outValid_div || divSqrt16.io.outValid_sqrt
val narrow = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24))
narrow.io.roundingMode := op.frm
narrow.io.detectTininess := hardfloat.consts.tininess_afterRounding
narrow.io.in := divSqrt.io.out
val divSqrt_out = Mux(op.vd_eew === 3.U, FType.D.ieee(divSqrt.io.out), Fill(2, FType.S.ieee(narrow.io.out)))
val out_buffer = RegEnable(divSqrt_out, divSqrt_out_valid)
val out_toWrite = RegInit(false.B)
val divSqrt_write = Mux(out_toWrite, out_buffer, divSqrt_out)
val divSqrt16_out = FType.H.ieee(divSqrt16.io.out)
val out16_buffer = RegEnable(divSqrt16_out, divSqrt16_out_valid)
val out16_toWrite = RegInit(false.B)
val divSqrt16_write = Mux(out16_toWrite, out16_buffer, divSqrt16_out)
// vfclass instruction
val gen_vfclass = Seq(FType.H, FType.S, FType.D).zipWithIndex.map { case(fType, i) =>
Fill(2, Cat(0.U((fType.ieeeWidth-10).W), fType.classify(fType.recode(rvs2_bits(fType.ieeeWidth-1,0)))))
}
val vfclass_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 16.U
val vfrsqrt7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 4.U
val vfrec7_inst = op.opff6.isOneOf(OPFFunct6.funary1) && op.rs1 === 5.U
// Reciprocal Sqrt Approximation
val recSqrt7 = Module(new VFRSQRT7)
recSqrt7.io.rvs2_input := Mux(valid && vfrsqrt7_inst, rvs2_bits, 0.U)
recSqrt7.io.eew := op.rvs2_eew
// Reciprocal Approximation
val rec7 = Module(new VFREC7)
rec7.io.rvs2_input := Mux(valid && vfrec7_inst, rvs2_bits, 0.U)
rec7.io.eew := op.rvs2_eew
rec7.io.frm := op.frm
// Capture result in case of write port backpressure
when (io.write.fire) {
out_toWrite := false.B
out16_toWrite := false.B
} .elsewhen (divSqrt_out_valid) {
out_toWrite := true.B
out16_toWrite := true.B
}
val out = Mux1H(
Seq(vfclass_inst, vfrsqrt7_inst, vfrec7_inst, out_toWrite || divSqrt_out_valid || divSqrt16_out_valid),
Seq(Mux1H(Seq(op.rvs2_eew === 3.U, op.rvs2_eew === 2.U, op.rvs2_eew === 1.U), Seq(gen_vfclass(2), gen_vfclass(1), gen_vfclass(0))), recSqrt7.io.out, rec7.io.out, divSqrt_write)
)(63,0)
io.write.valid := ((vfclass_inst || vfrsqrt7_inst || vfrec7_inst) && valid) || out_toWrite || divSqrt_out_valid
io.write.bits.eg := op.wvd_eg
io.write.bits.mask := FillInterleaved(8, op.wmask)
io.write.bits.data := Fill(dLenB >> 3, out)
io.iss.ready := accept_inst.matched && ((divSqrt_ready && io.iss.op.vd_eew >= 2.U) || (divSqrt16_ready && io.iss.op.vd_eew === 1.U)) && (!valid || last)
last := io.write.fire
io.set_fflags.valid := divSqrt_out_valid || divSqrt16_out_valid || (vfrsqrt7_inst && io.write.fire) || (vfrec7_inst && io.write.fire)
io.set_fflags.bits := (divSqrt.io.exceptionFlags & Fill(5, divSqrt_out_valid)) | divSqrt16.io.exceptionFlags & Fill(5, divSqrt_out_valid) | (recSqrt7.io.exc & Fill(5, vfrsqrt7_inst)) | (rec7.io.exc & Fill(5, vfrec7_inst))
io.scalar_write.valid := false.B
io.scalar_write.bits := DontCare
io.acc := false.B
io.tail := false.B
}
| module VFREC7( // @[FPDiv.scala:13:7]
input [63:0] io_rvs2_input, // @[FPDiv.scala:14:14]
input [1:0] io_eew, // @[FPDiv.scala:14:14]
input [2:0] io_frm, // @[FPDiv.scala:14:14]
output [63:0] io_out // @[FPDiv.scala:14:14]
);
wire [127:0][6:0] _GEN = '{7'h0, 7'h1, 7'h1, 7'h2, 7'h2, 7'h3, 7'h3, 7'h4, 7'h4, 7'h5, 7'h5, 7'h6, 7'h7, 7'h7, 7'h8, 7'h8, 7'h9, 7'h9, 7'hA, 7'hB, 7'hB, 7'hC, 7'hC, 7'hD, 7'hE, 7'hE, 7'hF, 7'hF, 7'h10, 7'h11, 7'h11, 7'h12, 7'h13, 7'h13, 7'h14, 7'h15, 7'h15, 7'h16, 7'h17, 7'h17, 7'h18, 7'h19, 7'h19, 7'h1A, 7'h1B, 7'h1C, 7'h1C, 7'h1D, 7'h1E, 7'h1F, 7'h1F, 7'h20, 7'h21, 7'h22, 7'h23, 7'h23, 7'h24, 7'h25, 7'h26, 7'h27, 7'h28, 7'h28, 7'h29, 7'h2A, 7'h2B, 7'h2C, 7'h2D, 7'h2E, 7'h2F, 7'h30, 7'h31, 7'h32, 7'h33, 7'h34, 7'h35, 7'h36, 7'h37, 7'h38, 7'h39, 7'h3A, 7'h3B, 7'h3C, 7'h3D, 7'h3E, 7'h3F, 7'h40, 7'h41, 7'h42, 7'h44, 7'h45, 7'h46, 7'h47, 7'h48, 7'h4A, 7'h4B, 7'h4C, 7'h4D, 7'h4F, 7'h50, 7'h51, 7'h53, 7'h54, 7'h55, 7'h57, 7'h58, 7'h5A, 7'h5B, 7'h5D, 7'h5E, 7'h60, 7'h61, 7'h63, 7'h64, 7'h66, 7'h68, 7'h69, 7'h6B, 7'h6D, 7'h6E, 7'h70, 7'h72, 7'h74, 7'h75, 7'h77, 7'h79, 7'h7B, 7'h7D, 7'h7F};
wire eew_sel_0 = io_eew == 2'h1; // @[FPDiv.scala:44:34]
wire eew_sel_1 = io_eew == 2'h2; // @[FPDiv.scala:44:34]
wire classify_rawIn_isZeroExpIn = io_rvs2_input[14:10] == 5'h0; // @[FPDiv.scala:45:78]
wire [3:0] classify_rawIn_normDist = io_rvs2_input[9] ? 4'h0 : io_rvs2_input[8] ? 4'h1 : io_rvs2_input[7] ? 4'h2 : io_rvs2_input[6] ? 4'h3 : io_rvs2_input[5] ? 4'h4 : io_rvs2_input[4] ? 4'h5 : io_rvs2_input[3] ? 4'h6 : io_rvs2_input[2] ? 4'h7 : {3'h4, ~(io_rvs2_input[1])}; // @[Mux.scala:50:70]
wire [24:0] _classify_rawIn_subnormFract_T = {15'h0, io_rvs2_input[9:0]} << classify_rawIn_normDist; // @[Mux.scala:50:70]
wire [5:0] _classify_rawIn_adjustedExp_T_4 = (classify_rawIn_isZeroExpIn ? {2'h3, ~classify_rawIn_normDist} : {1'h0, io_rvs2_input[14:10]}) + {4'h4, classify_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire _classify_rawIn_out_sig_T_2 = classify_rawIn_isZeroExpIn ? _classify_rawIn_subnormFract_T[8] : io_rvs2_input[9]; // @[FPDiv.scala:45:78]
wire [2:0] _classify_T_2 = classify_rawIn_isZeroExpIn & ~(|(io_rvs2_input[9:0])) ? 3'h0 : _classify_rawIn_adjustedExp_T_4[5:3]; // @[FPDiv.scala:45:78]
wire _classify_isInf_T = _classify_T_2[0] | (&(_classify_rawIn_adjustedExp_T_4[5:4])) & (|(io_rvs2_input[9:0])); // @[FPDiv.scala:45:78]
wire [2:0] classify_code = {_classify_T_2[2:1], _classify_isInf_T}; // @[FPU.scala:254:17]
wire _classify_isNormal_T = _classify_T_2[2:1] == 2'h1; // @[FPU.scala:259:46]
wire classify_isSubnormal = classify_code == 3'h1 | _classify_isNormal_T & {_classify_isInf_T, _classify_rawIn_adjustedExp_T_4[2:0]} < 4'h2; // @[FPU.scala:254:17, :258:{30,55}, :259:{28,36,46,54}]
wire classify_isNormal = _classify_isNormal_T & (|{_classify_isInf_T, _classify_rawIn_adjustedExp_T_4[2:1]}) | _classify_T_2[2:1] == 2'h2; // @[FPU.scala:258:55, :259:46, :260:{35,38,57,67}]
wire classify_isZero = classify_code == 3'h0; // @[FPU.scala:254:17, :261:23]
wire classify_isInf = (&(_classify_T_2[2:1])) & ~_classify_isInf_T; // @[FPU.scala:256:28, :262:{27,30}]
wire classify_rawIn_isZeroExpIn_1 = io_rvs2_input[30:23] == 8'h0; // @[FPDiv.scala:45:78]
wire [4:0] classify_rawIn_normDist_1 = io_rvs2_input[22] ? 5'h0 : io_rvs2_input[21] ? 5'h1 : io_rvs2_input[20] ? 5'h2 : io_rvs2_input[19] ? 5'h3 : io_rvs2_input[18] ? 5'h4 : io_rvs2_input[17] ? 5'h5 : io_rvs2_input[16] ? 5'h6 : io_rvs2_input[15] ? 5'h7 : io_rvs2_input[14] ? 5'h8 : io_rvs2_input[13] ? 5'h9 : io_rvs2_input[12] ? 5'hA : io_rvs2_input[11] ? 5'hB : io_rvs2_input[10] ? 5'hC : io_rvs2_input[9] ? 5'hD : io_rvs2_input[8] ? 5'hE : io_rvs2_input[7] ? 5'hF : io_rvs2_input[6] ? 5'h10 : io_rvs2_input[5] ? 5'h11 : io_rvs2_input[4] ? 5'h12 : io_rvs2_input[3] ? 5'h13 : io_rvs2_input[2] ? 5'h14 : io_rvs2_input[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [53:0] _classify_rawIn_subnormFract_T_2 = {31'h0, io_rvs2_input[22:0]} << classify_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [8:0] _classify_rawIn_adjustedExp_T_9 = (classify_rawIn_isZeroExpIn_1 ? {4'hF, ~classify_rawIn_normDist_1} : {1'h0, io_rvs2_input[30:23]}) + {7'h20, classify_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire _classify_rawIn_out_sig_T_6 = classify_rawIn_isZeroExpIn_1 ? _classify_rawIn_subnormFract_T_2[21] : io_rvs2_input[22]; // @[FPDiv.scala:45:78]
wire [2:0] _classify_T_25 = classify_rawIn_isZeroExpIn_1 & ~(|(io_rvs2_input[22:0])) ? 3'h0 : _classify_rawIn_adjustedExp_T_9[8:6]; // @[FPDiv.scala:45:78]
wire _classify_isInf_T_2 = _classify_T_25[0] | (&(_classify_rawIn_adjustedExp_T_9[8:7])) & (|(io_rvs2_input[22:0])); // @[FPDiv.scala:45:78]
wire [2:0] classify_code_1 = {_classify_T_25[2:1], _classify_isInf_T_2}; // @[FPU.scala:254:17]
wire _classify_isNormal_T_4 = _classify_T_25[2:1] == 2'h1; // @[FPU.scala:259:46]
wire classify_isSubnormal_1 = classify_code_1 == 3'h1 | _classify_isNormal_T_4 & {_classify_isInf_T_2, _classify_rawIn_adjustedExp_T_9[5:0]} < 7'h2; // @[FPU.scala:254:17, :258:{30,55}, :259:{28,36,46,54}]
wire classify_isNormal_1 = _classify_isNormal_T_4 & (|{_classify_isInf_T_2, _classify_rawIn_adjustedExp_T_9[5:1]}) | _classify_T_25[2:1] == 2'h2; // @[FPU.scala:258:55, :259:46, :260:{35,38,57,67}]
wire classify_isZero_1 = classify_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23]
wire classify_isInf_1 = (&(_classify_T_25[2:1])) & ~_classify_isInf_T_2; // @[FPU.scala:256:28, :262:{27,30}]
wire classify_rawIn_isZeroExpIn_2 = io_rvs2_input[62:52] == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire [5:0] classify_rawIn_normDist_2 = io_rvs2_input[51] ? 6'h0 : io_rvs2_input[50] ? 6'h1 : io_rvs2_input[49] ? 6'h2 : io_rvs2_input[48] ? 6'h3 : io_rvs2_input[47] ? 6'h4 : io_rvs2_input[46] ? 6'h5 : io_rvs2_input[45] ? 6'h6 : io_rvs2_input[44] ? 6'h7 : io_rvs2_input[43] ? 6'h8 : io_rvs2_input[42] ? 6'h9 : io_rvs2_input[41] ? 6'hA : io_rvs2_input[40] ? 6'hB : io_rvs2_input[39] ? 6'hC : io_rvs2_input[38] ? 6'hD : io_rvs2_input[37] ? 6'hE : io_rvs2_input[36] ? 6'hF : io_rvs2_input[35] ? 6'h10 : io_rvs2_input[34] ? 6'h11 : io_rvs2_input[33] ? 6'h12 : io_rvs2_input[32] ? 6'h13 : io_rvs2_input[31] ? 6'h14 : io_rvs2_input[30] ? 6'h15 : io_rvs2_input[29] ? 6'h16 : io_rvs2_input[28] ? 6'h17 : io_rvs2_input[27] ? 6'h18 : io_rvs2_input[26] ? 6'h19 : io_rvs2_input[25] ? 6'h1A : io_rvs2_input[24] ? 6'h1B : io_rvs2_input[23] ? 6'h1C : io_rvs2_input[22] ? 6'h1D : io_rvs2_input[21] ? 6'h1E : io_rvs2_input[20] ? 6'h1F : io_rvs2_input[19] ? 6'h20 : io_rvs2_input[18] ? 6'h21 : io_rvs2_input[17] ? 6'h22 : io_rvs2_input[16] ? 6'h23 : io_rvs2_input[15] ? 6'h24 : io_rvs2_input[14] ? 6'h25 : io_rvs2_input[13] ? 6'h26 : io_rvs2_input[12] ? 6'h27 : io_rvs2_input[11] ? 6'h28 : io_rvs2_input[10] ? 6'h29 : io_rvs2_input[9] ? 6'h2A : io_rvs2_input[8] ? 6'h2B : io_rvs2_input[7] ? 6'h2C : io_rvs2_input[6] ? 6'h2D : io_rvs2_input[5] ? 6'h2E : io_rvs2_input[4] ? 6'h2F : io_rvs2_input[3] ? 6'h30 : io_rvs2_input[2] ? 6'h31 : {5'h19, ~(io_rvs2_input[1])}; // @[Mux.scala:50:70]
wire [114:0] _classify_rawIn_subnormFract_T_4 = {63'h0, io_rvs2_input[51:0]} << classify_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [11:0] _classify_rawIn_adjustedExp_T_14 = (classify_rawIn_isZeroExpIn_2 ? {6'h3F, ~classify_rawIn_normDist_2} : {1'h0, io_rvs2_input[62:52]}) + {10'h100, classify_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire _classify_rawIn_out_sig_T_10 = classify_rawIn_isZeroExpIn_2 ? _classify_rawIn_subnormFract_T_4[50] : io_rvs2_input[51]; // @[rawFloatFromFN.scala:46:21, :48:30, :52:{33,64}, :70:33]
wire [2:0] _classify_T_48 = classify_rawIn_isZeroExpIn_2 & ~(|(io_rvs2_input[51:0])) ? 3'h0 : _classify_rawIn_adjustedExp_T_14[11:9]; // @[recFNFromFN.scala:48:{15,50}]
wire _classify_isInf_T_4 = _classify_T_48[0] | (&(_classify_rawIn_adjustedExp_T_14[11:10])) & (|(io_rvs2_input[51:0])); // @[recFNFromFN.scala:48:{15,76}]
wire [2:0] classify_code_2 = {_classify_T_48[2:1], _classify_isInf_T_4}; // @[FPU.scala:254:17]
wire _classify_isNormal_T_8 = _classify_T_48[2:1] == 2'h1; // @[FPU.scala:259:46]
wire classify_isSubnormal_2 = classify_code_2 == 3'h1 | _classify_isNormal_T_8 & {_classify_isInf_T_4, _classify_rawIn_adjustedExp_T_14[8:0]} < 10'h2; // @[FPU.scala:254:17, :258:{30,55}, :259:{28,36,46,54}]
wire classify_isNormal_2 = _classify_isNormal_T_8 & (|{_classify_isInf_T_4, _classify_rawIn_adjustedExp_T_14[8:1]}) | _classify_T_48[2:1] == 2'h2; // @[FPU.scala:258:55, :259:46, :260:{35,38,57,67}]
wire classify_isZero_2 = classify_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23]
wire classify_isInf_2 = (&(_classify_T_48[2:1])) & ~_classify_isInf_T_4; // @[FPU.scala:256:28, :262:{27,30}]
wire [9:0] classify = (eew_sel_0 ? {(&classify_code) & _classify_rawIn_out_sig_T_2, (&classify_code) & ~_classify_rawIn_out_sig_T_2, classify_isInf & ~(io_rvs2_input[15]), classify_isNormal & ~(io_rvs2_input[15]), classify_isSubnormal & ~(io_rvs2_input[15]), classify_isZero & ~(io_rvs2_input[15]), classify_isZero & io_rvs2_input[15], classify_isSubnormal & io_rvs2_input[15], classify_isNormal & io_rvs2_input[15], classify_isInf & io_rvs2_input[15]} : 10'h0) | (eew_sel_1 ? {(&classify_code_1) & _classify_rawIn_out_sig_T_6, (&classify_code_1) & ~_classify_rawIn_out_sig_T_6, classify_isInf_1 & ~(io_rvs2_input[31]), classify_isNormal_1 & ~(io_rvs2_input[31]), classify_isSubnormal_1 & ~(io_rvs2_input[31]), classify_isZero_1 & ~(io_rvs2_input[31]), classify_isZero_1 & io_rvs2_input[31], classify_isSubnormal_1 & io_rvs2_input[31], classify_isNormal_1 & io_rvs2_input[31], classify_isInf_1 & io_rvs2_input[31]} : 10'h0) | ((&io_eew) ? {(&classify_code_2) & _classify_rawIn_out_sig_T_10, (&classify_code_2) & ~_classify_rawIn_out_sig_T_10, classify_isInf_2 & ~(io_rvs2_input[63]), classify_isNormal_2 & ~(io_rvs2_input[63]), classify_isSubnormal_2 & ~(io_rvs2_input[63]), classify_isZero_2 & ~(io_rvs2_input[63]), classify_isZero_2 & io_rvs2_input[63], classify_isSubnormal_2 & io_rvs2_input[63], classify_isNormal_2 & io_rvs2_input[63], classify_isInf_2 & io_rvs2_input[63]} : 10'h0); // @[Mux.scala:30:73]
wire sub = classify[2] | classify[5]; // @[Mux.scala:30:73]
wire [10:0] exp = {3'h0, {3'h0, eew_sel_0 ? io_rvs2_input[14:10] : 5'h0} | (eew_sel_1 ? io_rvs2_input[30:23] : 8'h0)} | ((&io_eew) ? io_rvs2_input[62:52] : 11'h0); // @[Mux.scala:30:73]
wire [51:0] sig = {29'h0, {13'h0, eew_sel_0 ? io_rvs2_input[9:0] : 10'h0} | (eew_sel_1 ? io_rvs2_input[22:0] : 23'h0)} | ((&io_eew) ? io_rvs2_input[51:0] : 52'h0); // @[Mux.scala:30:73]
wire sign = eew_sel_0 & io_rvs2_input[15] | eew_sel_1 & io_rvs2_input[31] | (&io_eew) & io_rvs2_input[63]; // @[Mux.scala:30:73]
wire [18:0] _GEN_0 = {sig[5:4], sig[7:6], sig[9:8], sig[11:10], sig[13:12], sig[15:14], sig[17:16], sig[19:18], sig[21:20], sig[23]} & 19'h55555; // @[Mux.scala:30:73]
wire [3:0] _GEN_1 = _GEN_0[18:15] | {sig[7:6], sig[9:8]} & 4'h5; // @[Mux.scala:30:73]
wire [3:0] _GEN_2 = _GEN_0[10:7] | {sig[15:14], sig[17:16]} & 4'h5; // @[Mux.scala:30:73]
wire [3:0] _GEN_3 = {_GEN_0[2:0], 1'h0} | {sig[23:22], sig[25:24]} & 4'h5; // @[Mux.scala:30:73]
wire [5:0] leading_zeros = {1'h0, {1'h0, ~eew_sel_0 | sig[9] ? 4'h0 : sig[8] ? 4'h1 : sig[7] ? 4'h2 : sig[6] ? 4'h3 : sig[5] ? 4'h4 : sig[4] ? 4'h5 : sig[3] ? 4'h6 : sig[2] ? 4'h7 : {3'h4, ~(sig[1])}} | (~eew_sel_1 | sig[22] ? 5'h0 : sig[21] ? 5'h1 : sig[20] ? 5'h2 : sig[19] ? 5'h3 : sig[18] ? 5'h4 : sig[17] ? 5'h5 : sig[16] ? 5'h6 : sig[15] ? 5'h7 : sig[14] ? 5'h8 : sig[13] ? 5'h9 : sig[12] ? 5'hA : sig[11] ? 5'hB : sig[10] ? 5'hC : sig[9] ? 5'hD : sig[8] ? 5'hE : sig[7] ? 5'hF : sig[6] ? 5'h10 : sig[5] ? 5'h11 : sig[4] ? 5'h12 : sig[3] ? 5'h13 : sig[2] ? 5'h14 : sig[1] ? 5'h15 : 5'h16)} | (~(&io_eew) | sig[51] ? 6'h0 : sig[50] ? 6'h1 : sig[49] ? 6'h2 : sig[48] ? 6'h3 : sig[47] ? 6'h4 : sig[46] ? 6'h5 : sig[45] ? 6'h6 : sig[44] ? 6'h7 : sig[43] ? 6'h8 : sig[42] ? 6'h9 : sig[41] ? 6'hA : sig[40] ? 6'hB : sig[39] ? 6'hC : sig[38] ? 6'hD : sig[37] ? 6'hE : sig[36] ? 6'hF : sig[35] ? 6'h10 : sig[34] ? 6'h11 : sig[33] ? 6'h12 : sig[32] ? 6'h13 : sig[31] ? 6'h14 : sig[30] ? 6'h15 : sig[29] ? 6'h16 : sig[28] ? 6'h17 : sig[27] ? 6'h18 : sig[26] ? 6'h19 : sig[25] ? 6'h1A : _GEN_3[0] ? 6'h1B : _GEN_3[1] ? 6'h1C : _GEN_3[2] ? 6'h1D : _GEN_3[3] ? 6'h1E : sig[20] ? 6'h1F : sig[19] ? 6'h20 : _GEN_0[5] | sig[18] ? 6'h21 : sig[17] ? 6'h22 : _GEN_2[0] ? 6'h23 : _GEN_2[1] ? 6'h24 : _GEN_2[2] ? 6'h25 : _GEN_2[3] ? 6'h26 : sig[12] ? 6'h27 : sig[11] ? 6'h28 : _GEN_0[13] | sig[10] ? 6'h29 : sig[9] ? 6'h2A : _GEN_1[0] ? 6'h2B : _GEN_1[1] ? 6'h2C : _GEN_1[2] ? 6'h2D : _GEN_1[3] ? 6'h2E : sig[4] ? 6'h2F : sig[3] ? 6'h30 : sig[2] ? 6'h31 : {5'h19, ~(sig[1])}); // @[OneHot.scala:48:45]
wire [10:0] _exp_new_T = exp - {5'h0, leading_zeros}; // @[Mux.scala:30:73]
wire [178:0] _sig_new_T_1 = {127'h0, sig} << {1'h0, leading_zeros} + 7'h1; // @[Mux.scala:30:73]
wire [10:0] norm_exp = sub ? _exp_new_T : exp; // @[Mux.scala:30:73]
wire [48:0] _GEN_4 = sub ? _sig_new_T_1[51:3] & ({29'h0, {13'h0, {7{eew_sel_0}}} | {20{eew_sel_1}}} | {49{&io_eew}}) : sig[51:3]; // @[Mux.scala:30:73]
wire _GEN_5 = (|_exp_new_T) & _exp_new_T != 11'h7FF; // @[FPDiv.scala:82:25, :87:{21,29,41}]
wire [6:0] _GEN_6 = _GEN[(eew_sel_0 ? _GEN_4[6:0] : 7'h0) | (eew_sel_1 ? _GEN_4[19:13] : 7'h0) | ((&io_eew) ? _GEN_4[48:42] : 7'h0)]; // @[Mux.scala:30:73]
wire [51:0] default_out_sig = {29'h0, {13'h0, eew_sel_0 ? {_GEN_6, 3'h0} : 10'h0} | (eew_sel_1 ? {_GEN_6, 16'h0} : 23'h0)} | ((&io_eew) ? {_GEN_6, 45'h0} : 52'h0); // @[Mux.scala:30:73]
wire [10:0] default_out_exp = (eew_sel_0 ? ~norm_exp + 11'h1E : 11'h0) | (eew_sel_1 ? ~norm_exp + 11'hFE : 11'h0) | ((&io_eew) ? ~norm_exp - 11'h2 : 11'h0); // @[Mux.scala:30:73]
wire _GEN_7 = default_out_exp == 11'h0 | (&default_out_exp); // @[Mux.scala:30:73]
wire [51:0] out_sig = _GEN_7 ? ((&default_out_exp) ? {1'h0, default_out_sig[51:1]} : {&io_eew, default_out_sig[51:24], default_out_sig[23] | eew_sel_1, default_out_sig[22:11], default_out_sig[10] | eew_sel_0, default_out_sig[9:1]}) : default_out_sig; // @[Mux.scala:30:73]
wire [10:0] out_exp = _GEN_7 & (&default_out_exp) ? 11'h0 : default_out_exp; // @[Mux.scala:30:73]
wire [63:0] ret = classify[0] ? {&io_eew, 31'h0, eew_sel_1, 15'h0, eew_sel_0, 15'h0} : classify[7] ? 64'h0 : classify[3] ? {32'h0, {16'h0, eew_sel_0 ? 16'hFC00 : 16'h0} | (eew_sel_1 ? 32'hFF800000 : 32'h0)} | ((&io_eew) ? 64'hFFF0000000000000 : 64'h0) : classify[4] ? {32'h0, {16'h0, eew_sel_0 ? 16'h7C00 : 16'h0} | (eew_sel_1 ? 32'h7F800000 : 32'h0)} | ((&io_eew) ? 64'h7FF0000000000000 : 64'h0) : classify[8] ? {32'h0, {16'h0, eew_sel_0 ? 16'h7E00 : 16'h0} | (eew_sel_1 ? 32'h7FC00000 : 32'h0)} | ((&io_eew) ? 64'h7FF8000000000000 : 64'h0) : classify[9] ? {32'h0, {16'h0, eew_sel_0 ? 16'h7E00 : 16'h0} | (eew_sel_1 ? 32'h7FC00000 : 32'h0)} | ((&io_eew) ? 64'h7FF8000000000000 : 64'h0) : sub & _GEN_5 ? (sub & _GEN_5 ? (io_frm == 3'h1 | io_frm == 3'h2 & ~sign | io_frm == 3'h3 & sign ? ({32'h0, {16'h0, eew_sel_0 ? {sign, 15'h7C00} : 16'h0} | (eew_sel_1 ? {sign, 31'h7F800000} : 32'h0)} | ((&io_eew) ? {sign, 63'h7FF0000000000000} : 64'h0)) - 64'h1 : {32'h0, {16'h0, eew_sel_0 ? {sign, 15'h7C00} : 16'h0} | (eew_sel_1 ? {sign, 31'h7F800000} : 32'h0)} | ((&io_eew) ? {sign, 63'h7FF0000000000000} : 64'h0)) : 64'h0) : {32'h0, {16'h0, eew_sel_0 ? {sign, out_exp[4:0], out_sig[9:0]} : 16'h0} | (eew_sel_1 ? {sign, out_exp[7:0], out_sig[22:0]} : 32'h0)} | ((&io_eew) ? {sign, out_exp, out_sig} : 64'h0); // @[Mux.scala:30:73]
assign io_out = (eew_sel_0 ? {2{{2{ret[15:0]}}}} : 64'h0) | (eew_sel_1 ? {2{ret[31:0]}} : 64'h0) | ((&io_eew) ? ret : 64'h0); // @[Mux.scala:30:73]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_56( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File RegField.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.util.{DecoupledIO, ReadyValidIO}
import org.json4s.JsonDSL._
import org.json4s.JsonAST.JValue
import freechips.rocketchip.util.{SimpleRegIO}
case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
object RegReadFn
{
// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
// iready may combinationally depend on oready
// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
// effects must become visible on the cycle after ovalid && oready
// data is only inspected when ovalid && oready
implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
new RegReadFn(false, x)
implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
RegReadFn((ivalid, oready) => {
x.request.valid := ivalid
x.response.ready := oready
(x.request.ready, x.response.valid, x.response.bits)
})
// (ready: Bool) => (valid: Bool, data: UInt)
// valid must not combinationally depend on ready
// effects must become visible on the cycle after valid && ready
implicit def apply(x: Bool => (Bool, UInt)) =
new RegReadFn(true, { case (_, oready) =>
val (ovalid, data) = x(oready)
(true.B, ovalid, data)
})
// read from a ReadyValidIO (only safe if there is a consistent source of data)
implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) })
// read from a register
implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x))
// noop
implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U)
}
case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
object RegWriteFn
{
// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
// iready may combinationally depend on both oready and data
// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
// effects must become visible on the cycle after ovalid && oready
// data should only be used for an effect when ivalid && iready
implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
new RegWriteFn(false, x)
implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
RegWriteFn((ivalid, oready, data) => {
x.request.valid := ivalid
x.request.bits := data
x.response.ready := oready
(x.request.ready, x.response.valid)
})
// (valid: Bool, data: UInt) => (ready: Bool)
// ready may combinationally depend on data (but not valid)
// effects must become visible on the cycle after valid && ready
implicit def apply(x: (Bool, UInt) => Bool) =
// combinational => data valid on oready
new RegWriteFn(true, { case (_, oready, data) =>
(true.B, x(oready, data))
})
// write to a DecoupledIO (only safe if there is a consistent sink draining data)
// NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid
implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
// updates a register (or adds a mux to a wire)
implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B })
// noop
implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B })
}
case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc])
{
require (width >= 0, s"RegField width must be >= 0, not $width")
def pipelined = !read.combinational || !write.combinational
def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R)))
def toJson(byteOffset: Int, bitOffset: Int): JValue = {
( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~
("bitOffset" -> bitOffset) ~
("bitWidth" -> width) ~
("name" -> desc.map(_.name)) ~
("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~
("resetValue" -> desc.map{_.reset}) ~
("group" -> desc.map{_.group}) ~
("groupDesc" -> desc.map{_.groupDesc}) ~
("accessType" -> desc.map {d => d.access.toString}) ~
("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~
("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~
("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~
("enumerations" -> desc.map {d =>
Option(d.enumerations.map { case (key, (name, edesc)) =>
(("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc))
}).filter(_.nonEmpty)}) )
}
}
object RegField
{
// Byte address => sequence of bitfields, lowest index => lowest address
type Map = (Int, Seq[RegField])
def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved))
def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc))
def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))
def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None)
def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc))
def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None)
def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R)))
def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None)
def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W)))
// This RegField allows 'set' to set bits in 'reg'.
// and to clear bits when the bus writes bits of value 1.
// Setting takes priority over clearing.
def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField =
RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }),
desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)})
// This RegField wraps an explicit register
// (e.g. Black-Boxed Register) to create a R/W register.
def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField =
RegField(n, bb.q, RegWriteFn((valid, data) => {
bb.en := valid
bb.d := data
true.B
}), desc)
// Create byte-sized read-write RegFields out of a large UInt register.
// It is updated when any of the (implemented) bytes are written, the non-written
// bytes are just copied over from their current value.
// Because the RegField are all byte-sized, this is also suitable when a register is larger
// than the intended bus width of the device (atomic updates are impossible).
def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = {
require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.")
val numFullBytes = reg.getWidth/8
val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0
val numPadBytes = numBytes - numFullBytes - numPartialBytes
val pad = reg | 0.U((8*numBytes).W)
val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
val newBytes = WireDefault(oldBytes)
val valids = WireDefault(VecInit.fill(numBytes) { false.B })
when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => {
valids(i) := valid
when (valid) {newBytes(i) := data}
true.B
})
val fullBytes = Seq.tabulate(numFullBytes) { i =>
val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")}
RegField(8, oldBytes(i), wrFn(i), newDesc)}
val partialBytes = if (numPartialBytes > 0) {
val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")}
Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc),
RegField(8 - (reg.getWidth % 8)))
} else Nil
val padBytes = Seq.fill(numPadBytes){RegField(8)}
fullBytes ++ partialBytes ++ padBytes
}
def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = {
val width = reg.getWidth
require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits")
bytes(reg, width/8, desc)
}
def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None)
def bytes(reg: UInt): Seq[RegField] = bytes(reg, None)
}
trait HasRegMap
{
def regmap(mapping: RegField.Map*): Unit
val interrupts: Vec[Bool]
}
// See Example.scala for an example of how to use regmap
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File CLINT.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.Annotated
object CLINTConsts
{
def msipOffset(hart: Int) = hart * msipBytes
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
def timeOffset = 0xbff8
def msipBytes = 4
def timecmpBytes = 8
def size = 0x10000
def timeWidth = 64
def ipiWidth = 32
def ints = 2
}
case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
{
def address = AddressSet(baseAddress, CLINTConsts.size-1)
}
case object CLINTKey extends Field[Option[CLINTParams]](None)
case class CLINTAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object CLINTAttachKey extends Field(CLINTAttachParams())
class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
import CLINTConsts._
// clint0 => at most 4095 devices
val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
override val alwaysExtended = true
}
val node: TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes)
val intnode : IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
val io = IO(new Bundle {
val rtcTick = Input(Bool())
})
val time = RegInit(0.U(timeWidth.W))
when (io.rtcTick) { time := time + 1.U }
val nTiles = intnode.out.size
val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) }
val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
val (intnode_out, _) = intnode.out.unzip
intnode_out.zipWithIndex.foreach { case (int, i) =>
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}
/* 0000 msip hart 0
* 0004 msip hart 1
* 4000 mtimecmp hart 0 lo
* 4004 mtimecmp hart 0 hi
* 4008 mtimecmp hart 1 lo
* 400c mtimecmp hart 1 hi
* bff8 mtime lo
* bffc mtime hi
*/
node.regmap(
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),
RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
)
}
}
/** Trait that will connect a CLINT to a subsystem */
trait CanHavePeripheryCLINT { this: BaseSubsystem =>
val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } }
val clintTick = clintDomainWrapper { InModuleBody {
val tick = IO(Input(Bool()))
clint.module.io.rtcTick := tick
tick
}}
(clint, clintDomainWrapper, clintTick)
}.unzip3
}
| module CLINT( // @[CLINT.scala:65:9]
input clock, // @[CLINT.scala:65:9]
input reset, // @[CLINT.scala:65:9]
output auto_int_out_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_1, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_rtcTick // @[CLINT.scala:69:16]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9]
wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9]
wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9]
wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9]
wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire intnodeOut_1; // @[MixedNode.scala:542:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9]
wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_int_out_0_0; // @[CLINT.scala:65:9]
wire auto_int_out_1_0; // @[CLINT.scala:65:9]
wire auto_in_a_ready_0; // @[CLINT.scala:65:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9]
wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9]
wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9]
wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9]
wire auto_in_d_valid_0; // @[CLINT.scala:65:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9]
wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9]
wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9]
wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9]
wire _intnodeOut_0_T; // @[CLINT.scala:82:37]
assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9]
wire _intnodeOut_1_T; // @[CLINT.scala:83:43]
assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9]
reg [63:0] time_0; // @[CLINT.scala:73:23]
wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19]
wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38]
wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38]
reg [63:0] timecmp_0; // @[CLINT.scala:77:41]
wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19]
reg ipi_0; // @[CLINT.scala:78:41]
assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37]
wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24]
assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37]
assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43]
assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43]
wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}]
wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24]
wire [7:0] newBytes_0; // @[RegField.scala:152:31]
wire [7:0] newBytes_1; // @[RegField.scala:152:31]
wire [7:0] newBytes_2; // @[RegField.scala:152:31]
wire [7:0] newBytes_3; // @[RegField.scala:152:31]
wire [7:0] newBytes_4; // @[RegField.scala:152:31]
wire [7:0] newBytes_5; // @[RegField.scala:152:31]
wire [7:0] newBytes_6; // @[RegField.scala:152:31]
wire [7:0] newBytes_7; // @[RegField.scala:152:31]
wire out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire valids_0; // @[RegField.scala:153:29]
wire valids_1; // @[RegField.scala:153:29]
wire valids_2; // @[RegField.scala:153:29]
wire valids_3; // @[RegField.scala:153:29]
wire valids_4; // @[RegField.scala:153:29]
wire valids_5; // @[RegField.scala:153:29]
wire valids_6; // @[RegField.scala:153:29]
wire valids_7; // @[RegField.scala:153:29]
wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52]
wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52]
wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52]
wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52]
wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52]
wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52]
wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52]
wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}]
wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24]
wire [7:0] newBytes_1_0; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_1; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_2; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_3; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_4; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_5; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_6; // @[RegField.scala:152:31]
wire [7:0] newBytes_1_7; // @[RegField.scala:152:31]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire valids_1_0; // @[RegField.scala:153:29]
wire valids_1_1; // @[RegField.scala:153:29]
wire valids_1_2; // @[RegField.scala:153:29]
wire valids_1_3; // @[RegField.scala:153:29]
wire valids_1_4; // @[RegField.scala:153:29]
wire valids_1_5; // @[RegField.scala:153:29]
wire valids_1_6; // @[RegField.scala:153:29]
wire valids_1_7; // @[RegField.scala:153:29]
wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52]
wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52]
wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52]
wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52]
wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52]
wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52]
wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24]
wire [12:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_17; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_17; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire out_roready_16; // @[RegisterRouter.scala:87:24]
wire out_roready_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire out_woready_16; // @[RegisterRouter.scala:87:24]
wire out_woready_17; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24]
wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24]
assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24]
assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24]
wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24]
wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24]
wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24]
assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24]
assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24]
wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24]
wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24]
wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24]
wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24]
wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24]
assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24]
assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24]
assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24]
wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[CLINT.scala:65:9]
if (reset) begin // @[CLINT.scala:65:9]
time_0 <= 64'h0; // @[CLINT.scala:73:23]
ipi_0 <= 1'h0; // @[CLINT.scala:78:41]
end
else begin // @[CLINT.scala:65:9]
if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27]
time_0 <= _time_T_2; // @[RegField.scala:154:52]
else if (io_rtcTick_0) // @[CLINT.scala:65:9]
time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38]
if (out_f_woready) // @[RegisterRouter.scala:87:24]
ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24]
end
if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27]
timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52]
always @(posedge)
TLMonitor_56 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9]
assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9]
assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File fetch-target-queue.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Fetch Target Queue (FTQ)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.
//
// TODO:
// * reduce port counts.
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util.{Str}
import boom.v3.common._
import boom.v3.exu._
import boom.v3.util._
/**
* FTQ Parameters used in configurations
*
* @param nEntries # of entries in the FTQ
*/
case class FtqParameters(
nEntries: Int = 16
)
/**
* Bundle to add to the FTQ RAM and to be used as the pass in IO
*/
class FTQBundle(implicit p: Parameters) extends BoomBundle
with HasBoomFrontendParameters
{
// // TODO compress out high-order bits
// val fetch_pc = UInt(vaddrBitsExtended.W)
// IDX of instruction that was predicted taken, if any
val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))
// Was the CFI in this bundle found to be taken? or not
val cfi_taken = Bool()
// Was this CFI mispredicted by the branch prediction pipeline?
val cfi_mispredicted = Bool()
// What type of CFI was taken out of this bundle
val cfi_type = UInt(CFI_SZ.W)
// mask of branches which were visible in this fetch bundle
val br_mask = UInt(fetchWidth.W)
// This CFI is likely a CALL
val cfi_is_call = Bool()
// This CFI is likely a RET
val cfi_is_ret = Bool()
// Is the NPC after the CFI +4 or +2
val cfi_npc_plus4 = Bool()
// What was the top of the RAS that this bundle saw?
val ras_top = UInt(vaddrBitsExtended.W)
val ras_idx = UInt(log2Ceil(nRasEntries).W)
// Which bank did this start from?
val start_bank = UInt(1.W)
// // Metadata for the branch predictor
// val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))
}
/**
* IO to provide a port for a FunctionalUnit to get the PC of an instruction.
* And for JALRs, the PC of the next instruction.
*/
class GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))
val entry = Output(new FTQBundle)
val ghist = Output(new GlobalHistory)
val pc = Output(UInt(vaddrBitsExtended.W))
val com_pc = Output(UInt(vaddrBitsExtended.W))
// the next_pc may not be valid (stalled or still being fetched)
val next_val = Output(Bool())
val next_pc = Output(UInt(vaddrBitsExtended.W))
}
/**
* Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the
* processor.
*
* @param num_entries # of entries in the FTQ
*/
class FetchTargetQueue(implicit p: Parameters) extends BoomModule
with HasBoomCoreParameters
with HasBoomFrontendParameters
{
val num_entries = ftqSz
private val idx_sz = log2Ceil(num_entries)
val io = IO(new BoomBundle {
// Enqueue one entry for every fetch cycle.
val enq = Flipped(Decoupled(new FetchBundle()))
// Pass to FetchBuffer (newly fetched instructions).
val enq_idx = Output(UInt(idx_sz.W))
// ROB tells us the youngest committed ftq_idx to remove from FTQ.
val deq = Flipped(Valid(UInt(idx_sz.W)))
// Give PC info to BranchUnit.
val get_ftq_pc = Vec(2, new GetPCFromFtqIO())
// Used to regenerate PC for trace port stuff in FireSim
// Don't tape this out, this blows up the FTQ
val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))
val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))
val redirect = Input(Valid(UInt(idx_sz.W)))
val brupdate = Input(new BrUpdateInfo)
val bpdupdate = Output(Valid(new BranchPredictionUpdate))
val ras_update = Output(Bool())
val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))
val ras_update_pc = Output(UInt(vaddrBitsExtended.W))
})
val bpd_ptr = RegInit(0.U(idx_sz.W))
val deq_ptr = RegInit(0.U(idx_sz.W))
val enq_ptr = RegInit(1.U(idx_sz.W))
val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||
(WrapInc(enq_ptr, num_entries) === bpd_ptr))
val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))
val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))
val ram = Reg(Vec(num_entries, new FTQBundle))
val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }
val lhist = if (useLHist) {
Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))
} else {
None
}
val do_enq = io.enq.fire
// This register lets us initialize the ghist to 0
val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))
val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))
val prev_pc = RegInit(0.U(vaddrBitsExtended.W))
when (do_enq) {
pcs(enq_ptr) := io.enq.bits.pc
val new_entry = Wire(new FTQBundle)
new_entry.cfi_idx := io.enq.bits.cfi_idx
// Initially, if we see a CFI, it is assumed to be taken.
// Branch resolutions may change this
new_entry.cfi_taken := io.enq.bits.cfi_idx.valid
new_entry.cfi_mispredicted := false.B
new_entry.cfi_type := io.enq.bits.cfi_type
new_entry.cfi_is_call := io.enq.bits.cfi_is_call
new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret
new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4
new_entry.ras_top := io.enq.bits.ras_top
new_entry.ras_idx := io.enq.bits.ghist.ras_idx
new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask
new_entry.start_bank := bank(io.enq.bits.pc)
val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,
io.enq.bits.ghist,
prev_ghist.update(
prev_entry.br_mask,
prev_entry.cfi_taken,
prev_entry.br_mask(prev_entry.cfi_idx.bits),
prev_entry.cfi_idx.bits,
prev_entry.cfi_idx.valid,
prev_pc,
prev_entry.cfi_is_call,
prev_entry.cfi_is_ret
)
)
lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))
ghist.map( g => g.write(enq_ptr, new_ghist))
meta.write(enq_ptr, io.enq.bits.bpd_meta)
ram(enq_ptr) := new_entry
prev_pc := io.enq.bits.pc
prev_entry := new_entry
prev_ghist := new_ghist
enq_ptr := WrapInc(enq_ptr, num_entries)
}
io.enq_idx := enq_ptr
io.bpdupdate.valid := false.B
io.bpdupdate.bits := DontCare
when (io.deq.valid) {
deq_ptr := io.deq.bits
}
// This register avoids a spurious bpd update on the first fetch packet
val first_empty = RegInit(true.B)
// We can update the branch predictors when we know the target of the
// CFI in this fetch bundle
val ras_update = WireInit(false.B)
val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))
val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))
io.ras_update := RegNext(ras_update)
io.ras_update_pc := RegNext(ras_update_pc)
io.ras_update_idx := RegNext(ras_update_idx)
val bpd_update_mispredict = RegInit(false.B)
val bpd_update_repair = RegInit(false.B)
val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))
val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))
val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,
Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))
val bpd_entry = RegNext(ram(bpd_idx))
val bpd_ghist = ghist(0).read(bpd_idx, true.B)
val bpd_lhist = if (useLHist) {
lhist.get.read(bpd_idx, true.B)
} else {
VecInit(Seq.fill(nBanks) { 0.U })
}
val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs
val bpd_pc = RegNext(pcs(bpd_idx))
val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))
when (io.redirect.valid) {
bpd_update_mispredict := false.B
bpd_update_repair := false.B
} .elsewhen (RegNext(io.brupdate.b2.mispredict)) {
bpd_update_mispredict := true.B
bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)
bpd_end_idx := RegNext(enq_ptr)
} .elsewhen (bpd_update_mispredict) {
bpd_update_mispredict := false.B
bpd_update_repair := true.B
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {
bpd_repair_pc := bpd_pc
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
} .elsewhen (bpd_update_repair) {
bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)
when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||
bpd_pc === bpd_repair_pc) {
bpd_update_repair := false.B
}
}
val do_commit_update = (!bpd_update_mispredict &&
!bpd_update_repair &&
bpd_ptr =/= deq_ptr &&
enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&
!io.brupdate.b2.mispredict &&
!io.redirect.valid && !RegNext(io.redirect.valid))
val do_mispredict_update = bpd_update_mispredict
val do_repair_update = bpd_update_repair
when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {
val cfi_idx = bpd_entry.cfi_idx.bits
val valid_repair = bpd_pc =/= bpd_repair_pc
io.bpdupdate.valid := (!first_empty &&
(bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&
!(RegNext(do_repair_update) && !valid_repair))
io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)
io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)
io.bpdupdate.bits.pc := bpd_pc
io.bpdupdate.bits.btb_mispredicts := 0.U
io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,
MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)
io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx
io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted
io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken
io.bpdupdate.bits.target := bpd_target
io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)
io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR
io.bpdupdate.bits.ghist := bpd_ghist
io.bpdupdate.bits.lhist := bpd_lhist
io.bpdupdate.bits.meta := bpd_meta
first_empty := false.B
}
when (do_commit_update) {
bpd_ptr := WrapInc(bpd_ptr, num_entries)
}
io.enq.ready := RegNext(!full || do_commit_update)
val redirect_idx = io.redirect.bits
val redirect_entry = ram(redirect_idx)
val redirect_new_entry = WireInit(redirect_entry)
when (io.redirect.valid) {
enq_ptr := WrapInc(io.redirect.bits, num_entries)
when (io.brupdate.b2.mispredict) {
val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^
Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)
redirect_new_entry.cfi_idx.valid := true.B
redirect_new_entry.cfi_idx.bits := new_cfi_idx
redirect_new_entry.cfi_mispredicted := true.B
redirect_new_entry.cfi_taken := io.brupdate.b2.taken
redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx
redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx
}
ras_update := true.B
ras_update_pc := redirect_entry.ras_top
ras_update_idx := redirect_entry.ras_idx
} .elsewhen (RegNext(io.redirect.valid)) {
prev_entry := RegNext(redirect_new_entry)
prev_ghist := bpd_ghist
prev_pc := bpd_pc
ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)
}
//-------------------------------------------------------------
// **** Core Read PCs ****
//-------------------------------------------------------------
for (i <- 0 until 2) {
val idx = io.get_ftq_pc(i).ftq_idx
val next_idx = WrapInc(idx, num_entries)
val next_is_enq = (next_idx === enq_ptr) && io.enq.fire
val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))
val get_entry = ram(idx)
val next_entry = ram(next_idx)
io.get_ftq_pc(i).entry := RegNext(get_entry)
if (i == 1)
io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)
else
io.get_ftq_pc(i).ghist := DontCare
io.get_ftq_pc(i).pc := RegNext(pcs(idx))
io.get_ftq_pc(i).next_pc := RegNext(next_pc)
io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)
io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))
}
for (w <- 0 until coreWidth) {
io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))
}
}
| module ghist_1_0( // @[fetch-target-queue.scala:144:43]
input [3:0] R0_addr,
input R0_clk,
output [71:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [71:0] W0_data
);
ghist_0_ext ghist_0_ext ( // @[fetch-target-queue.scala:144:43]
.R0_addr (R0_addr),
.R0_en (1'h1), // @[fetch-target-queue.scala:144:43]
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[fetch-target-queue.scala:144:43]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_33( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_in_valid // @[IngressUnit.scala:24:14]
); |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_29( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_285 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_64( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_64 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_8( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_37 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
| module TLDFromNoC_1( // @[TilelinkAdapters.scala:185:7]
input clock, // @[TilelinkAdapters.scala:185:7]
input reset, // @[TilelinkAdapters.scala:185:7]
input io_protocol_ready, // @[TilelinkAdapters.scala:56:14]
output io_protocol_valid, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14]
output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14]
output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14]
output [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14]
output [5:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14]
output [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14]
input [128:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
reg [22:0] const_reg; // @[TilelinkAdapters.scala:69:22]
wire [22:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[22:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7]
if (reset) // @[TilelinkAdapters.scala:185:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7]
else // @[TilelinkAdapters.scala:185:7]
is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35]
if (_GEN_0) // @[TilelinkAdapters.scala:84:22]
const_reg <= io_flit_bits_payload[22:0]; // @[TilelinkAdapters.scala:56:14, :69:22]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File HasTiles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
import freechips.rocketchip.tilelink.TLWidthWidget
import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
import freechips.rocketchip.rocket.TracedInstruction
import freechips.rocketchip.util.TraceCoreInterface
import scala.collection.immutable.SortedMap
/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
/** List of HierarchicalLocations which might contain a Tile */
case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil)
/** For determining static tile id */
case object NumTiles extends Field[Int](0)
/** Whether to add timing-closure registers along the path of the hart id
* as it propagates through the subsystem and into the tile.
*
* These are typically only desirable when a dynamically programmable prefix is being combined
* with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]].
*/
case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false)
/** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block,
* and if so, what their width should be.
*/
case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None)
/** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block.
*
* Unlike the hart ids, the reset vector width is determined by the sinks within the tiles,
* based on the size of the address map visible to the tiles.
*/
case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
/** These are sources of "constants" that are driven into the tile.
*
* While they are not expected to change dyanmically while the tile is executing code,
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
* Each "prefix" input is actually the same full width as the outer hart id; the expected usage
* is that each prefix source would set only some non-overlapping portion of the bits to non-zero values.
* This node orReduces them, and further combines the reduction with the static ids assigned to each tile,
* producing a unique, dynamic hart id for each tile.
*
* If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered.
*
* The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into
* the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous.
*/
val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i =>
val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup
if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y
},
default = Some(() => 0.U(p(MaxHartIdBits).W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs
/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below
)
/** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids.
*
* Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile.
*/
val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match {
case Some(w) => (0 until nTotalTiles).map { i =>
val hartIdSource = BundleBridgeSource(() => UInt(w.W))
tileHartIdNodes(i) := hartIdSource
hartIdSource
}
case None => {
(0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode }
Nil
}
}
/** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors.
*
* Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile.
*/
val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match {
case true => (0 until nTotalTiles).map { i =>
val resetVectorSource = BundleBridgeSource[UInt]()
tileResetVectorNodes(i) := resetVectorSource
resetVectorSource
}
case false => {
(0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode }
Nil
}
}
}
/** These are sinks of notifications that are driven out from the tile.
*
* They need to be instantiated before tiles are attached to the subsystem containing them.
*/
trait HasTileNotificationSinks { this: LazyModule =>
val tileHaltXbarNode = IntXbar()
val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
tileHaltSinkNode := tileHaltXbarNode
val tileWFIXbarNode = IntXbar()
val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
tileWFISinkNode := tileWFIXbarNode
val tileCeaseXbarNode = IntXbar()
val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
tileCeaseSinkNode := tileCeaseXbarNode
}
/** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
*
* Sub-classes of this trait can optionally override the individual connect functions in order to specialize
* their attachment behaviors, but most use cases should be be handled simply by changing the implementation
* of the injectNode functions in crossingParams.
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: HierarchicalElementCrossingParamsLike
/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
})
tile_prci_domain
}
/** A default set of connections that need to occur for most tile types */
def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC(domain, context)
connectOutputNotifications(domain, context)
connectInputConstants(domain, context)
connectTrace(domain, context)
}
/** Connect the port where the tile is the master to a TileLink interconnect. */
def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
dataBus.coupleFrom(tileParams.baseName) { bus =>
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
}
}
/** Connect the port where the tile is the slave to a TileLink interconnect. */
def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
DisableMonitors { implicit p =>
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
controlBus.coupleTo(tileParams.baseName) { bus =>
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
}
}
}
/** Connect the various interrupts sent to and and raised by the tile. */
def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from tile.intInwardNode inside the tile. For this reason,
// we stub out missing interrupts with constant sources here.
// 1. Debug interrupt is definitely asynchronous in all cases.
domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } :=
context.debugNodes(domain.element.tileId)
// 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively,
// so might need to be synchronized depending on the Tile's crossing type.
// From CLINT: "msip" and "mtip"
context.msipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.msipNodes(domain.element.tileId)
}
// From PLIC: "meip"
context.meipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.meipNodes(domain.element.tileId)
}
// From PLIC: "seip" (only if supervisor mode is enabled)
if (domain.element.tileParams.core.hasSupervisorMode) {
context.seipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.seipNodes(domain.element.tileId)
}
}
// 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
// (they are connected to domain.element.intInwardNode in a seperate trait)
// 4. Interrupts coming out of the tile are sent to the PLIC,
// so might need to be synchronized depending on the Tile's crossing type.
context.tileToPlicNodes.get(domain.element.tileId).foreach { node =>
FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out =>
context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) }
}}
}
// 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock.
domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId))
}
/** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */
def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
domain {
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode)
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode)
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode)
}
// TODO should context be forced to have a trace sink connected here?
// for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally
}
/** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */
def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId)
domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId)
tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ }
}
/** Connect power/reset/clock resources. */
def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
(crossingParams.crossingType match {
case _: SynchronousCrossing | _: CreditedCrossing =>
if (crossingParams.forceSeparateClockReset) {
domain.clockNode := tlBusToGetClockDriverFrom.clockNode
} else {
domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
}
case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
case _: AsynchronousCrossing => {
val tileClockGroup = ClockGroup()
tileClockGroup := context.allClockGroupsNode
domain.clockNode := tileClockGroup
}
})
domain {
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
}
}
/** Function to handle all trace crossings when tile is instantiated inside domains */
def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle](
resetCrossingType = crossingParams.resetCrossingType)
context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode
val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface](
resetCrossingType = crossingParams.resetCrossingType)
context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode
}
}
case class CloneTileAttachParams(
sourceTileId: Int,
cloneParams: CanAttachTile
) extends CanAttachTile {
type TileType = cloneParams.TileType
type TileContextType = cloneParams.TileContextType
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
},
instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]]
)
tile_prci_domain
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TilePRCIDomain( // @[ClockDomain.scala:14:9]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_element_reset_domain_shuttle_tile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _intsink_3_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_2_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_1_auto_out_0; // @[Crossing.scala:109:29]
wire _intsink_1_auto_out_1; // @[Crossing.scala:109:29]
wire _intsink_auto_out_0; // @[Crossing.scala:86:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_b_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_b_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_b_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_b_bits_size; // @[Buffer.scala:75:28]
wire [5:0] _buffer_auto_in_b_bits_source; // @[Buffer.scala:75:28]
wire [31:0] _buffer_auto_in_b_bits_address; // @[Buffer.scala:75:28]
wire [15:0] _buffer_auto_in_b_bits_mask; // @[Buffer.scala:75:28]
wire [127:0] _buffer_auto_in_b_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_in_c_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [5:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [127:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_in_e_ready; // @[Buffer.scala:75:28]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_a_valid; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param; // @[HasTiles.scala:164:59]
wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size; // @[HasTiles.scala:164:59]
wire [5:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source; // @[HasTiles.scala:164:59]
wire [31:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address; // @[HasTiles.scala:164:59]
wire [15:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask; // @[HasTiles.scala:164:59]
wire [127:0] _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_b_ready; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_c_valid; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode; // @[HasTiles.scala:164:59]
wire [2:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param; // @[HasTiles.scala:164:59]
wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size; // @[HasTiles.scala:164:59]
wire [5:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source; // @[HasTiles.scala:164:59]
wire [31:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address; // @[HasTiles.scala:164:59]
wire [127:0] _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_d_ready; // @[HasTiles.scala:164:59]
wire _element_reset_domain_shuttle_tile_auto_buffer_out_e_valid; // @[HasTiles.scala:164:59]
wire [3:0] _element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink; // @[HasTiles.scala:164:59]
ShuttleTile element_reset_domain_shuttle_tile ( // @[HasTiles.scala:164:59]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_buffer_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_a_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_b_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_b_ready),
.auto_buffer_out_b_valid (_buffer_auto_in_b_valid), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_opcode (_buffer_auto_in_b_bits_opcode), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_param (_buffer_auto_in_b_bits_param), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_size (_buffer_auto_in_b_bits_size), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_source (_buffer_auto_in_b_bits_source), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_address (_buffer_auto_in_b_bits_address), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_mask (_buffer_auto_in_b_bits_mask), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_data (_buffer_auto_in_b_bits_data), // @[Buffer.scala:75:28]
.auto_buffer_out_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt), // @[Buffer.scala:75:28]
.auto_buffer_out_c_ready (_buffer_auto_in_c_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_c_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data),
.auto_buffer_out_c_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt),
.auto_buffer_out_d_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_buffer_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28]
.auto_buffer_out_e_ready (_buffer_auto_in_e_ready), // @[Buffer.scala:75:28]
.auto_buffer_out_e_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (_element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink),
.auto_int_local_in_3_0 (_intsink_3_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_2_0 (_intsink_2_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_1_0 (_intsink_1_auto_out_0), // @[Crossing.scala:109:29]
.auto_int_local_in_1_1 (_intsink_1_auto_out_1), // @[Crossing.scala:109:29]
.auto_int_local_in_0_0 (_intsink_auto_out_0), // @[Crossing.scala:86:29]
.auto_hartid_in (auto_element_reset_domain_shuttle_tile_hartid_in)
); // @[HasTiles.scala:164:59]
TLBuffer_a32d128s6k4z4c_2 buffer ( // @[Buffer.scala:75:28]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_a_valid), // @[HasTiles.scala:164:59]
.auto_in_a_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_opcode), // @[HasTiles.scala:164:59]
.auto_in_a_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_param), // @[HasTiles.scala:164:59]
.auto_in_a_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_size), // @[HasTiles.scala:164:59]
.auto_in_a_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_source), // @[HasTiles.scala:164:59]
.auto_in_a_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_address), // @[HasTiles.scala:164:59]
.auto_in_a_bits_mask (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_mask), // @[HasTiles.scala:164:59]
.auto_in_a_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_data), // @[HasTiles.scala:164:59]
.auto_in_a_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_a_bits_corrupt), // @[HasTiles.scala:164:59]
.auto_in_b_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_b_ready), // @[HasTiles.scala:164:59]
.auto_in_b_valid (_buffer_auto_in_b_valid),
.auto_in_b_bits_opcode (_buffer_auto_in_b_bits_opcode),
.auto_in_b_bits_param (_buffer_auto_in_b_bits_param),
.auto_in_b_bits_size (_buffer_auto_in_b_bits_size),
.auto_in_b_bits_source (_buffer_auto_in_b_bits_source),
.auto_in_b_bits_address (_buffer_auto_in_b_bits_address),
.auto_in_b_bits_mask (_buffer_auto_in_b_bits_mask),
.auto_in_b_bits_data (_buffer_auto_in_b_bits_data),
.auto_in_b_bits_corrupt (_buffer_auto_in_b_bits_corrupt),
.auto_in_c_ready (_buffer_auto_in_c_ready),
.auto_in_c_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_c_valid), // @[HasTiles.scala:164:59]
.auto_in_c_bits_opcode (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_opcode), // @[HasTiles.scala:164:59]
.auto_in_c_bits_param (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_param), // @[HasTiles.scala:164:59]
.auto_in_c_bits_size (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_size), // @[HasTiles.scala:164:59]
.auto_in_c_bits_source (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_source), // @[HasTiles.scala:164:59]
.auto_in_c_bits_address (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_address), // @[HasTiles.scala:164:59]
.auto_in_c_bits_data (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_data), // @[HasTiles.scala:164:59]
.auto_in_c_bits_corrupt (_element_reset_domain_shuttle_tile_auto_buffer_out_c_bits_corrupt), // @[HasTiles.scala:164:59]
.auto_in_d_ready (_element_reset_domain_shuttle_tile_auto_buffer_out_d_ready), // @[HasTiles.scala:164:59]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_in_e_ready (_buffer_auto_in_e_ready),
.auto_in_e_valid (_element_reset_domain_shuttle_tile_auto_buffer_out_e_valid), // @[HasTiles.scala:164:59]
.auto_in_e_bits_sink (_element_reset_domain_shuttle_tile_auto_buffer_out_e_bits_sink), // @[HasTiles.scala:164:59]
.auto_out_a_ready (auto_tl_master_clock_xing_out_a_ready),
.auto_out_a_valid (auto_tl_master_clock_xing_out_a_valid),
.auto_out_a_bits_opcode (auto_tl_master_clock_xing_out_a_bits_opcode),
.auto_out_a_bits_param (auto_tl_master_clock_xing_out_a_bits_param),
.auto_out_a_bits_size (auto_tl_master_clock_xing_out_a_bits_size),
.auto_out_a_bits_source (auto_tl_master_clock_xing_out_a_bits_source),
.auto_out_a_bits_address (auto_tl_master_clock_xing_out_a_bits_address),
.auto_out_a_bits_mask (auto_tl_master_clock_xing_out_a_bits_mask),
.auto_out_a_bits_data (auto_tl_master_clock_xing_out_a_bits_data),
.auto_out_a_bits_corrupt (auto_tl_master_clock_xing_out_a_bits_corrupt),
.auto_out_b_ready (auto_tl_master_clock_xing_out_b_ready),
.auto_out_b_valid (auto_tl_master_clock_xing_out_b_valid),
.auto_out_b_bits_param (auto_tl_master_clock_xing_out_b_bits_param),
.auto_out_b_bits_address (auto_tl_master_clock_xing_out_b_bits_address),
.auto_out_c_ready (auto_tl_master_clock_xing_out_c_ready),
.auto_out_c_valid (auto_tl_master_clock_xing_out_c_valid),
.auto_out_c_bits_opcode (auto_tl_master_clock_xing_out_c_bits_opcode),
.auto_out_c_bits_param (auto_tl_master_clock_xing_out_c_bits_param),
.auto_out_c_bits_size (auto_tl_master_clock_xing_out_c_bits_size),
.auto_out_c_bits_source (auto_tl_master_clock_xing_out_c_bits_source),
.auto_out_c_bits_address (auto_tl_master_clock_xing_out_c_bits_address),
.auto_out_c_bits_data (auto_tl_master_clock_xing_out_c_bits_data),
.auto_out_c_bits_corrupt (auto_tl_master_clock_xing_out_c_bits_corrupt),
.auto_out_d_ready (auto_tl_master_clock_xing_out_d_ready),
.auto_out_d_valid (auto_tl_master_clock_xing_out_d_valid),
.auto_out_d_bits_opcode (auto_tl_master_clock_xing_out_d_bits_opcode),
.auto_out_d_bits_param (auto_tl_master_clock_xing_out_d_bits_param),
.auto_out_d_bits_size (auto_tl_master_clock_xing_out_d_bits_size),
.auto_out_d_bits_source (auto_tl_master_clock_xing_out_d_bits_source),
.auto_out_d_bits_sink (auto_tl_master_clock_xing_out_d_bits_sink),
.auto_out_d_bits_denied (auto_tl_master_clock_xing_out_d_bits_denied),
.auto_out_d_bits_data (auto_tl_master_clock_xing_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_tl_master_clock_xing_out_d_bits_corrupt),
.auto_out_e_valid (auto_tl_master_clock_xing_out_e_valid),
.auto_out_e_bits_sink (auto_tl_master_clock_xing_out_e_bits_sink)
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29]
.clock (auto_tap_clock_in_clock),
.auto_in_sync_0 (auto_intsink_in_sync_0),
.auto_out_0 (_intsink_auto_out_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_0_sync_0),
.auto_in_sync_1 (auto_int_in_clock_xing_in_0_sync_1),
.auto_out_0 (_intsink_1_auto_out_0),
.auto_out_1 (_intsink_1_auto_out_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_1_sync_0),
.auto_out_0 (_intsink_2_auto_out_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (auto_int_in_clock_xing_in_2_sync_0),
.auto_out_0 (_intsink_3_auto_out_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (1'h0), // @[Buffer.scala:75:28]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (1'h0), // @[Buffer.scala:75:28]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_2 ( // @[Crossing.scala:29:31]
.clock (auto_tap_clock_in_clock),
.reset (auto_tap_clock_in_reset),
.auto_in_0 (1'h0), // @[Buffer.scala:75:28]
.auto_out_sync_0 (/* unused */)
); // @[Crossing.scala:29:31]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File StoreSequencer.scala:
package saturn.backend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import saturn.common._
class StoreSequencer(implicit p: Parameters) extends PipeSequencer(new StoreDataMicroOp)(p) {
def accepts(inst: VectorIssueInst) = inst.vmu && inst.opcode(5)
val valid = RegInit(false.B)
val inst = Reg(new VectorIssueInst)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val sidx = Reg(UInt(3.W))
val rvd_mask = Reg(UInt(egsTotal.W))
val rvm_mask = Reg(UInt(egsPerVReg.W))
val sub_dlen = Reg(UInt(2.W))
val head = Reg(Bool())
val renvm = !inst.vm && inst.mop === mopUnit
val next_eidx = get_next_eidx(inst.vconfig.vl, eidx, inst.mem_elem_size, sub_dlen, false.B, false.B)
val tail = next_eidx === inst.vconfig.vl && sidx === inst.seg_nf
io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall
when (io.dis.fire) {
val iss_inst = io.dis.bits
valid := true.B
inst := iss_inst
eidx := iss_inst.vstart
sidx := 0.U
val rvd_arch_mask = Wire(Vec(32, Bool()))
for (i <- 0 until 32) {
val group = i.U >> iss_inst.emul
val rd_group = iss_inst.rd >> iss_inst.emul
rvd_arch_mask(i) := group >= rd_group && group <= (rd_group + iss_inst.nf)
}
rvd_mask := FillInterleaved(egsPerVReg, rvd_arch_mask.asUInt)
rvm_mask := Mux(!iss_inst.vm, ~(0.U(egsPerVReg.W)), 0.U)
sub_dlen := Mux(iss_inst.seg_nf =/= 0.U && (dLenOffBits.U > (3.U +& iss_inst.mem_elem_size)),
dLenOffBits.U - 3.U - iss_inst.mem_elem_size,
0.U)
head := true.B
} .elsewhen (io.iss.fire) {
valid := !tail
head := false.B
}
io.vat := inst.vat
io.seq_hazard.valid := valid
io.seq_hazard.bits.rintent := hazardMultiply(rvd_mask | rvm_mask)
io.seq_hazard.bits.wintent := 0.U
io.seq_hazard.bits.vat := inst.vat
val vd_read_oh = UIntToOH(io.rvd.req.bits.eg)
val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U)
val raw_hazard = ((vm_read_oh | vd_read_oh) & io.older_writes) =/= 0.U
val data_hazard = raw_hazard
val oldest = inst.vat === io.vat_head
io.rvd.req.valid := valid && io.iss.ready
io.rvd.req.bits.eg := getEgId(inst.rd + (sidx << inst.emul), eidx, inst.mem_elem_size, false.B)
io.rvd.req.bits.oldest := oldest
io.rvm.req.valid := valid && renvm && io.iss.ready
io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B)
io.rvm.req.bits.oldest := oldest
io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && io.rvd.req.ready
io.iss.bits.stdata := io.rvd.resp
val head_mask = get_head_mask(~(0.U(dLenB.W)), eidx , inst.mem_elem_size)
val tail_mask = get_tail_mask(~(0.U(dLenB.W)), next_eidx, inst.mem_elem_size)
val vm_mask = Mux(!renvm, ~(0.U(dLenB.W)), get_vm_mask(io.rvm.resp, eidx, inst.mem_elem_size))
io.iss.bits.stmask := vm_mask
io.iss.bits.debug_id := inst.debug_id
io.iss.bits.tail := tail
io.iss.bits.vat := inst.vat
when (io.iss.fire && !tail) {
when (next_is_new_eg(eidx, next_eidx, inst.mem_elem_size, false.B) && vParams.enableChaining.B) {
rvd_mask := rvd_mask & ~UIntToOH(io.rvd.req.bits.eg)
}
when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) {
rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg)
}
when (sidx === inst.seg_nf) {
sidx := 0.U
eidx := next_eidx
} .otherwise {
sidx := sidx + 1.U
}
}
io.busy := valid
io.head := head
}
File PipeSequencer.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile.{CoreModule}
import saturn.common._
abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val dis = Flipped(Decoupled(new BackendIssueInst))
val dis_stall = Input(Bool()) // used to disable OOO
val seq_hazard = Output(Valid(new SequencerHazard))
val vat = Output(UInt(vParams.vatSz.W))
val vat_head = Input(UInt(vParams.vatSz.W))
val older_writes = Input(UInt(egsTotal.W))
val older_reads = Input(UInt(egsTotal.W))
val busy = Output(Bool())
val head = Output(Bool())
val rvs1 = new VectorReadIO
val rvs2 = new VectorReadIO
val rvd = new VectorReadIO
val rvm = new VectorReadIO
val perm = new Bundle {
val req = Decoupled(new CompactorReq(dLenB))
val data = Input(UInt(dLen.W))
}
val iss = Decoupled(issType)
val acc = Input(Valid(new VectorWrite(dLen)))
})
def accepts(inst: VectorIssueInst): Bool
def min(a: UInt, b: UInt) = Mux(a > b, b, a)
def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0)
def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0)
def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0))
def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = {
val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W)
val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0)
val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0)
Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) })
}
def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = {
val next = Wire(UInt((1+log2Ceil(maxVLMax)).W))
next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask,
eidx +& dLen.U,
(((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen))
))
min(vl, next)
}
def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = {
val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew)
(next_eidx >> offset) =/= (eidx >> offset)
}
io.rvs1.req.valid := false.B
io.rvs1.req.bits := DontCare
io.rvs2.req.valid := false.B
io.rvs2.req.bits := DontCare
io.rvd.req.valid := false.B
io.rvd.req.bits := DontCare
io.rvm.req.valid := false.B
io.rvm.req.bits := DontCare
io.perm.req.valid := false.B
io.perm.req.bits := DontCare
}
| module StoreSequencer( // @[StoreSequencer.scala:8:7]
input clock, // @[StoreSequencer.scala:8:7]
input reset, // @[StoreSequencer.scala:8:7]
output io_dis_ready, // @[PipeSequencer.scala:11:14]
input io_dis_valid, // @[PipeSequencer.scala:11:14]
input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14]
input [7:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14]
input [6:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14]
input [4:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14]
input [15:0] io_dis_bits_debug_id, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_mop, // @[PipeSequencer.scala:11:14]
output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14]
output [31:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14]
output [4:0] io_vat, // @[PipeSequencer.scala:11:14]
input [4:0] io_vat_head, // @[PipeSequencer.scala:11:14]
input [31:0] io_older_writes, // @[PipeSequencer.scala:11:14]
output io_busy, // @[PipeSequencer.scala:11:14]
input io_rvd_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvd_req_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_rvd_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvd_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [127:0] io_rvd_resp, // @[PipeSequencer.scala:11:14]
input io_rvm_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvm_req_valid, // @[PipeSequencer.scala:11:14]
output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [127:0] io_rvm_resp, // @[PipeSequencer.scala:11:14]
input io_iss_ready, // @[PipeSequencer.scala:11:14]
output io_iss_valid, // @[PipeSequencer.scala:11:14]
output [127:0] io_iss_bits_stdata, // @[PipeSequencer.scala:11:14]
output [15:0] io_iss_bits_stmask, // @[PipeSequencer.scala:11:14]
output [15:0] io_iss_bits_debug_id, // @[PipeSequencer.scala:11:14]
output io_iss_bits_tail, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_vat // @[PipeSequencer.scala:11:14]
);
wire io_iss_valid_0; // @[StoreSequencer.scala:71:{25,41,73}]
wire [4:0] _io_rvd_req_bits_eg_T_7; // @[Parameters.scala:344:10]
reg valid; // @[StoreSequencer.scala:11:25]
reg [31:0] inst_bits; // @[StoreSequencer.scala:12:21]
reg [7:0] inst_vconfig_vl; // @[StoreSequencer.scala:12:21]
reg [2:0] inst_vconfig_vtype_vsew; // @[StoreSequencer.scala:12:21]
reg [4:0] inst_vat; // @[StoreSequencer.scala:12:21]
reg [1:0] inst_emul; // @[StoreSequencer.scala:12:21]
reg [15:0] inst_debug_id; // @[StoreSequencer.scala:12:21]
reg [1:0] inst_mop; // @[StoreSequencer.scala:12:21]
reg [6:0] eidx; // @[StoreSequencer.scala:13:21]
reg [2:0] sidx; // @[StoreSequencer.scala:14:21]
reg [31:0] rvd_mask; // @[StoreSequencer.scala:15:21]
reg rvm_mask; // @[StoreSequencer.scala:16:21]
reg [1:0] sub_dlen; // @[StoreSequencer.scala:17:21]
wire renvm = ~(inst_bits[25]) & inst_mop == 2'h0; // @[Bundles.scala:60:16]
wire [2:0] _GEN = {1'h0, inst_bits[13:12]}; // @[Bundles.scala:59:{26,59}]
wire [2:0] _next_eidx_next_T_8 = 3'h4 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Bundles.scala:59:{26,30}]
wire [2:0] _GEN_0 = {1'h0, sub_dlen}; // @[StoreSequencer.scala:17:21]
wire [14:0] _next_eidx_next_T_14 = {7'h0, {1'h0, eidx >> _next_eidx_next_T_8 - _GEN_0} + 8'h1} << _next_eidx_next_T_8 - _GEN_0; // @[StoreSequencer.scala:13:21]
wire [7:0] next_eidx = inst_vconfig_vl > _next_eidx_next_T_14[7:0] ? _next_eidx_next_T_14[7:0] : inst_vconfig_vl; // @[StoreSequencer.scala:12:21]
wire tail = next_eidx == inst_vconfig_vl & sidx == (~(|(inst_bits[27:26])) & inst_bits[24:20] == 5'h8 ? 3'h0 : inst_bits[31:29]); // @[Bundles.scala:61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35]
wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35]
wire [31:0] vd_read_oh = 32'h1 << _io_rvd_req_bits_eg_T_7; // @[OneHot.scala:58:35]
wire oldest = inst_vat == io_vat_head; // @[StoreSequencer.scala:12:21, :62:25]
wire [5:0] _io_rvd_req_bits_eg_T_1 = {3'h0, sidx} << inst_emul; // @[StoreSequencer.scala:12:21, :14:21, :65:49]
wire [6:0] io_rvd_req_bits_eg_off = eidx >> 3'h4 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Parameters.scala:343:{20,73}]
assign _io_rvd_req_bits_eg_T_7 = inst_bits[11:7] + _io_rvd_req_bits_eg_T_1[4:0] + io_rvd_req_bits_eg_off[4:0]; // @[Parameters.scala:343:20, :344:10]
assign io_iss_valid_0 = valid & (({31'h0, renvm} | vd_read_oh) & io_older_writes) == 32'h0 & (~renvm | io_rvm_req_ready) & io_rvd_req_ready; // @[OneHot.scala:58:35]
wire [2:0] _vm_mask_T_4 = inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN; // @[Bundles.scala:59:{26,30}]
wire [127:0] _vm_mask_vm_resp_T = io_rvm_resp >> (eidx & ~(7'hF >> _vm_mask_T_4)); // @[Bundles.scala:59:26]
wire [4:0] _GEN_1 = {3'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:36:34]
wire [4:0] rd_group = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [1:0] group = 2'h0 >> io_dis_bits_emul; // @[StoreSequencer.scala:35:23]
wire [4:0] _GEN_2 = {4'h0, group[0]}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_1 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [1:0] group_1 = 2'h1 >> io_dis_bits_emul; // @[StoreSequencer.scala:35:23]
wire [4:0] _GEN_3 = {4'h0, group_1[0]}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_2 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_4 = {3'h0, 2'h2 >> io_dis_bits_emul}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_3 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_5 = {3'h0, 2'h3 >> io_dis_bits_emul}; // @[StoreSequencer.scala:35:23, :37:33]
wire [2:0] _GEN_6 = {1'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:35:23]
wire [4:0] rd_group_4 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_7 = {2'h0, 3'h4 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_5 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_8 = {2'h0, 3'h5 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_6 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_9 = {2'h0, 3'h6 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_7 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_10 = {2'h0, 3'h7 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [3:0] _GEN_11 = {2'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:35:23]
wire [4:0] rd_group_8 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_12 = {1'h0, 4'h8 >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_9 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_13 = {1'h0, 4'h9 >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_10 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_14 = {1'h0, 4'hA >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_11 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_15 = {1'h0, 4'hB >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_12 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_16 = {1'h0, 4'hC >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_13 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_17 = {1'h0, 4'hD >> _GEN_11}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_14 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_18 = {1'h0, 4'hE >> _GEN_11}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_15 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_19 = {1'h0, 4'hF >> _GEN_11}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] group_16 = 5'h10 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_16 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_17 = 5'h11 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_17 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_18 = 5'h12 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_18 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_19 = 5'h13 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_19 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_20 = 5'h14 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_20 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_21 = 5'h15 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_21 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_22 = 5'h16 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_22 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_23 = 5'h17 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_23 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_24 = 5'h18 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_24 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_25 = 5'h19 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_25 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_26 = 5'h1A >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_26 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_27 = 5'h1B >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_27 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_28 = 5'h1C >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_28 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_29 = 5'h1D >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_29 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_30 = 5'h1E >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_30 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_31 = 5'h1F >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_31 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire _GEN_20 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35]
wire _GEN_21 = _io_dis_ready_T_1 & ~tail; // @[Decoupled.scala:51:35]
wire [2:0] _offset_T = 3'h4 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Bundles.scala:59:{26,30}]
wire _GEN_22 = sidx == (~(|(inst_bits[27:26])) & inst_bits[24:20] == 5'h8 ? 3'h0 : inst_bits[31:29]); // @[Bundles.scala:61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
wire [4:0] _GEN_23 = {2'h0, io_dis_bits_bits[31:29]}; // @[Bundles.scala:63:16]
always @(posedge clock) begin // @[StoreSequencer.scala:8:7]
if (reset) // @[StoreSequencer.scala:8:7]
valid <= 1'h0; // @[StoreSequencer.scala:11:25]
else // @[StoreSequencer.scala:8:7]
valid <= _GEN_20 | (_io_dis_ready_T_1 ? ~tail : valid); // @[Decoupled.scala:51:35]
if (_GEN_20) begin // @[Decoupled.scala:51:35]
inst_bits <= io_dis_bits_bits; // @[StoreSequencer.scala:12:21]
inst_vconfig_vl <= io_dis_bits_vconfig_vl; // @[StoreSequencer.scala:12:21]
inst_vconfig_vtype_vsew <= io_dis_bits_vconfig_vtype_vsew; // @[StoreSequencer.scala:12:21]
inst_vat <= io_dis_bits_vat; // @[StoreSequencer.scala:12:21]
inst_emul <= io_dis_bits_emul; // @[StoreSequencer.scala:12:21]
inst_debug_id <= io_dis_bits_debug_id; // @[StoreSequencer.scala:12:21]
inst_mop <= io_dis_bits_mop; // @[StoreSequencer.scala:12:21]
sub_dlen <= (|(io_dis_bits_bits[27:26] == 2'h0 & io_dis_bits_bits[24:20] == 5'h8 ? 3'h0 : io_dis_bits_bits[31:29])) & {1'h0, io_dis_bits_mop[0] ? io_dis_bits_vconfig_vtype_vsew : {1'h0, io_dis_bits_bits[13:12]}} + 4'h3 < 4'h4 ? 2'h1 - (io_dis_bits_mop[0] ? io_dis_bits_vconfig_vtype_vsew[1:0] : io_dis_bits_bits[13:12]) : 2'h0; // @[Bundles.scala:59:{26,30,59}, :61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
end
if (_GEN_21 & _GEN_22) // @[StoreSequencer.scala:26:22, :81:{21,31}, :88:{16,33}, :90:12]
eidx <= next_eidx[6:0]; // @[StoreSequencer.scala:13:21, :90:12]
else if (_GEN_20) // @[Decoupled.scala:51:35]
eidx <= io_dis_bits_vstart; // @[StoreSequencer.scala:13:21]
if (_GEN_21) // @[StoreSequencer.scala:81:21]
sidx <= _GEN_22 ? 3'h0 : sidx + 3'h1; // @[StoreSequencer.scala:14:21, :88:{16,33}, :89:12, :92:{12,20}]
else if (_GEN_20) // @[Decoupled.scala:51:35]
sidx <= 3'h0; // @[StoreSequencer.scala:14:21]
if (~_GEN_21 | next_eidx >> _offset_T == {1'h0, eidx >> _offset_T}) begin // @[StoreSequencer.scala:13:21, :26:22, :81:{21,31}, :82:101, :83:16]
if (_GEN_20) // @[Decoupled.scala:51:35]
rvd_mask <= {group_31 >= rd_group_31 & group_31 <= rd_group_31 + _GEN_23, group_30 >= rd_group_30 & group_30 <= rd_group_30 + _GEN_23, group_29 >= rd_group_29 & group_29 <= rd_group_29 + _GEN_23, group_28 >= rd_group_28 & group_28 <= rd_group_28 + _GEN_23, group_27 >= rd_group_27 & group_27 <= rd_group_27 + _GEN_23, group_26 >= rd_group_26 & group_26 <= rd_group_26 + _GEN_23, group_25 >= rd_group_25 & group_25 <= rd_group_25 + _GEN_23, group_24 >= rd_group_24 & group_24 <= rd_group_24 + _GEN_23, group_23 >= rd_group_23 & group_23 <= rd_group_23 + _GEN_23, group_22 >= rd_group_22 & group_22 <= rd_group_22 + _GEN_23, group_21 >= rd_group_21 & group_21 <= rd_group_21 + _GEN_23, group_20 >= rd_group_20 & group_20 <= rd_group_20 + _GEN_23, group_19 >= rd_group_19 & group_19 <= rd_group_19 + _GEN_23, group_18 >= rd_group_18 & group_18 <= rd_group_18 + _GEN_23, group_17 >= rd_group_17 & group_17 <= rd_group_17 + _GEN_23, group_16 >= rd_group_16 & group_16 <= rd_group_16 + _GEN_23, _GEN_19 >= rd_group_15 & _GEN_19 <= rd_group_15 + _GEN_23, _GEN_18 >= rd_group_14 & _GEN_18 <= rd_group_14 + _GEN_23, _GEN_17 >= rd_group_13 & _GEN_17 <= rd_group_13 + _GEN_23, _GEN_16 >= rd_group_12 & _GEN_16 <= rd_group_12 + _GEN_23, _GEN_15 >= rd_group_11 & _GEN_15 <= rd_group_11 + _GEN_23, _GEN_14 >= rd_group_10 & _GEN_14 <= rd_group_10 + _GEN_23, _GEN_13 >= rd_group_9 & _GEN_13 <= rd_group_9 + _GEN_23, _GEN_12 >= rd_group_8 & _GEN_12 <= rd_group_8 + _GEN_23, _GEN_10 >= rd_group_7 & _GEN_10 <= rd_group_7 + _GEN_23, _GEN_9 >= rd_group_6 & _GEN_9 <= rd_group_6 + _GEN_23, _GEN_8 >= rd_group_5 & _GEN_8 <= rd_group_5 + _GEN_23, _GEN_7 >= rd_group_4 & _GEN_7 <= rd_group_4 + _GEN_23, _GEN_5 >= rd_group_3 & _GEN_5 <= rd_group_3 + _GEN_23, _GEN_4 >= rd_group_2 & _GEN_4 <= rd_group_2 + _GEN_23, _GEN_3 >= rd_group_1 & _GEN_3 <= rd_group_1 + _GEN_23, _GEN_2 >= rd_group & _GEN_2 <= rd_group + _GEN_23}; // @[StoreSequencer.scala:15:21, :35:23, :36:34, :37:{33,45,54,67}, :39:59]
end
else // @[StoreSequencer.scala:26:22, :81:31, :82:101]
rvd_mask <= rvd_mask & ~vd_read_oh; // @[OneHot.scala:58:35]
rvm_mask <= ~(_GEN_21 & next_eidx[7]) & (_GEN_20 ? ~(io_dis_bits_bits[25]) : rvm_mask); // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToIN_e11_s53_i64_7( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [64:0] io_in, // @[RecFNToIN.scala:49:16]
input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16]
input io_signedOut, // @[RecFNToIN.scala:49:16]
output [63:0] io_out, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7]
wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7]
wire [63:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [63:0] io_out_0; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53]
wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [5:0] _shiftedSig_T_2 = rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 6'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [115:0] shiftedSig = {63'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [64:0] _alignedSig_T = shiftedSig[115:51]; // @[RecFNToIN.scala:83:49, :89:20]
wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [65:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [63:0] _unroundedInt_T = alignedSig[65:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [63:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35]
wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35]
wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35]
wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26]
wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}]
wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27]
wire [63:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [63:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [64:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 65'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [63:0] _roundedInt_T_2 = _roundedInt_T_1[63:0]; // @[RecFNToIN.scala:106:31]
wire [63:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31]
wire [63:0] roundedInt = {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}]
wire magGeOne_atOverflowEdge = posExp == 11'h3F; // @[RecFNToIN.scala:62:28, :110:43]
wire [61:0] _roundCarryBut2_T = unroundedInt[61:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[10:6]); // @[RecFNToIN.scala:62:28, :116:21]
wire [62:0] _common_overflow_T_1 = unroundedInt[62:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 11'h3E; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_9 = unroundedInt[62]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13]
wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}]
wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27]
wire [63:0] _excOut_T_1 = {_excOut_T, 63'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [62:0] _excOut_T_3 = {63{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [63:0] excOut = {_excOut_T_1[63], _excOut_T_1[62:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_out = io_out_0; // @[RecFNToIN.scala:46:7]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_334( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulRawFN_49( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_49 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d64s4k3z4c_3( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_72 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s4k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s4k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s4k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s4k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s4k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_15( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_72( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9]
wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _GEN_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_29( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module TLXbar_prcibus_i1_o2_a21d64s7k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] in_0_d_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] out_1_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _in_0_d_bits_WIRE_param = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_19 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_WIRE_9 = 2'h0; // @[Mux.scala:30:73]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_d_bits_sink = 1'h0; // @[Xbar.scala:159:18]
wire in_0_d_bits_denied = 1'h0; // @[Xbar.scala:159:18]
wire in_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_0_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_1_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _out_1_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _in_0_d_bits_WIRE_sink = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_denied = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_5 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_6 = 1'h0; // @[Mux.scala:30:73]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [20:0] _addressC_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _addressC_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _requestCIO_T = 21'h0; // @[Parameters.scala:137:31]
wire [20:0] _requestCIO_T_5 = 21'h0; // @[Parameters.scala:137:31]
wire [20:0] _requestBOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _requestBOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] _requestBOI_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _requestBOI_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] _beatsBO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _beatsBO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] _beatsBO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _beatsBO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] _beatsCI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _beatsCI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _portsBIO_WIRE_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _portsBIO_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] portsBIO_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24]
wire [20:0] _portsBIO_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:264:74]
wire [20:0] _portsBIO_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:264:61]
wire [20:0] portsBIO_filtered_1_0_bits_address = 21'h0; // @[Xbar.scala:352:24]
wire [20:0] _portsCOI_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _portsCOI_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] portsCOI_filtered_0_bits_address = 21'h0; // @[Xbar.scala:352:24]
wire [20:0] portsCOI_filtered_1_bits_address = 21'h0; // @[Xbar.scala:352:24]
wire [6:0] _addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_1 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71]
wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire [21:0] _requestCIO_T_1 = 22'h0; // @[Parameters.scala:137:41]
wire [21:0] _requestCIO_T_2 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] _requestCIO_T_3 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] _requestCIO_T_6 = 22'h0; // @[Parameters.scala:137:41]
wire [21:0] _requestCIO_T_7 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] _requestCIO_T_8 = 22'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [20:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [20:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [6:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [20:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [20:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_1_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [20:0] out_1_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [20:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [20:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [20:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [21:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [21:0] _requestAIO_T_2 = _requestAIO_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}]
wire [21:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46]
wire _requestAIO_T_4 = _requestAIO_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54]
wire [20:0] _requestAIO_T_5 = {in_0_a_bits_address[20:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [21:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [21:0] _requestAIO_T_7 = _requestAIO_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}]
wire [21:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46]
wire _requestAIO_T_9 = _requestAIO_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54]
wire [6:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73]
assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_118( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_8, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_8, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_8, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_9, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [9:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_9; // @[InputUnit.scala:266:32]
wire vcalloc_vals_8; // @[InputUnit.scala:266:32]
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_8_g; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_9_g; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_8; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [9:0] mask; // @[InputUnit.scala:250:21]
wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, 3'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_250( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module TLXbar_cbus_out_i1_o8_a29d64s7k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_7_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_7_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_6_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_5_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_4_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_3_d_bits_size; // @[Xbar.scala:216:19]
wire out_2_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_2_d_bits_size; // @[Xbar.scala:216:19]
wire out_1_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19]
wire out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_7_a_ready_0 = auto_anon_out_7_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_7_d_valid_0 = auto_anon_out_7_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_7_d_bits_opcode_0 = auto_anon_out_7_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_7_d_bits_param_0 = auto_anon_out_7_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_7_d_bits_size_0 = auto_anon_out_7_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_7_d_bits_source_0 = auto_anon_out_7_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_7_d_bits_sink_0 = auto_anon_out_7_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_7_d_bits_denied_0 = auto_anon_out_7_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_7_d_bits_data_0 = auto_anon_out_7_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_7_d_bits_corrupt_0 = auto_anon_out_7_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_6_a_ready_0 = auto_anon_out_6_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_6_d_valid_0 = auto_anon_out_6_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_6_d_bits_size_0 = auto_anon_out_6_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_6_d_bits_source_0 = auto_anon_out_6_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_6_d_bits_data_0 = auto_anon_out_6_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_5_a_ready_0 = auto_anon_out_5_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_5_d_valid_0 = auto_anon_out_5_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_5_d_bits_opcode_0 = auto_anon_out_5_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_5_d_bits_size_0 = auto_anon_out_5_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_5_d_bits_source_0 = auto_anon_out_5_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_5_d_bits_data_0 = auto_anon_out_5_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_4_a_ready_0 = auto_anon_out_4_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_4_d_valid_0 = auto_anon_out_4_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_4_d_bits_opcode_0 = auto_anon_out_4_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_4_d_bits_size_0 = auto_anon_out_4_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_4_d_bits_source_0 = auto_anon_out_4_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_4_d_bits_data_0 = auto_anon_out_4_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_3_a_ready_0 = auto_anon_out_3_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_3_d_valid_0 = auto_anon_out_3_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_3_d_bits_opcode_0 = auto_anon_out_3_d_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_3_d_bits_size_0 = auto_anon_out_3_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_3_d_bits_source_0 = auto_anon_out_3_d_bits_source; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_3_d_bits_data_0 = auto_anon_out_3_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_2_a_ready_0 = auto_anon_out_2_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_2_d_valid_0 = auto_anon_out_2_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_2_d_bits_opcode_0 = auto_anon_out_2_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_2_d_bits_param_0 = auto_anon_out_2_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_2_d_bits_size_0 = auto_anon_out_2_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_2_d_bits_source_0 = auto_anon_out_2_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_2_d_bits_sink_0 = auto_anon_out_2_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_2_d_bits_denied_0 = auto_anon_out_2_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_2_d_bits_data_0 = auto_anon_out_2_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_2_d_bits_corrupt_0 = auto_anon_out_2_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_out_6_d_bits_opcode = 3'h1; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_5_d_bits_opcode = 3'h1; // @[MixedNode.scala:542:17]
wire [2:0] out_6_d_bits_opcode = 3'h1; // @[Xbar.scala:216:19]
wire [2:0] portsDIO_filtered_6_0_bits_opcode = 3'h1; // @[Xbar.scala:352:24]
wire [1:0] auto_anon_out_6_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_5_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_4_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_3_d_bits_param = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_2_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_anonOut_3_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_anonOut_4_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_anonOut_5_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] out_3_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] out_4_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] out_5_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] out_6_d_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_2_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_6_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_7_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_3_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_8_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_9_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_4_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_10_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_11_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_5_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_12_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_13_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_6_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _portsBIO_WIRE_14_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_15_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_7_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_3_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_4_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_5_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsDIO_filtered_6_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] _in_0_d_bits_T_93 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_94 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_95 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_96 = 2'h0; // @[Mux.scala:30:73]
wire auto_anon_out_6_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_6_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_6_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_d_bits_sink = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_d_bits_denied = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_d_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire x1_anonOut_2_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire out_3_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_3_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_3_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_4_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_4_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_4_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_5_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_5_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_5_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_6_d_bits_sink = 1'h0; // @[Xbar.scala:216:19]
wire out_6_d_bits_denied = 1'h0; // @[Xbar.scala:216:19]
wire out_6_d_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _out_3_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _out_4_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _out_5_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _out_6_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_10 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_15 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_20 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_25 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_30 = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_35 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_10 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_15 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_20 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_25 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_30 = 1'h0; // @[Parameters.scala:54:10]
wire _requestDOI_T_35 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_4_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_5_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_6_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_7_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_8_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_8_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_8_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_9_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_9_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_9_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_10_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_10_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_10_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_11_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_11_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_11_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_12_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_12_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_12_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_13_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_13_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_13_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_14_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_14_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_14_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_15_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_15_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_15_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_2 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_3 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_4 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_5 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_6 = 1'h0; // @[Edges.scala:97:37]
wire _beatsBO_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T_7 = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_6_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_6_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_6_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_7_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_7_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_7_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_3_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_8_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_8_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_8_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_9_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_9_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_9_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_4_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_10_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_10_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_10_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_11_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_11_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_11_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_5_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_5_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_5_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_11 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_12_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_12_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_12_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_13_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_13_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_13_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_6_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_6_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_6_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_13 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_WIRE_14_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_14_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_14_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_15_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_15_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_15_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_7_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_7_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_7_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_15 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_5_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_6_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_7_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_5 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_12 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_13 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_T_14 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire portsDIO_filtered_3_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_3_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_3_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_4_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_4_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_4_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_5_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_5_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_5_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_6_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_6_0_bits_denied = 1'h0; // @[Xbar.scala:352:24]
wire portsDIO_filtered_6_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_3_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_4_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_5_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_5_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_6_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_6_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_7_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_7_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_5 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_12 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_13 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_T_14 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_6 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7 = 1'h0; // @[Arbiter.scala:88:34]
wire _in_0_d_bits_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_5 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_48 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_49 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_50 = 1'h0; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_51 = 1'h0; // @[Mux.scala:30:73]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_2 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_3 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_4 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_5 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_34 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_6 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_39 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_7 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_11 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_13 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_2_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_16 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_18 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_3_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_21 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_23 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_4_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_26 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_28 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_5_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_31 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_33 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_34 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_6_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_36 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_38 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_7_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_11 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_13 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_2_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_16 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_18 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_3_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_21 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_23 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_4_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_26 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_28 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_5_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_31 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_33 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_34 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_6_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_36 = 1'h1; // @[Parameters.scala:54:32]
wire _requestDOI_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_38 = 1'h1; // @[Parameters.scala:54:67]
wire _requestDOI_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire requestDOI_7_0 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_2 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_3 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_4 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_5 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_6 = 1'h1; // @[Edges.scala:97:28]
wire beatsBO_opdata_7 = 1'h1; // @[Edges.scala:97:28]
wire beatsDO_opdata_6 = 1'h1; // @[Edges.scala:106:36]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_10 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_12 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_14 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_2_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_3_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_4_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_5_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_6_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_7_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_10 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_12 = 1'h1; // @[Xbar.scala:355:54]
wire _portsDIO_filtered_0_valid_T_14 = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_2_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_6_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_7_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_3_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_8_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_9_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_4_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_10_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_11_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_5_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_12_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_13_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_6_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsBIO_WIRE_14_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_15_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_7_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_2_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_3_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_4_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_5_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_6_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_7_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [28:0] _addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _requestCIO_T = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_5 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_10 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_15 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_20 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_25 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_30 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestCIO_T_35 = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] _requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_6_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_7_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_8_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_9_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_10_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_11_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_12_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_13_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _requestBOI_WIRE_14_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _requestBOI_WIRE_15_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_6_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_7_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_8_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_9_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_10_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_11_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_12_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_13_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsBO_WIRE_14_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _beatsBO_WIRE_15_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] _beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_1_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_2_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_6_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_7_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_3_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_8_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_9_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_4_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_10_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_11_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_5_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_12_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_13_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_6_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsBIO_WIRE_14_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] _portsBIO_WIRE_15_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] portsBIO_filtered_7_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] _portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_1_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_2_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_3_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_4_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_5_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_6_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] portsCOI_filtered_7_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [6:0] _addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_1 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_2 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_2 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_3 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_3 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_4 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_4 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_5 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_5 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_6 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_6 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T_7 = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] requestBOI_uncommonBits_7 = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] _beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_2_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_6_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_7_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_3_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_8_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_9_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_4_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_10_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_11_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_5_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_12_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_13_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_6_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsBIO_WIRE_14_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_15_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_7_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_2_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_3_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_4_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_5_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_6_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsCOI_filtered_7_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_2_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_6_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_7_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_3_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_8_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_9_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_4_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_10_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_11_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_5_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_12_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_13_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_6_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsBIO_WIRE_14_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_15_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_7_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_3_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_4_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_5_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_6_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_7_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_2 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_2 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_3 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_3 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_4 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_4 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_5 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_5 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_6 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_6 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsBO_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] beatsBO_decode_7 = 3'h0; // @[Edges.scala:220:59]
wire [2:0] beatsBO_7 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_2_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_6_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_7_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_3_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_8_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_9_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_4_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_10_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_11_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_5_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_12_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_13_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_6_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_14_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_15_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_7_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_2_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_6_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_7_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_3_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_8_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_9_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_4_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_10_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_11_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_5_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_12_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_13_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_6_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsBIO_WIRE_14_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_15_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_7_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_8 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_11 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_14 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_17 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_20 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_23 = 6'h0; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_7 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_10 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_13 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_16 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_19 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _beatsBO_decode_T_22 = 6'h3F; // @[package.scala:243:76]
wire [20:0] _beatsBO_decode_T_3 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_6 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_9 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_12 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_15 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_18 = 21'h3F; // @[package.scala:243:71]
wire [20:0] _beatsBO_decode_T_21 = 21'h3F; // @[package.scala:243:71]
wire [29:0] _requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_6 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_7 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_8 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_11 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_12 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_13 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_16 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_17 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_18 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_21 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_22 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_23 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_26 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_27 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_28 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_31 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_32 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_33 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_36 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] _requestCIO_T_37 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _requestCIO_T_38 = 30'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_anonOut_6_a_ready = auto_anon_out_7_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_6_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_6_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_6_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_6_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_6_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] x1_anonOut_6_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_6_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_6_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_6_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_6_d_valid = auto_anon_out_7_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_6_d_bits_opcode = auto_anon_out_7_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_6_d_bits_param = auto_anon_out_7_d_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_6_d_bits_size = auto_anon_out_7_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_6_d_bits_source = auto_anon_out_7_d_bits_source_0; // @[Xbar.scala:74:9]
wire x1_anonOut_6_d_bits_sink = auto_anon_out_7_d_bits_sink_0; // @[Xbar.scala:74:9]
wire x1_anonOut_6_d_bits_denied = auto_anon_out_7_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_6_d_bits_data = auto_anon_out_7_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_6_d_bits_corrupt = auto_anon_out_7_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire x1_anonOut_5_a_ready = auto_anon_out_6_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_5_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_5_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_5_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_5_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_5_a_bits_source; // @[MixedNode.scala:542:17]
wire [16:0] x1_anonOut_5_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_5_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_5_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_5_d_valid = auto_anon_out_6_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_5_d_bits_size = auto_anon_out_6_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_5_d_bits_source = auto_anon_out_6_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_5_d_bits_data = auto_anon_out_6_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_4_a_ready = auto_anon_out_5_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_4_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_4_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_4_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_4_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_4_a_bits_source; // @[MixedNode.scala:542:17]
wire [11:0] x1_anonOut_4_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_4_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_4_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_4_d_valid = auto_anon_out_5_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_4_d_bits_opcode = auto_anon_out_5_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_4_d_bits_size = auto_anon_out_5_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_4_d_bits_source = auto_anon_out_5_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_4_d_bits_data = auto_anon_out_5_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_3_a_ready = auto_anon_out_4_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_3_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_3_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_3_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_3_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_3_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] x1_anonOut_3_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_3_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_3_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_3_d_valid = auto_anon_out_4_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_3_d_bits_opcode = auto_anon_out_4_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_3_d_bits_size = auto_anon_out_4_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_3_d_bits_source = auto_anon_out_4_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_3_d_bits_data = auto_anon_out_4_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_2_a_ready = auto_anon_out_3_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [25:0] x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_2_d_valid = auto_anon_out_3_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_2_d_bits_opcode = auto_anon_out_3_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_2_d_bits_size = auto_anon_out_3_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_2_d_bits_source = auto_anon_out_3_d_bits_source_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_2_d_bits_data = auto_anon_out_3_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_1_a_ready = auto_anon_out_2_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_d_valid = auto_anon_out_2_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_1_d_bits_opcode = auto_anon_out_2_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_1_d_bits_param = auto_anon_out_2_d_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_1_d_bits_size = auto_anon_out_2_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_1_d_bits_source = auto_anon_out_2_d_bits_source_0; // @[Xbar.scala:74:9]
wire x1_anonOut_1_d_bits_sink = auto_anon_out_2_d_bits_sink_0; // @[Xbar.scala:74:9]
wire x1_anonOut_1_d_bits_denied = auto_anon_out_2_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_1_d_bits_data = auto_anon_out_2_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_1_d_bits_corrupt = auto_anon_out_2_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [25:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [13:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_7_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_7_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_7_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_7_a_bits_source_0; // @[Xbar.scala:74:9]
wire [20:0] auto_anon_out_7_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_7_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_7_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_7_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_7_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_7_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_6_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_6_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_6_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_6_a_bits_source_0; // @[Xbar.scala:74:9]
wire [16:0] auto_anon_out_6_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_6_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_6_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_6_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_6_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_6_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_5_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_5_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_5_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_5_a_bits_source_0; // @[Xbar.scala:74:9]
wire [11:0] auto_anon_out_5_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_5_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_5_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_5_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_4_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_4_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_4_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_4_a_bits_source_0; // @[Xbar.scala:74:9]
wire [27:0] auto_anon_out_4_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_4_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_4_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_4_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_3_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_3_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_3_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_3_a_bits_source_0; // @[Xbar.scala:74:9]
wire [25:0] auto_anon_out_3_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_3_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_3_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_3_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_2_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_2_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_2_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_2_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_out_2_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_2_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_2_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_2_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_2_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_2_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [25:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [13:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [6:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [28:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_1_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [6:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_2_a_ready = x1_anonOut_1_a_ready; // @[Xbar.scala:216:19]
wire out_2_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_valid_0 = x1_anonOut_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_2_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_opcode_0 = x1_anonOut_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_2_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_param_0 = x1_anonOut_1_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_2_a_bits_size_0 = x1_anonOut_1_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_2_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_source_0 = x1_anonOut_1_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] out_2_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_address_0 = x1_anonOut_1_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_2_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_mask_0 = x1_anonOut_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_2_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_data_0 = x1_anonOut_1_a_bits_data; // @[Xbar.scala:74:9]
wire out_2_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_2_a_bits_corrupt_0 = x1_anonOut_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_2_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_2_d_ready_0 = x1_anonOut_1_d_ready; // @[Xbar.scala:74:9]
wire out_2_d_valid = x1_anonOut_1_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_2_d_bits_opcode = x1_anonOut_1_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_2_d_bits_param = x1_anonOut_1_d_bits_param; // @[Xbar.scala:216:19]
wire [6:0] out_2_d_bits_source = x1_anonOut_1_d_bits_source; // @[Xbar.scala:216:19]
wire _out_2_d_bits_sink_T = x1_anonOut_1_d_bits_sink; // @[Xbar.scala:251:53]
wire out_2_d_bits_denied = x1_anonOut_1_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_2_d_bits_data = x1_anonOut_1_d_bits_data; // @[Xbar.scala:216:19]
wire out_2_d_bits_corrupt = x1_anonOut_1_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_3_a_ready = x1_anonOut_2_a_ready; // @[Xbar.scala:216:19]
wire out_3_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_valid_0 = x1_anonOut_2_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_3_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_opcode_0 = x1_anonOut_2_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_3_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_param_0 = x1_anonOut_2_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_3_a_bits_size_0 = x1_anonOut_2_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_3_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_source_0 = x1_anonOut_2_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_3_a_bits_address_0 = x1_anonOut_2_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_3_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_mask_0 = x1_anonOut_2_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_3_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_data_0 = x1_anonOut_2_a_bits_data; // @[Xbar.scala:74:9]
wire out_3_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_3_a_bits_corrupt_0 = x1_anonOut_2_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_3_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_3_d_ready_0 = x1_anonOut_2_d_ready; // @[Xbar.scala:74:9]
wire out_3_d_valid = x1_anonOut_2_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_3_d_bits_opcode = x1_anonOut_2_d_bits_opcode; // @[Xbar.scala:216:19]
wire [6:0] out_3_d_bits_source = x1_anonOut_2_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_3_d_bits_data = x1_anonOut_2_d_bits_data; // @[Xbar.scala:216:19]
wire out_4_a_ready = x1_anonOut_3_a_ready; // @[Xbar.scala:216:19]
wire out_4_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_valid_0 = x1_anonOut_3_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_4_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_opcode_0 = x1_anonOut_3_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_4_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_param_0 = x1_anonOut_3_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_4_a_bits_size_0 = x1_anonOut_3_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_4_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_source_0 = x1_anonOut_3_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_4_a_bits_address_0 = x1_anonOut_3_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_4_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_mask_0 = x1_anonOut_3_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_4_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_data_0 = x1_anonOut_3_a_bits_data; // @[Xbar.scala:74:9]
wire out_4_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_4_a_bits_corrupt_0 = x1_anonOut_3_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_4_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_4_d_ready_0 = x1_anonOut_3_d_ready; // @[Xbar.scala:74:9]
wire out_4_d_valid = x1_anonOut_3_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_4_d_bits_opcode = x1_anonOut_3_d_bits_opcode; // @[Xbar.scala:216:19]
wire [6:0] out_4_d_bits_source = x1_anonOut_3_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_4_d_bits_data = x1_anonOut_3_d_bits_data; // @[Xbar.scala:216:19]
wire out_5_a_ready = x1_anonOut_4_a_ready; // @[Xbar.scala:216:19]
wire out_5_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_valid_0 = x1_anonOut_4_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_5_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_opcode_0 = x1_anonOut_4_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_5_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_param_0 = x1_anonOut_4_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_5_a_bits_size_0 = x1_anonOut_4_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_5_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_source_0 = x1_anonOut_4_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_5_a_bits_address_0 = x1_anonOut_4_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_5_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_mask_0 = x1_anonOut_4_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_5_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_data_0 = x1_anonOut_4_a_bits_data; // @[Xbar.scala:74:9]
wire out_5_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_5_a_bits_corrupt_0 = x1_anonOut_4_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_5_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_5_d_ready_0 = x1_anonOut_4_d_ready; // @[Xbar.scala:74:9]
wire out_5_d_valid = x1_anonOut_4_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_5_d_bits_opcode = x1_anonOut_4_d_bits_opcode; // @[Xbar.scala:216:19]
wire [6:0] out_5_d_bits_source = x1_anonOut_4_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_5_d_bits_data = x1_anonOut_4_d_bits_data; // @[Xbar.scala:216:19]
wire out_6_a_ready = x1_anonOut_5_a_ready; // @[Xbar.scala:216:19]
wire out_6_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_valid_0 = x1_anonOut_5_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_6_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_opcode_0 = x1_anonOut_5_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_6_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_param_0 = x1_anonOut_5_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_6_a_bits_size_0 = x1_anonOut_5_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_6_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_source_0 = x1_anonOut_5_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_6_a_bits_address_0 = x1_anonOut_5_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_6_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_mask_0 = x1_anonOut_5_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_6_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_data_0 = x1_anonOut_5_a_bits_data; // @[Xbar.scala:74:9]
wire out_6_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_6_a_bits_corrupt_0 = x1_anonOut_5_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_6_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_6_d_ready_0 = x1_anonOut_5_d_ready; // @[Xbar.scala:74:9]
wire out_6_d_valid = x1_anonOut_5_d_valid; // @[Xbar.scala:216:19]
wire [6:0] out_6_d_bits_source = x1_anonOut_5_d_bits_source; // @[Xbar.scala:216:19]
wire [63:0] out_6_d_bits_data = x1_anonOut_5_d_bits_data; // @[Xbar.scala:216:19]
wire out_7_a_ready = x1_anonOut_6_a_ready; // @[Xbar.scala:216:19]
wire out_7_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_valid_0 = x1_anonOut_6_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_7_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_opcode_0 = x1_anonOut_6_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_7_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_param_0 = x1_anonOut_6_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_7_a_bits_size_0 = x1_anonOut_6_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_7_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_source_0 = x1_anonOut_6_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_7_a_bits_address_0 = x1_anonOut_6_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_7_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_mask_0 = x1_anonOut_6_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_7_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_data_0 = x1_anonOut_6_a_bits_data; // @[Xbar.scala:74:9]
wire out_7_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_7_a_bits_corrupt_0 = x1_anonOut_6_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_7_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_7_d_ready_0 = x1_anonOut_6_d_ready; // @[Xbar.scala:74:9]
wire out_7_d_valid = x1_anonOut_6_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_7_d_bits_opcode = x1_anonOut_6_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_7_d_bits_param = x1_anonOut_6_d_bits_param; // @[Xbar.scala:216:19]
wire [6:0] out_7_d_bits_source = x1_anonOut_6_d_bits_source; // @[Xbar.scala:216:19]
wire _out_7_d_bits_sink_T = x1_anonOut_6_d_bits_sink; // @[Xbar.scala:251:53]
wire out_7_d_bits_denied = x1_anonOut_6_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_7_d_bits_data = x1_anonOut_6_d_bits_data; // @[Xbar.scala:216:19]
wire out_7_d_bits_corrupt = x1_anonOut_6_d_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_3_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_4_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_5_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_6_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_7_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_3_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_4_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_5_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_6_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_7_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_2_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_3_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_4_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_5_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_6_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_7_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_2_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_3_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_4_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_5_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_6_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_7_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [28:0] _requestAIO_T_31 = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [28:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_2_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_3_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_4_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_5_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_6_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [28:0] portsAOI_filtered_7_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_2_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_3_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_4_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_5_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_6_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_7_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_2_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_3_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_4_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_5_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_6_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_7_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_3_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_4_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_5_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_6_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_7_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_0_d_valid_T_22; // @[Arbiter.scala:96:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_2_ready = out_2_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_2_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_1_a_valid = out_2_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_opcode = out_2_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_param = out_2_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_source = out_2_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_address = out_2_a_bits_address; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_mask = out_2_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_data = out_2_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_1_a_bits_corrupt = out_2_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_2_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_1_d_ready = out_2_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_5 = out_2_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_2_0_bits_opcode = out_2_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_2_0_bits_param = out_2_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_2_0_bits_size = out_2_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_2 = out_2_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_2_0_bits_source = out_2_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_0_bits_sink = out_2_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_0_bits_denied = out_2_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_2_0_bits_data = out_2_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_0_bits_corrupt = out_2_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_3_ready = out_3_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_3_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_2_a_valid = out_3_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_opcode = out_3_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_param = out_3_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_source = out_3_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_mask = out_3_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_data = out_3_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_2_a_bits_corrupt = out_3_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_3_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_2_d_ready = out_3_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_7 = out_3_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_3_0_bits_opcode = out_3_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_3_0_bits_size = out_3_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_3 = out_3_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_3_0_bits_source = out_3_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_3_0_bits_data = out_3_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_4_ready = out_4_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_4_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_3_a_valid = out_4_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_opcode = out_4_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_param = out_4_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_source = out_4_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_mask = out_4_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_data = out_4_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_3_a_bits_corrupt = out_4_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_4_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_3_d_ready = out_4_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_9 = out_4_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_4_0_bits_opcode = out_4_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_4_0_bits_size = out_4_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_4 = out_4_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_4_0_bits_source = out_4_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_4_0_bits_data = out_4_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_5_ready = out_5_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_5_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_4_a_valid = out_5_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_opcode = out_5_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_param = out_5_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_source = out_5_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_mask = out_5_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_data = out_5_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_4_a_bits_corrupt = out_5_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_5_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_4_d_ready = out_5_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_11 = out_5_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_5_0_bits_opcode = out_5_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_5_0_bits_size = out_5_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_5 = out_5_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_5_0_bits_source = out_5_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_5_0_bits_data = out_5_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_6_ready = out_6_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_6_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_5_a_valid = out_6_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_opcode = out_6_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_param = out_6_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_source = out_6_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_mask = out_6_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_data = out_6_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_5_a_bits_corrupt = out_6_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_6_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_5_d_ready = out_6_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_13 = out_6_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [3:0] portsDIO_filtered_6_0_bits_size = out_6_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_6 = out_6_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_6_0_bits_source = out_6_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_6_0_bits_data = out_6_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_7_ready = out_7_a_ready; // @[Xbar.scala:216:19, :352:24]
wire portsAOI_filtered_7_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_6_a_valid = out_7_a_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_opcode = out_7_a_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_param = out_7_a_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_source = out_7_a_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_mask = out_7_a_bits_mask; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_data = out_7_a_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_6_a_bits_corrupt = out_7_a_bits_corrupt; // @[Xbar.scala:216:19]
wire portsDIO_filtered_7_0_ready; // @[Xbar.scala:352:24]
assign x1_anonOut_6_d_ready = out_7_d_ready; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T_15 = out_7_d_valid; // @[Xbar.scala:216:19, :355:40]
wire [2:0] portsDIO_filtered_7_0_bits_opcode = out_7_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_7_0_bits_param = out_7_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_7_0_bits_size = out_7_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T_7 = out_7_d_bits_source; // @[Xbar.scala:216:19]
wire [6:0] portsDIO_filtered_7_0_bits_source = out_7_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_7_0_bits_sink = out_7_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_7_0_bits_denied = out_7_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_7_0_bits_data = out_7_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [28:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
wire portsDIO_filtered_7_0_bits_corrupt = out_7_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_1_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] out_2_a_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_3_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_3_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] out_4_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_4_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] out_5_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_5_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] out_6_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_6_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] out_7_a_bits_size; // @[Xbar.scala:216:19]
wire [28:0] out_7_a_bits_address; // @[Xbar.scala:216:19]
assign anonOut_a_bits_address = out_0_a_bits_address[13:0]; // @[Xbar.scala:216:19, :222:41]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign x1_anonOut_a_bits_address = out_1_a_bits_address[25:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign x1_anonOut_1_a_bits_size = out_2_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_2_d_bits_size = {1'h0, x1_anonOut_1_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign out_2_d_bits_sink = _out_2_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign x1_anonOut_2_a_bits_address = out_3_a_bits_address[25:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_2_a_bits_size = out_3_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_3_d_bits_size = {1'h0, x1_anonOut_2_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign x1_anonOut_3_a_bits_address = out_4_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_3_a_bits_size = out_4_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_4_d_bits_size = {1'h0, x1_anonOut_3_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign x1_anonOut_4_a_bits_address = out_5_a_bits_address[11:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_4_a_bits_size = out_5_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_5_d_bits_size = {1'h0, x1_anonOut_4_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign x1_anonOut_5_a_bits_address = out_6_a_bits_address[16:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_5_a_bits_size = out_6_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_6_d_bits_size = {1'h0, x1_anonOut_5_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign x1_anonOut_6_a_bits_address = out_7_a_bits_address[20:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_6_a_bits_size = out_7_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign out_7_d_bits_size = {1'h0, x1_anonOut_6_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign out_7_d_bits_sink = _out_7_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [28:0] _requestAIO_T = {in_0_a_bits_address[28:14], in_0_a_bits_address[13:0] ^ 14'h3000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_2 = _requestAIO_T_1 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46]
wire _requestAIO_T_4 = _requestAIO_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_5 = {in_0_a_bits_address[28:26], in_0_a_bits_address[25:0] ^ 26'h2010000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_7 = _requestAIO_T_6 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46]
wire _requestAIO_T_9 = _requestAIO_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_10 = {in_0_a_bits_address[28:13], in_0_a_bits_address[12:0] ^ 13'h1000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_12 = _requestAIO_T_11 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46]
wire _requestAIO_T_14 = _requestAIO_T_13 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _requestAIO_T_15 = in_0_a_bits_address ^ 29'h10000000; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_16 = {1'h0, _requestAIO_T_15}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_17 = _requestAIO_T_16 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_18 = _requestAIO_T_17; // @[Parameters.scala:137:46]
wire _requestAIO_T_19 = _requestAIO_T_18 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_20 = _requestAIO_T_14 | _requestAIO_T_19; // @[Xbar.scala:291:92]
wire requestAIO_0_2 = _requestAIO_T_20; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_2_valid_T = requestAIO_0_2; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_21 = {in_0_a_bits_address[28:26], in_0_a_bits_address[25:0] ^ 26'h2000000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_22 = {1'h0, _requestAIO_T_21}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_23 = _requestAIO_T_22 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_24 = _requestAIO_T_23; // @[Parameters.scala:137:46]
wire _requestAIO_T_25 = _requestAIO_T_24 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_3 = _requestAIO_T_25; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_3_valid_T = requestAIO_0_3; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_26 = {in_0_a_bits_address[28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_27 = {1'h0, _requestAIO_T_26}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_28 = _requestAIO_T_27 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_29 = _requestAIO_T_28; // @[Parameters.scala:137:46]
wire _requestAIO_T_30 = _requestAIO_T_29 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_4 = _requestAIO_T_30; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_4_valid_T = requestAIO_0_4; // @[Xbar.scala:307:107, :355:54]
wire [29:0] _requestAIO_T_32 = {1'h0, _requestAIO_T_31}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_33 = _requestAIO_T_32 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_34 = _requestAIO_T_33; // @[Parameters.scala:137:46]
wire _requestAIO_T_35 = _requestAIO_T_34 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_5 = _requestAIO_T_35; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_5_valid_T = requestAIO_0_5; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_36 = {in_0_a_bits_address[28:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_37 = {1'h0, _requestAIO_T_36}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_38 = _requestAIO_T_37 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_39 = _requestAIO_T_38; // @[Parameters.scala:137:46]
wire _requestAIO_T_40 = _requestAIO_T_39 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_6 = _requestAIO_T_40; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_6_valid_T = requestAIO_0_6; // @[Xbar.scala:307:107, :355:54]
wire [28:0] _requestAIO_T_41 = {in_0_a_bits_address[28:21], in_0_a_bits_address[20:0] ^ 21'h100000}; // @[Xbar.scala:159:18]
wire [29:0] _requestAIO_T_42 = {1'h0, _requestAIO_T_41}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _requestAIO_T_43 = _requestAIO_T_42 & 30'h1A103000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _requestAIO_T_44 = _requestAIO_T_43; // @[Parameters.scala:137:46]
wire _requestAIO_T_45 = _requestAIO_T_44 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire requestAIO_0_7 = _requestAIO_T_45; // @[Xbar.scala:307:107]
wire _portsAOI_filtered_7_valid_T = requestAIO_0_7; // @[Xbar.scala:307:107, :355:54]
wire [6:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_6 = _requestDOI_uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [6:0] requestDOI_uncommonBits_7 = _requestDOI_uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_6 = 21'h3F << out_2_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_7 = _beatsDO_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_8 = ~_beatsDO_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_2 = _beatsDO_decode_T_8[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_2 = out_2_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_9 = 21'h3F << out_3_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_10 = _beatsDO_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_3 = _beatsDO_decode_T_11[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_3 = out_3_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_12 = 21'h3F << out_4_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_13 = _beatsDO_decode_T_12[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_14 = ~_beatsDO_decode_T_13; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_4 = _beatsDO_decode_T_14[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_4 = out_4_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_15 = 21'h3F << out_5_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_16 = _beatsDO_decode_T_15[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_17 = ~_beatsDO_decode_T_16; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_5 = _beatsDO_decode_T_17[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_5 = out_5_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_18 = 21'h3F << out_6_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_19 = _beatsDO_decode_T_18[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_20 = ~_beatsDO_decode_T_19; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_6 = _beatsDO_decode_T_20[5:3]; // @[package.scala:243:46]
wire [2:0] beatsDO_6 = beatsDO_decode_6; // @[Edges.scala:220:59, :221:14]
wire [20:0] _beatsDO_decode_T_21 = 21'h3F << out_7_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_22 = _beatsDO_decode_T_21[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_22; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_7 = _beatsDO_decode_T_23[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_7 = out_7_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_7 = beatsDO_opdata_7 ? beatsDO_decode_7 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_2_valid_T_1; // @[Xbar.scala:355:40]
assign out_2_a_valid = portsAOI_filtered_2_valid; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_opcode = portsAOI_filtered_2_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_param = portsAOI_filtered_2_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_size = portsAOI_filtered_2_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_source = portsAOI_filtered_2_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_address = portsAOI_filtered_2_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_mask = portsAOI_filtered_2_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_data = portsAOI_filtered_2_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_2_a_bits_corrupt = portsAOI_filtered_2_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_3_valid_T_1; // @[Xbar.scala:355:40]
assign out_3_a_valid = portsAOI_filtered_3_valid; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_opcode = portsAOI_filtered_3_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_param = portsAOI_filtered_3_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_size = portsAOI_filtered_3_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_source = portsAOI_filtered_3_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_address = portsAOI_filtered_3_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_mask = portsAOI_filtered_3_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_data = portsAOI_filtered_3_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_3_a_bits_corrupt = portsAOI_filtered_3_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_4_valid_T_1; // @[Xbar.scala:355:40]
assign out_4_a_valid = portsAOI_filtered_4_valid; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_opcode = portsAOI_filtered_4_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_param = portsAOI_filtered_4_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_size = portsAOI_filtered_4_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_source = portsAOI_filtered_4_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_address = portsAOI_filtered_4_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_mask = portsAOI_filtered_4_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_data = portsAOI_filtered_4_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_4_a_bits_corrupt = portsAOI_filtered_4_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_5_valid_T_1; // @[Xbar.scala:355:40]
assign out_5_a_valid = portsAOI_filtered_5_valid; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_opcode = portsAOI_filtered_5_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_param = portsAOI_filtered_5_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_size = portsAOI_filtered_5_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_source = portsAOI_filtered_5_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_address = portsAOI_filtered_5_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_mask = portsAOI_filtered_5_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_data = portsAOI_filtered_5_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_5_a_bits_corrupt = portsAOI_filtered_5_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_6_valid_T_1; // @[Xbar.scala:355:40]
assign out_6_a_valid = portsAOI_filtered_6_valid; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_opcode = portsAOI_filtered_6_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_param = portsAOI_filtered_6_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_size = portsAOI_filtered_6_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_source = portsAOI_filtered_6_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_address = portsAOI_filtered_6_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_mask = portsAOI_filtered_6_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_data = portsAOI_filtered_6_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_6_a_bits_corrupt = portsAOI_filtered_6_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _portsAOI_filtered_7_valid_T_1; // @[Xbar.scala:355:40]
assign out_7_a_valid = portsAOI_filtered_7_valid; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_opcode = portsAOI_filtered_7_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_param = portsAOI_filtered_7_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_size = portsAOI_filtered_7_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_source = portsAOI_filtered_7_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_address = portsAOI_filtered_7_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_mask = portsAOI_filtered_7_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_data = portsAOI_filtered_7_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_7_a_bits_corrupt = portsAOI_filtered_7_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_2_valid_T_1 = in_0_a_valid & _portsAOI_filtered_2_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_2_valid = _portsAOI_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_3_valid_T_1 = in_0_a_valid & _portsAOI_filtered_3_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_3_valid = _portsAOI_filtered_3_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_4_valid_T_1 = in_0_a_valid & _portsAOI_filtered_4_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_4_valid = _portsAOI_filtered_4_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_5_valid_T_1 = in_0_a_valid & _portsAOI_filtered_5_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_5_valid = _portsAOI_filtered_5_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_6_valid_T_1 = in_0_a_valid & _portsAOI_filtered_6_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_6_valid = _portsAOI_filtered_6_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_7_valid_T_1 = in_0_a_valid & _portsAOI_filtered_7_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_7_valid = _portsAOI_filtered_7_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_2 = requestAIO_0_2 & portsAOI_filtered_2_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_3 = requestAIO_0_3 & portsAOI_filtered_3_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_4 = requestAIO_0_4 & portsAOI_filtered_4_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_5 = requestAIO_0_5 & portsAOI_filtered_5_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_6 = requestAIO_0_6 & portsAOI_filtered_6_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_7 = requestAIO_0_7 & portsAOI_filtered_7_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_8 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_9 = _portsAOI_in_0_a_ready_T_8 | _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_10 = _portsAOI_in_0_a_ready_T_9 | _portsAOI_in_0_a_ready_T_3; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_11 = _portsAOI_in_0_a_ready_T_10 | _portsAOI_in_0_a_ready_T_4; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_12 = _portsAOI_in_0_a_ready_T_11 | _portsAOI_in_0_a_ready_T_5; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_13 = _portsAOI_in_0_a_ready_T_12 | _portsAOI_in_0_a_ready_T_6; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_14 = _portsAOI_in_0_a_ready_T_13 | _portsAOI_in_0_a_ready_T_7; // @[Mux.scala:30:73]
assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_14; // @[Mux.scala:30:73]
assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31]
assign out_2_d_ready = portsDIO_filtered_2_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_2_0_valid = _portsDIO_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31]
assign out_3_d_ready = portsDIO_filtered_3_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_3_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_3_0_valid = _portsDIO_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31]
assign out_4_d_ready = portsDIO_filtered_4_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_4_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_4_0_valid = _portsDIO_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_5; // @[Arbiter.scala:94:31]
assign out_5_d_ready = portsDIO_filtered_5_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_5_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_5_0_valid = _portsDIO_filtered_0_valid_T_11; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_6; // @[Arbiter.scala:94:31]
assign out_6_d_ready = portsDIO_filtered_6_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_6_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_6_0_valid = _portsDIO_filtered_0_valid_T_13; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_7; // @[Arbiter.scala:94:31]
assign out_7_d_ready = portsDIO_filtered_7_0_ready; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_7_0_valid; // @[Xbar.scala:352:24]
assign portsDIO_filtered_7_0_valid = _portsDIO_filtered_0_valid_T_15; // @[Xbar.scala:352:24, :355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18]
wire [1:0] readys_lo_lo = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_lo_hi = {portsDIO_filtered_3_0_valid, portsDIO_filtered_2_0_valid}; // @[Xbar.scala:352:24]
wire [3:0] readys_lo = {readys_lo_hi, readys_lo_lo}; // @[Arbiter.scala:68:51]
wire [1:0] readys_hi_lo = {portsDIO_filtered_5_0_valid, portsDIO_filtered_4_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_hi_hi = {portsDIO_filtered_7_0_valid, portsDIO_filtered_6_0_valid}; // @[Xbar.scala:352:24]
wire [3:0] readys_hi = {readys_hi_hi, readys_hi_lo}; // @[Arbiter.scala:68:51]
wire [7:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51]
wire [7:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [7:0] readys_mask; // @[Arbiter.scala:23:23]
wire [7:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [7:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [15:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [14:0] _readys_unready_T = readys_filter[15:1]; // @[package.scala:262:48]
wire [15:0] _readys_unready_T_1 = {readys_filter[15], readys_filter[14:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [13:0] _readys_unready_T_2 = _readys_unready_T_1[15:2]; // @[package.scala:262:{43,48}]
wire [15:0] _readys_unready_T_3 = {_readys_unready_T_1[15:14], _readys_unready_T_1[13:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}]
wire [11:0] _readys_unready_T_4 = _readys_unready_T_3[15:4]; // @[package.scala:262:{43,48}]
wire [15:0] _readys_unready_T_5 = {_readys_unready_T_3[15:12], _readys_unready_T_3[11:0] | _readys_unready_T_4}; // @[package.scala:262:{43,48}]
wire [15:0] _readys_unready_T_6 = _readys_unready_T_5; // @[package.scala:262:43, :263:17]
wire [14:0] _readys_unready_T_7 = _readys_unready_T_6[15:1]; // @[package.scala:263:17]
wire [15:0] _readys_unready_T_8 = {readys_mask, 8'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [15:0] readys_unready = {1'h0, _readys_unready_T_7} | _readys_unready_T_8; // @[Arbiter.scala:25:{52,58,66}]
wire [7:0] _readys_readys_T = readys_unready[15:8]; // @[Arbiter.scala:25:58, :26:29]
wire [7:0] _readys_readys_T_1 = readys_unready[7:0]; // @[Arbiter.scala:25:58, :26:48]
wire [7:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [7:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [7:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [7:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [8:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [7:0] _readys_mask_T_2 = _readys_mask_T_1[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [9:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _readys_mask_T_5 = _readys_mask_T_4[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}]
wire [11:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _readys_mask_T_8 = _readys_mask_T_7[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_8; // @[package.scala:253:{43,53}]
wire [7:0] _readys_mask_T_10 = _readys_mask_T_9; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_11 = _readys_T_7[3]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3 = _readys_T_11; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_12 = _readys_T_7[4]; // @[Arbiter.scala:30:11, :68:76]
wire readys_4 = _readys_T_12; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_13 = _readys_T_7[5]; // @[Arbiter.scala:30:11, :68:76]
wire readys_5 = _readys_T_13; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_14 = _readys_T_7[6]; // @[Arbiter.scala:30:11, :68:76]
wire readys_6 = _readys_T_14; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_15 = _readys_T_7[7]; // @[Arbiter.scala:30:11, :68:76]
wire readys_7 = _readys_T_15; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_2 = readys_2 & portsDIO_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_3 = readys_3 & portsDIO_filtered_3_0_valid; // @[Xbar.scala:352:24]
wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_4 = readys_4 & portsDIO_filtered_4_0_valid; // @[Xbar.scala:352:24]
wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_5 = readys_5 & portsDIO_filtered_5_0_valid; // @[Xbar.scala:352:24]
wire winner_5 = _winner_T_5; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_6 = readys_6 & portsDIO_filtered_6_0_valid; // @[Xbar.scala:352:24]
wire winner_6 = _winner_T_6; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_7 = readys_7 & portsDIO_filtered_7_0_valid; // @[Xbar.scala:352:24]
wire winner_7 = _winner_T_7; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_3 = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_4 = prefixOR_3 | winner_3; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_5 = prefixOR_4 | winner_4; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_6 = prefixOR_5 | winner_5; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_7 = prefixOR_6 | winner_6; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_7 | winner_7; // @[Arbiter.scala:71:27, :76:48]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_71( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_3( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_3 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_3 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_3 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_39( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_50( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_70 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_153( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i64_e5_s11_1( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [16:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [16:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_1 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_172( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLFragmenter_1( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [13:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [1:0] _maxLgHint_T = {2{~(_repeater_io_deq_bits_address[8])}}; // @[Mux.scala:30:73]
wire [1:0] _maxLgHint_T_1 = {2{_repeater_io_deq_bits_address[8]}}; // @[Mux.scala:30:73]
wire [7:0][1:0] _GEN_0 = {{2'h3}, {2'h3}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}, {_maxLgHint_T | _maxLgHint_T_1}}; // @[Mux.scala:30:73]
wire [1:0] limit = _GEN_0[_repeater_io_deq_bits_opcode]; // @[Fragmenter.scala:274:30, :288:49]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_186( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c_1( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [3:0] out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24]
wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73]
wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18]
wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire [15:0] auto_anon_in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9]
wire [15:0] anonIn_1_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18]
wire [15:0] portsAOI_filtered_1_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24]
wire [127:0] auto_anon_in_1_a_bits_data = 128'h0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_1_a_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] in_1_a_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_1_c_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] portsAOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] _out_0_a_bits_T_4 = 128'h0; // @[Mux.scala:30:73]
wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [7:0] beatsAI_1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsCI_decode_1 = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsCI_1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69]
wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_b_bits_source = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_source = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_e_bits_sink = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] requestEIO_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_0_bits_source = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0; // @[Xbar.scala:352:24]
wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [3:0] in_1_a_bits_source = 4'h8; // @[Xbar.scala:159:18]
wire [3:0] _in_1_a_bits_source_T = 4'h8; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_1_0_bits_source = 4'h8; // @[Xbar.scala:352:24]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [7:0] beatsAI_decode_1 = 8'h3; // @[Edges.scala:220:59]
wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [15:0] in_1_b_bits_mask = 16'h0; // @[Xbar.scala:159:18]
wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_e_ready; // @[MixedNode.scala:551:17]
wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_b_ready; // @[MixedNode.scala:542:17]
wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9]
wire anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9]
wire anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [2:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18]
wire in_0_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9]
wire [2:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9]
wire [15:0] in_0_b_bits_mask; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] in_0_b_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9]
wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9]
wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [2:0] _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [127:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_e_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9]
wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18]
wire [3:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19]
wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire [15:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19]
wire [127:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_0_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [127:0] out_0_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19]
wire out_0_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9]
wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18]
wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18]
wire [15:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24]
assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18]
wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [3:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire [3:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [3:0] in_0_b_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_b_bits_source_T = in_0_b_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
wire [15:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [127:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19]
assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19]
assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19]
assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19]
assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire [2:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _requestBOI_T = out_0_b_bits_source[3]; // @[Xbar.scala:216:19]
wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54]
wire requestBOI_0_1 = out_0_b_bits_source == 4'h8; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54]
wire [2:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[3]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire requestDOI_0_1 = out_0_d_bits_source == 4'h8; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73]
wire [3:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsBO_decode = _beatsBO_decode_T_2[11:4]; // @[package.scala:243:46]
wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19]
wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}]
wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsCI_decode = _beatsCI_decode_T_2[11:4]; // @[package.scala:243:46]
wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [7:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73]
assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73]
assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
reg [7:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_46( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_27( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_27 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_27 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_42 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_10( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Plic.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
}
| module TLPLIC( // @[Plic.scala:132:9]
input clock, // @[Plic.scala:132:9]
input reset, // @[Plic.scala:132:9]
input auto_int_in_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_0, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire _fanin_io_dev; // @[Plic.scala:189:27]
wire _fanin_io_max; // @[Plic.scala:189:27]
wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27]
wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9]
wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9]
wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9]
wire _out_T_49 = reset; // @[Plic.scala:298:19]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9]
wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55]
wire _out_T_15 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_3 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_24 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_25 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_5 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_6 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_7 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [31:0] _out_prepend_T_4 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [22:0] out_maskMatch = 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9]
wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9]
wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_int_out_0_0; // @[Plic.scala:132:9]
wire auto_in_a_ready_0; // @[Plic.scala:132:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9]
wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9]
wire [11:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9]
wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9]
wire auto_in_d_valid_0; // @[Plic.scala:132:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9]
wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9]
wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9]
wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9]
wire _intnodeOut_0_T; // @[Plic.scala:193:60]
assign auto_int_out_0_0 = intnodeOut_0; // @[Plic.scala:132:9]
reg priority_0; // @[Plic.scala:167:31]
reg threshold_0; // @[Plic.scala:170:31]
wire _out_T_35 = threshold_0; // @[RegisterRouter.scala:87:24]
reg pending_0; // @[Plic.scala:172:26]
reg enables_0_0; // @[Plic.scala:178:26]
wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28]
wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52]
wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}]
reg maxDevs_0; // @[Plic.scala:185:22]
wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40]
reg intnodeOut_0_REG; // @[Plic.scala:193:45]
assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}]
assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60]
wire out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire claimer_0; // @[Plic.scala:250:23]
wire claiming = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49]
wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49]
wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}]
wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27]
wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}]
wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27]
wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}]
wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18]
wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34]
wire _out_completer_0_T_2; // @[Plic.scala:301:35]
wire completer_0; // @[Plic.scala:267:25]
wire _out_completerDev_T; // @[package.scala:163:13]
wire completerDev; // @[Plic.scala:269:28]
wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49]
wire [1:0] _completedDevs_T = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _completedDevs_T_1 = _completedDevs_T; // @[OneHot.scala:65:{12,27}]
wire [1:0] completedDevs = completer_0 ? _completedDevs_T_1 : 2'h0; // @[OneHot.scala:65:27]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire [22:0] out_findex = out_front_bits_index & 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9FF; // @[RegisterRouter.scala:87:24]
wire _GEN = out_findex == 23'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_4 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_6 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_24 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_rimask_T_3 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_wimask_T_3 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_romask_T_3 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_womask_T_3 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_37 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_42 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_1 = {1'h0, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_44 = {30'h0, out_prepend_1}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_45 = _out_T_44; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_45; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_4 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_4 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_4 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_4 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
assign claimer_0 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_46 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = _out_T_46[0]; // @[package.scala:163:13]
assign _out_completerDev_T = _out_T_46[0]; // @[package.scala:163:13]
wire _out_T_48 = completerDev == _out_T_47; // @[package.scala:163:13]
wire _out_T_50 = ~_out_T_49; // @[Plic.scala:298:19]
wire _out_T_51 = ~_out_T_48; // @[Plic.scala:298:{19,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncSyncCrossingSink_n1x2_2( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_in_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_out_0, // @[LazyModuleImp.scala:107:25]
output auto_out_1 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire nodeOut_1; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
wire auto_out_1_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File AtomicAutomata.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.util.leftOR
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operations.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
val node = TLAdapterNode(
managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
m.v1copy(
supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical),
mayDenyGet = m.mayDenyGet || m.mayDenyPut)
})})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes
// To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, beatBytes)
val managersNeedingHelp = managers.filter { m =>
m.supportsPutFull.contains(ourSupport) &&
m.supportsGet.contains(ourSupport) &&
((logical && !m.supportsLogical .contains(ourSupport)) ||
(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
!passthrough) // we will do atomics for everyone we can
}
// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n"))
// We cannot add atomics to a non-FIFO manager
managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
// We need to preserve FIFO semantics across FIFO domains, not managers
// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
// Don't overprovision the CAM
val camSize = min(domainsNeedingHelp.size, concurrency)
// Compact the fifoIds to only those we care about
def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)
// CAM entry state machine
val FREE = 0.U // unused waiting on Atomic from A
val GET = 3.U // Get sent down A waiting on AccessDataAck from D
val AMO = 2.U // AccessDataAck sent up D waiting for A availability
val ACK = 1.U // Put sent down A waiting for PutAck from D
val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size)
// Do we need to do anything at all?
if (camSize > 0) {
val initval = Wire(new TLAtomicAutomata.CAM_S(params))
initval.state := FREE
val cam_s = RegInit(VecInit.fill(camSize)(initval))
val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params)))
val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params)))
val cam_free = cam_s.map(_.state === FREE)
val cam_amo = cam_s.map(_.state === AMO)
val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries
// Can the manager already handle this message?
val a_address = edgeIn.address(in.a.bits)
val a_size = edgeIn.size(in.a.bits)
val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size)
val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size)
val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B))
// Must we do a Put?
val a_cam_any_put = cam_amo.reduce(_ || _)
val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init
val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
val a_cam_a = PriorityMux(cam_amo, cam_a)
val a_cam_d = PriorityMux(cam_amo, cam_d)
val a_a = a_cam_a.bits.data
val a_d = a_cam_d.data
// Does the A request conflict with an inflight AMO?
val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U)
val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
// (Where) are we are allocating in the CAM?
val a_cam_any_free = cam_free.reduce(_ || _)
val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init
val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
// Logical AMO
val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
// Arithmetic AMO
val unsigned = a_cam_a.bits.param(1)
val take_max = a_cam_a.bits.param(0)
val adder = a_cam_a.bits.param(2)
val mask = a_cam_a.bits.mask
val signSel = ~(~mask | (mask >> 1))
val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a
val a_d_ext = (a_d & wide_mask) | signext_d
val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
val adder_out = a_a_ext + a_d_inv
val h = 8*beatBytes-1 // now sign-extended; use biggest bit
val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
val pick_a = take_max === a_bigger
val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d))
// AMO result data
val amo_data =
if (!logical) arith_out else
if (!arithmetic) logic_out else
Mux(a_cam_a.bits.opcode(0), logic_out, arith_out)
// Potentially mutate the message from inner
val source_i = Wire(chiselTypeOf(in.a))
val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
in.a.ready := source_i.ready && a_allow
source_i.valid := in.a.valid && a_allow
source_i.bits := in.a.bits
when (!a_isSupported) { // minimal mux difference
source_i.bits.opcode := TLMessages.Get
source_i.bits.param := 0.U
}
// Potentially take the message from the CAM
val source_c = Wire(chiselTypeOf(in.a))
source_c.valid := a_cam_any_put
source_c.bits := edgeOut.Put(
fromSource = a_cam_a.bits.source,
toAddress = edgeIn.address(a_cam_a.bits),
lgSize = a_cam_a.bits.size,
data = amo_data,
corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2
source_c.bits.user :<= a_cam_a.bits.user
source_c.bits.echo :<= a_cam_a.bits.echo
// Finishing an AMO from the CAM has highest priority
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i))
// Capture the A state into the CAM
when (source_i.fire && !a_isSupported) {
(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
when (en) {
r.fifoId := a_fifoId
r.bits := in.a.bits
r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
TLAtomics.AND -> 0x8.U,
TLAtomics.OR -> 0xe.U,
TLAtomics.XOR -> 0x6.U,
TLAtomics.SWAP -> 0xc.U))
}
}
(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := GET
}
}
}
// Advance the put state
when (source_c.fire) {
(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := ACK
}
}
}
// We need to deal with a potential D response in the same cycle as the A request
val d_first = edgeOut.first(out.d)
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied))
val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
val d_ack = out.d.bits.opcode === TLMessages.AccessAck
when (out.d.fire && d_first) {
(d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) {
r.data := out.d.bits.data
r.denied := out.d.bits.denied
r.corrupt := out.d.bits.corrupt
}
}
(d_cam_sel zip cam_s) foreach { case (en, r) =>
when (en) {
// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
r.state := Mux(d_ackd, AMO, FREE)
}
}
}
val d_drop = d_first && d_ackd && d_cam_sel_any
val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _)
in.d.valid := out.d.valid && !d_drop
out.d.ready := in.d.ready || d_drop
in.d.bits := out.d.bits
when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data
in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied
in.d.bits.denied := d_cam_denied || out.d.bits.denied
}
} else {
out.a.valid := in.a.valid
in.a.ready := out.a.ready
out.a.bits := in.a.bits
in.d.valid := out.d.valid
out.d.ready := in.d.ready
in.d.bits := out.d.bits
}
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAtomicAutomata
{
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
})
atomics.node
}
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
class CAM_S(val params: CAMParams) extends Bundle {
val state = UInt(2.W)
}
class CAM_A(val params: CAMParams) extends Bundle {
val bits = new TLBundleA(params.a)
val fifoId = UInt(log2Up(params.domainsNeedingHelp).W)
val lut = UInt(4.W)
}
class CAM_D(val params: CAMParams) extends Bundle {
val data = UInt(params.a.dataBits.W)
val denied = Bool()
val corrupt = Bool()
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
| module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83]
wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60]
wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85]
wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canLogical_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canArithmetic_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _source_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29]
wire _source_c_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27]
wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [6:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9]
wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28]
wire [6:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28]
wire [28:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28]
wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28]
wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28]
wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [6:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17]
wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34]
reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
wire [6:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17]
reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44]
wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58]
wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82]
wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire cam_amo_0; // @[AtomicAutomata.scala:87:44]
assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44]
wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68]
assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68]
wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56]
wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80]
wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28]
wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49]
wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}]
wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96]
wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49]
wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire _a_canLogical_T_1; // @[Parameters.scala:92:38]
assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38]
assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29]
wire [28:0] _GEN_1 = {nodeIn_a_bits_address[28:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_4; // @[Parameters.scala:137:31]
assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46]
wire _a_canLogical_T_8 = _a_canLogical_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_2 = nodeIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_9; // @[Parameters.scala:137:31]
assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46]
wire _a_canLogical_T_13 = _a_canLogical_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13; // @[Parameters.scala:685:42]
wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canLogical_T_47 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46]
wire _a_canLogical_T_21 = _a_canLogical_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_3 = {nodeIn_a_bits_address[28:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_22; // @[Parameters.scala:137:31]
assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46]
wire _a_canLogical_T_26 = _a_canLogical_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_4 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_27; // @[Parameters.scala:137:31]
assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46]
wire _a_canLogical_T_31 = _a_canLogical_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_5 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_32; // @[Parameters.scala:137:31]
assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46]
wire _a_canLogical_T_36 = _a_canLogical_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_6 = {nodeIn_a_bits_address[28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_37; // @[Parameters.scala:137:31]
assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46]
wire _a_canLogical_T_41 = _a_canLogical_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_42 = _a_canLogical_T_21 | _a_canLogical_T_26; // @[Parameters.scala:685:42]
wire _a_canLogical_T_43 = _a_canLogical_T_42 | _a_canLogical_T_31; // @[Parameters.scala:685:42]
wire _a_canLogical_T_44 = _a_canLogical_T_43 | _a_canLogical_T_36; // @[Parameters.scala:685:42]
wire _a_canLogical_T_45 = _a_canLogical_T_44 | _a_canLogical_T_41; // @[Parameters.scala:685:42]
wire _a_canLogical_T_48 = _a_canLogical_T_47; // @[Parameters.scala:686:26]
wire a_canLogical = _a_canLogical_T_48; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29]
wire [29:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canArithmetic_T_47 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_42 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_43 = _a_canArithmetic_T_42 | _a_canArithmetic_T_31; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_44 = _a_canArithmetic_T_43 | _a_canArithmetic_T_36; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_45 = _a_canArithmetic_T_44 | _a_canArithmetic_T_41; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47; // @[Parameters.scala:686:26]
wire a_canArithmetic = _a_canArithmetic_T_48; // @[Parameters.scala:686:26]
wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47]
wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47]
wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63]
wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]
wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}]
wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57]
wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28]
wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42]
wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42]
wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39]
wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25]
wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39]
wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}]
wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}]
wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29]
wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29]
wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38]
wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}]
wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}]
wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38]
wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}]
wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}]
wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17]
wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17]
wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17]
wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17]
wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17]
wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17]
wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17]
wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17]
wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40]
wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40]
wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17]
wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17]
wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17]
wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17]
wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17]
wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17]
wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17]
wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17]
wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40]
wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40]
wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40]
wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28]
wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}]
wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28]
wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}]
wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43]
wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]
wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33]
wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33]
wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49]
wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35]
wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}]
wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50]
wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}]
wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65]
wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}]
wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}]
wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31]
wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]
wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]
wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34]
wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]
wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17]
wire _source_i_ready_T; // @[Arbiter.scala:94:31]
wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38]
wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28]
wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28]
wire source_i_ready; // @[AtomicAutomata.scala:154:28]
wire source_i_valid; // @[AtomicAutomata.scala:154:28]
wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23]
wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53]
wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}]
assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38]
assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]
assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]
wire _source_c_ready_T; // @[Arbiter.scala:94:31]
wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17]
wire source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28]
wire [6:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28]
wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28]
wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28]
wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28]
wire source_c_ready; // @[AtomicAutomata.scala:165:28]
wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45]
assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17]
wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [28:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[28:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _source_c_bits_legal_T_57 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [29:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 30'h1A112000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[28:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 30'h1A103000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2010000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_34 = {cam_a_0_bits_address[28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_39 = cam_a_0_bits_address ^ 29'h10000000; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_40 = {1'h0, _source_c_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_42 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_44 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_45 = _source_c_bits_legal_T_44 | _source_c_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_46 = _source_c_bits_legal_T_45 | _source_c_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 | _source_c_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47 | _source_c_bits_legal_T_43; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_48; // @[Parameters.scala:684:{29,54}, :685:42]
wire [28:0] _source_c_bits_legal_T_51 = {cam_a_0_bits_address[28:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_52 = {1'h0, _source_c_bits_legal_T_51}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_53 = _source_c_bits_legal_T_52 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_54 = _source_c_bits_legal_T_53; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_55 = _source_c_bits_legal_T_54 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_58 = _source_c_bits_legal_T_57 | _source_c_bits_legal_T_49; // @[Parameters.scala:684:54, :686:26]
wire source_c_bits_legal = _source_c_bits_legal_T_58; // @[Parameters.scala:686:26]
assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17]
assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17]
assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17]
assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17]
assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46]
wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_8( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1339 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1339; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1339; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1412 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1412; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1265 = _T_1339 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1265 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1265 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1265 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1265 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1265 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1311 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1311 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1280 = _T_1412 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1280 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1280 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1280 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1383 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1383 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1365 = _T_1412 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1365 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1365 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1365 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_146( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_161 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Metadata.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.util._
object ClientStates {
val width = 2
def Nothing = 0.U(width.W)
def Branch = 1.U(width.W)
def Trunk = 2.U(width.W)
def Dirty = 3.U(width.W)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch
}
object MemoryOpCategories extends MemoryOpConstants {
def wr = Cat(true.B, true.B) // Op actually writes
def wi = Cat(false.B, true.B) // Future op will write
def rd = Cat(false.B, false.B) // Op only reads
def categorize(cmd: UInt): UInt = {
val cat = Cat(isWrite(cmd), isWriteIntent(cmd))
//assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.")
cat
}
}
/** Stores the client-side coherence information,
* such as permissions on the data and whether the data is dirty.
* Its API can be used to make TileLink messages in response to
* memory operations, cache control oeprations, or Probe messages.
*/
class ClientMetadata extends Bundle {
/** Actual state information stored in this bundle */
val state = UInt(ClientStates.width.W)
/** Metadata equality */
def ===(rhs: UInt): Bool = state === rhs
def ===(rhs: ClientMetadata): Bool = state === rhs.state
def =/=(rhs: ClientMetadata): Bool = !this.===(rhs)
/** Is the block's data present in this cache */
def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing
/** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */
private def growStarter(cmd: UInt): (Bool, UInt) = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
MuxTLookup(Cat(c, state), (false.B, 0.U), Seq(
//(effect, am now) -> (was a hit, next)
Cat(rd, Dirty) -> (true.B, Dirty),
Cat(rd, Trunk) -> (true.B, Trunk),
Cat(rd, Branch) -> (true.B, Branch),
Cat(wi, Dirty) -> (true.B, Dirty),
Cat(wi, Trunk) -> (true.B, Trunk),
Cat(wr, Dirty) -> (true.B, Dirty),
Cat(wr, Trunk) -> (true.B, Dirty),
//(effect, am now) -> (was a miss, param)
Cat(rd, Nothing) -> (false.B, NtoB),
Cat(wi, Branch) -> (false.B, BtoT),
Cat(wi, Nothing) -> (false.B, NtoT),
Cat(wr, Branch) -> (false.B, BtoT),
Cat(wr, Nothing) -> (false.B, NtoT)))
}
/** Determine what state to go to after miss based on Grant param
* For now, doesn't depend on state (which may have been Probed).
*/
private def growFinisher(cmd: UInt, param: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
//assert(c === rd || param === toT, "Client was expecting trunk permissions.")
MuxLookup(Cat(c, param), Nothing)(Seq(
//(effect param) -> (next)
Cat(rd, toB) -> Branch,
Cat(rd, toT) -> Trunk,
Cat(wi, toT) -> Trunk,
Cat(wr, toT) -> Dirty))
}
/** Does this cache have permissions on this block sufficient to perform op,
* and what to do next (Acquire message param or updated metadata). */
def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = growStarter(cmd)
(r._1, r._2, ClientMetadata(r._2))
}
/** Does a secondary miss on the block require another Acquire message */
def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = {
import MemoryOpCategories._
val r1 = growStarter(first_cmd)
val r2 = growStarter(second_cmd)
val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd)
val hit_again = r1._1 && r2._1
val dirties = categorize(second_cmd) === wr
val biggest_grow_param = Mux(dirties, r2._2, r1._2)
val dirtiest_state = ClientMetadata(biggest_grow_param)
val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd)
(needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd)
}
/** Metadata change on a returned Grant */
def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param))
/** Determine what state to go to based on Probe param */
private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = {
import ClientStates._
import TLPermissions._
MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq(
//(wanted, am now) -> (hasDirtyData resp, next)
Cat(toT, Dirty) -> (true.B, TtoT, Trunk),
Cat(toT, Trunk) -> (false.B, TtoT, Trunk),
Cat(toT, Branch) -> (false.B, BtoB, Branch),
Cat(toT, Nothing) -> (false.B, NtoN, Nothing),
Cat(toB, Dirty) -> (true.B, TtoB, Branch),
Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade
Cat(toB, Branch) -> (false.B, BtoB, Branch),
Cat(toB, Nothing) -> (false.B, NtoN, Nothing),
Cat(toN, Dirty) -> (true.B, TtoN, Nothing),
Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Nothing) -> (false.B, NtoN, Nothing)))
}
/** Translate cache control cmds into Probe param */
private def cmdToPermCap(cmd: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
MuxLookup(cmd, toN)(Seq(
M_FLUSH -> toN,
M_PRODUCE -> toB,
M_CLEAN -> toT))
}
def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(cmdToPermCap(cmd))
(r._1, r._2, ClientMetadata(r._3))
}
def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(param)
(r._1, r._2, ClientMetadata(r._3))
}
}
/** Factories for ClientMetadata, including on reset */
object ClientMetadata {
def apply(perm: UInt) = {
val meta = Wire(new ClientMetadata)
meta.state := perm
meta
}
def onReset = ClientMetadata(ClientStates.Nothing)
def maximum = ClientMetadata(ClientStates.Dirty)
}
File HellaCache.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3.{dontTouch, _}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.AMBAProtField
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType}
import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters}
import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata}
import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle}
import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt}
import scala.collection.mutable.ListBuffer
case class DCacheParams(
nSets: Int = 64,
nWays: Int = 4,
rowBits: Int = 64,
subWordBits: Option[Int] = None,
replacementPolicy: String = "random",
nTLBSets: Int = 1,
nTLBWays: Int = 32,
nTLBBasePageSectors: Int = 4,
nTLBSuperpages: Int = 4,
tagECC: Option[String] = None,
dataECC: Option[String] = None,
dataECCBytes: Int = 1,
nMSHRs: Int = 1,
nSDQ: Int = 17,
nRPQ: Int = 16,
nMMIOs: Int = 1,
blockBytes: Int = 64,
separateUncachedResp: Boolean = false,
acquireBeforeRelease: Boolean = false,
pipelineWayMux: Boolean = false,
clockGate: Boolean = false,
scratch: Option[BigInt] = None) extends L1CacheParams {
def tagCode: Code = Code.fromString(tagECC)
def dataCode: Code = Code.fromString(dataECC)
def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
def replacement = new RandomReplacement(nWays)
def silentDrop: Boolean = !acquireBeforeRelease
require((!scratch.isDefined || nWays == 1),
"Scratchpad only allowed in direct-mapped cache.")
require((!scratch.isDefined || nMSHRs == 0),
"Scratchpad only allowed in blocking cache.")
if (scratch.isEmpty)
require(isPow2(nSets), s"nSets($nSets) must be pow2")
}
trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {
val cacheParams = tileParams.dcache.get
val cfg = cacheParams
def wordBits = coreDataBits
def wordBytes = coreDataBytes
def subWordBits = cacheParams.subWordBits.getOrElse(wordBits)
def subWordBytes = subWordBits / 8
def wordOffBits = log2Up(wordBytes)
def beatBytes = cacheBlockBytes / cacheDataBeats
def beatWords = beatBytes / wordBytes
def beatOffBits = log2Up(beatBytes)
def idxMSB = untagBits-1
def idxLSB = blockOffBits
def offsetmsb = idxLSB-1
def offsetlsb = wordOffBits
def rowWords = rowBits/wordBits
def doNarrowRead = coreDataBits * nWays % rowBits == 0
def eccBytes = cacheParams.dataECCBytes
val eccBits = cacheParams.dataECCBytes * 8
val encBits = cacheParams.dataCode.width(eccBits)
val encWordBits = encBits * (wordBits / eccBits)
def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only
def encRowBits = encDataBits*rowWords
def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed
def lrscBackoff = 3 // disallow LRSC reacquisition briefly
def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant
def nIOMSHRs = cacheParams.nMMIOs
def maxUncachedInFlight = cacheParams.nMMIOs
def dataScratchpadSize = cacheParams.dataScratchpadBytes
require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)")
if (!usingDataScratchpad)
require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)")
// would need offset addr for puts if data width < xlen
require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)")
}
abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
with HasL1HellaCacheParameters
abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasL1HellaCacheParameters
/** Bundle definitions for HellaCache interfaces */
trait HasCoreMemOp extends HasL1HellaCacheParameters {
val addr = UInt(coreMaxAddrBits.W)
val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W))
val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W)
val cmd = UInt(M_SZ.W)
val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W)
val signed = Bool()
val dprv = UInt(PRV.SZ.W)
val dv = Bool()
}
trait HasCoreData extends HasCoreParameters {
val data = UInt(coreDataBits.W)
val mask = UInt(coreDataBytes.W)
}
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {
val phys = Bool()
val no_resp = Bool() // The dcache may omit generating a response for this request
val no_alloc = Bool()
val no_xcpt = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
val has_data = Bool()
val data_word_bypass = UInt(coreDataBits.W)
val data_raw = UInt(coreDataBits.W)
val store_data = UInt(coreDataBits.W)
}
class AlignmentExceptions extends Bundle {
val ld = Bool()
val st = Bool()
}
class HellaCacheExceptions extends Bundle {
val ma = new AlignmentExceptions
val pf = new AlignmentExceptions
val gf = new AlignmentExceptions
val ae = new AlignmentExceptions
}
class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData
class HellaCachePerfEvents extends Bundle {
val acquire = Bool()
val release = Bool()
val grant = Bool()
val tlbMiss = Bool()
val blocked = Bool()
val canAcceptStoreThenLoad = Bool()
val canAcceptStoreThenRMW = Bool()
val canAcceptLoadThenLoad = Bool()
val storeBufferEmptyAfterLoad = Bool()
val storeBufferEmptyAfterStore = Bool()
}
// interface between D$ and processor/DTLB
class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
val req = Decoupled(new HellaCacheReq)
val s1_kill = Output(Bool()) // kill previous cycle's req
val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req
val s2_nack = Input(Bool()) // req from two cycles ago is rejected
val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint)
val s2_kill = Output(Bool()) // kill req from two cycles ago
val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO
val s2_paddr = Input(UInt(paddrBits.W)) // translated address
val resp = Flipped(Valid(new HellaCacheResp))
val replay_next = Input(Bool())
val s2_xcpt = Input(new HellaCacheExceptions)
val s2_gpa = Input(UInt(vaddrBitsExtended.W))
val s2_gpa_is_pte = Input(Bool())
val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))
val ordered = Input(Bool())
val store_pending = Input(Bool()) // there is a store in a store buffer somewhere
val perf = Input(new HellaCachePerfEvents())
val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?
val clock_enabled = Input(Bool()) // is D$ currently being clocked?
}
/** Base classes for Diplomatic TL2 HellaCaches */
abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule
with HasNonDiplomaticTileParameters {
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache",
sourceId = IdRange(0, 1 max cfg.nMSHRs),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${tileId} DCache MMIO",
sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),
requestFifo = true))
def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = cacheClientParameters ++ mmioClientParameters,
minLatency = 1,
requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField())))))
val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())
val module: HellaCacheModule
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {
val cpu = Flipped(new HellaCacheIO)
val ptw = new TLBPTWIO()
val errors = new DCacheErrors
val tlb_port = new DCacheTLBPort
}
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val edge: TLEdgeOut = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle)
val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle)
val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle)
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
dontTouch(io.cpu.s1_data)
require(rowBits == edge.bundle.dataBits)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+
s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}")
}
}
/** Support overriding which HellaCache is instantiated */
case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply)
object HellaCacheFactory {
def apply(tile: BaseTile)(p: Parameters): HellaCache = {
if (tile.tileParams.dcache.get.nMSHRs == 0)
new DCache(tile.tileId, tile.crossing)(p)
else
new NonBlockingDCache(tile.tileId)(p)
}
}
/** Mix-ins for constructing tiles that have a HellaCache */
trait HasHellaCache { this: BaseTile =>
val module: HasHellaCacheModule
implicit val p: Parameters
var nDCachePorts = 0
lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p))
tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node
dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }
dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }
InModuleBody {
dcache.module.io.tlb_port := DontCare
}
}
trait HasHellaCacheModule {
val outer: HasHellaCache with HasTileParameters
implicit val p: Parameters
val dcachePorts = ListBuffer[HellaCacheIO]()
val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))
outer.dcache.module.io.cpu <> dcacheArb.io.mem
}
/** Metadata array used for all HellaCaches */
class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val coh = new ClientMetadata
val tag = UInt(tagBits.W)
}
object L1Metadata {
def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
val meta = Wire(new L1Metadata)
meta.tag := tag
meta.coh := coh
meta
}
}
class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val idx = UInt(idxBits.W)
val way_en = UInt(nWays.W)
val tag = UInt(tagBits.W)
}
class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {
val data = new L1Metadata
}
class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val rstVal = onReset()
val io = IO(new Bundle {
val read = Flipped(Decoupled(new L1MetaReadReq))
val write = Flipped(Decoupled(new L1MetaWriteReq))
val resp = Output(Vec(nWays, rstVal.cloneType))
})
val rst_cnt = RegInit(0.U(log2Up(nSets+1).W))
val rst = rst_cnt < nSets.U
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools
val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools
when (rst) { rst_cnt := rst_cnt+1.U }
val metabits = rstVal.getWidth
val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W)))
val wen = rst || io.write.valid
when (wen) {
tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)
}
io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))
io.read.ready := !wen // so really this could be a 6T RAM
io.write.ready := !rst
}
| module L1MetadataArray( // @[HellaCache.scala:322:7]
input clock, // @[HellaCache.scala:322:7]
input reset, // @[HellaCache.scala:322:7]
output io_read_ready, // @[HellaCache.scala:324:14]
input io_read_valid, // @[HellaCache.scala:324:14]
input [5:0] io_read_bits_idx, // @[HellaCache.scala:324:14]
input [19:0] io_read_bits_tag, // @[HellaCache.scala:324:14]
output io_write_ready, // @[HellaCache.scala:324:14]
input io_write_valid, // @[HellaCache.scala:324:14]
input [5:0] io_write_bits_idx, // @[HellaCache.scala:324:14]
input [7:0] io_write_bits_way_en, // @[HellaCache.scala:324:14]
input [19:0] io_write_bits_tag, // @[HellaCache.scala:324:14]
input [1:0] io_write_bits_data_coh_state, // @[HellaCache.scala:324:14]
input [19:0] io_write_bits_data_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_0_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_0_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_1_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_1_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_2_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_2_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_3_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_3_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_4_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_4_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_5_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_5_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_6_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_6_tag, // @[HellaCache.scala:324:14]
output [1:0] io_resp_7_coh_state, // @[HellaCache.scala:324:14]
output [19:0] io_resp_7_tag // @[HellaCache.scala:324:14]
);
wire tag_array_MPORT_1_en; // @[Decoupled.scala:51:35]
wire [5:0] tag_array_MPORT_addr; // @[HellaCache.scala:342:20]
wire [175:0] _tag_array_RW0_rdata; // @[HellaCache.scala:339:30]
wire io_read_valid_0 = io_read_valid; // @[HellaCache.scala:322:7]
wire [5:0] io_read_bits_idx_0 = io_read_bits_idx; // @[HellaCache.scala:322:7]
wire [19:0] io_read_bits_tag_0 = io_read_bits_tag; // @[HellaCache.scala:322:7]
wire io_write_valid_0 = io_write_valid; // @[HellaCache.scala:322:7]
wire [5:0] io_write_bits_idx_0 = io_write_bits_idx; // @[HellaCache.scala:322:7]
wire [7:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[HellaCache.scala:322:7]
wire [19:0] io_write_bits_tag_0 = io_write_bits_tag; // @[HellaCache.scala:322:7]
wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[HellaCache.scala:322:7]
wire [19:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[HellaCache.scala:322:7]
wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [19:0] rstVal_tag = 20'h0; // @[HellaCache.scala:305:20]
wire rmask_0 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_1 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_2 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_3 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_4 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_5 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_6 = 1'h1; // @[HellaCache.scala:335:78]
wire rmask_7 = 1'h1; // @[HellaCache.scala:335:78]
wire [7:0] io_read_bits_way_en = 8'hFF; // @[HellaCache.scala:322:7, :324:14]
wire [7:0] _rmask_T_1 = 8'hFF; // @[HellaCache.scala:322:7, :324:14, :335:70]
wire [7:0] _rmask_T_2 = 8'hFF; // @[HellaCache.scala:322:7, :324:14, :335:18]
wire _io_read_ready_T; // @[HellaCache.scala:346:20]
wire _io_write_ready_T; // @[HellaCache.scala:347:21]
wire [7:0] _wmask_T_1 = io_write_bits_way_en_0; // @[HellaCache.scala:322:7, :334:71]
wire io_read_ready_0; // @[HellaCache.scala:322:7]
wire io_write_ready_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_0_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_0_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_1_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_1_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_2_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_2_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_3_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_3_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_4_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_4_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_5_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_5_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_6_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_6_tag_0; // @[HellaCache.scala:322:7]
wire [1:0] io_resp_7_coh_state_0; // @[HellaCache.scala:322:7]
wire [19:0] io_resp_7_tag_0; // @[HellaCache.scala:322:7]
reg [6:0] rst_cnt; // @[HellaCache.scala:330:24]
wire rst = ~(rst_cnt[6]); // @[HellaCache.scala:330:24, :331:21]
wire _wmask_T = rst; // @[HellaCache.scala:331:21, :334:23]
wire _rmask_T = rst; // @[HellaCache.scala:331:21, :335:23]
wire [6:0] waddr = rst ? rst_cnt : {1'h0, io_write_bits_idx_0}; // @[HellaCache.scala:322:7, :330:24, :331:21, :332:18]
wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[HellaCache.scala:322:7, :331:21, :333:18]
wire [19:0] _wdata_T_tag = rst ? 20'h0 : io_write_bits_data_tag_0; // @[HellaCache.scala:322:7, :331:21, :333:18]
wire [21:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[HellaCache.scala:333:{18,52}]
wire [7:0] _wmask_T_2 = _wmask_T ? 8'hFF : _wmask_T_1; // @[HellaCache.scala:322:7, :324:14, :334:{18,23,71}]
wire wmask_0 = _wmask_T_2[0]; // @[HellaCache.scala:334:{18,79}]
wire wmask_1 = _wmask_T_2[1]; // @[HellaCache.scala:334:{18,79}]
wire wmask_2 = _wmask_T_2[2]; // @[HellaCache.scala:334:{18,79}]
wire wmask_3 = _wmask_T_2[3]; // @[HellaCache.scala:334:{18,79}]
wire wmask_4 = _wmask_T_2[4]; // @[HellaCache.scala:334:{18,79}]
wire wmask_5 = _wmask_T_2[5]; // @[HellaCache.scala:334:{18,79}]
wire wmask_6 = _wmask_T_2[6]; // @[HellaCache.scala:334:{18,79}]
wire wmask_7 = _wmask_T_2[7]; // @[HellaCache.scala:334:{18,79}]
wire [7:0] _rst_cnt_T = {1'h0, rst_cnt} + 8'h1; // @[HellaCache.scala:330:24, :332:18, :336:34]
wire [6:0] _rst_cnt_T_1 = _rst_cnt_T[6:0]; // @[HellaCache.scala:336:34]
wire wen; // @[HellaCache.scala:340:17]
assign wen = rst | io_write_valid_0; // @[HellaCache.scala:322:7, :331:21, :340:17]
assign tag_array_MPORT_addr = waddr[5:0]; // @[HellaCache.scala:332:18, :342:20]
assign tag_array_MPORT_1_en = io_read_ready_0 & io_read_valid_0; // @[Decoupled.scala:51:35]
assign io_resp_0_tag_0 = _tag_array_RW0_rdata[19:0]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_0_coh_state_0 = _tag_array_RW0_rdata[21:20]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_1_tag_0 = _tag_array_RW0_rdata[41:22]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_1_coh_state_0 = _tag_array_RW0_rdata[43:42]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_2_tag_0 = _tag_array_RW0_rdata[63:44]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_2_coh_state_0 = _tag_array_RW0_rdata[65:64]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_3_tag_0 = _tag_array_RW0_rdata[85:66]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_3_coh_state_0 = _tag_array_RW0_rdata[87:86]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_4_tag_0 = _tag_array_RW0_rdata[107:88]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_4_coh_state_0 = _tag_array_RW0_rdata[109:108]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_5_tag_0 = _tag_array_RW0_rdata[129:110]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_5_coh_state_0 = _tag_array_RW0_rdata[131:130]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_6_tag_0 = _tag_array_RW0_rdata[151:132]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_6_coh_state_0 = _tag_array_RW0_rdata[153:152]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_7_tag_0 = _tag_array_RW0_rdata[173:154]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign io_resp_7_coh_state_0 = _tag_array_RW0_rdata[175:174]; // @[HellaCache.scala:322:7, :339:30, :344:75]
assign _io_read_ready_T = ~wen; // @[HellaCache.scala:340:17, :346:20]
assign io_read_ready_0 = _io_read_ready_T; // @[HellaCache.scala:322:7, :346:20]
assign _io_write_ready_T = ~rst; // @[HellaCache.scala:331:21, :347:21]
assign io_write_ready_0 = _io_write_ready_T; // @[HellaCache.scala:322:7, :347:21]
always @(posedge clock) begin // @[HellaCache.scala:322:7]
if (reset) // @[HellaCache.scala:322:7]
rst_cnt <= 7'h0; // @[HellaCache.scala:330:24]
else if (rst) // @[HellaCache.scala:331:21]
rst_cnt <= _rst_cnt_T_1; // @[HellaCache.scala:330:24, :336:34]
always @(posedge)
tag_array tag_array ( // @[HellaCache.scala:339:30]
.RW0_addr (wen ? tag_array_MPORT_addr : io_read_bits_idx_0), // @[HellaCache.scala:322:7, :339:30, :340:17, :342:20]
.RW0_en (tag_array_MPORT_1_en | wen), // @[Decoupled.scala:51:35]
.RW0_clk (clock),
.RW0_wmode (wen), // @[HellaCache.scala:340:17]
.RW0_wdata ({8{wdata}}), // @[HellaCache.scala:333:52, :339:30]
.RW0_rdata (_tag_array_RW0_rdata),
.RW0_wmask ({wmask_7, wmask_6, wmask_5, wmask_4, wmask_3, wmask_2, wmask_1, wmask_0}) // @[HellaCache.scala:334:79, :339:30]
); // @[HellaCache.scala:339:30]
assign io_read_ready = io_read_ready_0; // @[HellaCache.scala:322:7]
assign io_write_ready = io_write_ready_0; // @[HellaCache.scala:322:7]
assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_0_tag = io_resp_0_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_1_tag = io_resp_1_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_2_coh_state = io_resp_2_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_2_tag = io_resp_2_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_3_coh_state = io_resp_3_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_3_tag = io_resp_3_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_4_coh_state = io_resp_4_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_4_tag = io_resp_4_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_5_coh_state = io_resp_5_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_5_tag = io_resp_5_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_6_coh_state = io_resp_6_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_6_tag = io_resp_6_tag_0; // @[HellaCache.scala:322:7]
assign io_resp_7_coh_state = io_resp_7_coh_state_0; // @[HellaCache.scala:322:7]
assign io_resp_7_tag = io_resp_7_tag_0; // @[HellaCache.scala:322:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_348( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_92 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File tracegen.scala:
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, BundleBridgeSource}
import freechips.rocketchip.prci.{SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.subsystem._
import boom.v3.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
import boom.v3.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
import freechips.rocketchip.prci.ClockSinkParameters
class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
with MemoryOpConstants {
val io = IO(new Bundle {
val lsu = Flipped(new LSUCoreIO)
val tracegen = Flipped(new HellaCacheIO)
})
io.tracegen := DontCare
io.lsu := DontCare
io.lsu.tsc_reg := 0.U(1.W)
val rob_sz = numRobEntries
val rob = Reg(Vec(rob_sz, new HellaCacheReq))
val rob_respd = RegInit(VecInit((~(0.U(rob_sz.W))).asBools))
val rob_uop = Reg(Vec(rob_sz, new MicroOp))
val rob_bsy = RegInit(VecInit(0.U(rob_sz.W).asBools))
val rob_head = RegInit(0.U(log2Up(rob_sz).W))
val rob_tail = RegInit(0.U(log2Up(rob_sz).W))
val rob_wait_till_empty = RegInit(false.B)
val ready_for_amo = rob_tail === rob_head && io.lsu.fencei_rdy
when (ready_for_amo) {
rob_wait_till_empty := false.B
}
def WrapInc(idx: UInt, max: Int): UInt = {
Mux(idx === (max-1).U, 0.U, idx + 1.U)
}
io.tracegen.req.ready := (!rob_bsy(rob_tail) &&
!rob_wait_till_empty &&
(ready_for_amo || !(isAMO(io.tracegen.req.bits.cmd) || io.tracegen.req.bits.cmd === M_XLR || io.tracegen.req.bits.cmd === M_XSC)) &&
(WrapInc(rob_tail, rob_sz) =/= rob_head) &&
!(io.lsu.ldq_full(0) && isRead(io.tracegen.req.bits.cmd)) &&
!(io.lsu.stq_full(0) && isWrite(io.tracegen.req.bits.cmd))
)
val tracegen_uop = WireInit((0.U).asTypeOf(new MicroOp))
tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.rob_idx := rob_tail
tracegen_uop.uopc := io.tracegen.req.bits.tag
tracegen_uop.mem_size := io.tracegen.req.bits.size
tracegen_uop.mem_cmd := io.tracegen.req.bits.cmd
tracegen_uop.mem_signed := io.tracegen.req.bits.signed
tracegen_uop.ldq_idx := io.lsu.dis_ldq_idx(0)
tracegen_uop.stq_idx := io.lsu.dis_stq_idx(0)
tracegen_uop.is_amo := isAMO(io.tracegen.req.bits.cmd) || io.tracegen.req.bits.cmd === M_XSC
tracegen_uop.ctrl.is_load := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.ctrl.is_sta := isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.ctrl.is_std := isWrite(io.tracegen.req.bits.cmd)
io.lsu.dis_uops(0).valid := io.tracegen.req.fire
io.lsu.dis_uops(0).bits := tracegen_uop
when (io.tracegen.req.fire) {
rob_tail := WrapInc(rob_tail, rob_sz)
rob_bsy(rob_tail) := true.B
rob_uop(rob_tail) := tracegen_uop
rob_respd(rob_tail) := false.B
rob(rob_tail) := io.tracegen.req.bits
when (
isAMO(io.tracegen.req.bits.cmd) ||
io.tracegen.req.bits.cmd === M_XLR ||
io.tracegen.req.bits.cmd === M_XSC
) {
rob_wait_till_empty := true.B
}
}
io.lsu.fp_stdata.valid := false.B
io.lsu.fp_stdata.bits := DontCare
io.lsu.commit.valids(0) := (!rob_bsy(rob_head) && rob_head =/= rob_tail && rob_respd(rob_head))
io.lsu.commit.uops(0) := rob_uop(rob_head)
io.lsu.commit.rbk_valids(0) := false.B
io.lsu.commit.rollback := false.B
io.lsu.commit.fflags := DontCare
when (io.lsu.commit.valids(0)) {
rob_head := WrapInc(rob_head, rob_sz)
}
when (io.lsu.clr_bsy(0).valid) {
rob_bsy(io.lsu.clr_bsy(0).bits) := false.B
}
when (io.lsu.clr_unsafe(0).valid && rob(io.lsu.clr_unsafe(0).bits).cmd =/= M_XLR) {
rob_bsy(io.lsu.clr_unsafe(0).bits) := false.B
}
when (io.lsu.exe(0).iresp.valid) {
rob_bsy(io.lsu.exe(0).iresp.bits.uop.rob_idx) := false.B
}
assert(!io.lsu.lxcpt.valid)
io.lsu.exe(0).req.valid := RegNext(io.tracegen.req.fire)
io.lsu.exe(0).req.bits := DontCare
io.lsu.exe(0).req.bits.uop := RegNext(tracegen_uop)
io.lsu.exe(0).req.bits.addr := RegNext(io.tracegen.req.bits.addr)
io.lsu.exe(0).req.bits.data := RegNext(io.tracegen.req.bits.data)
io.tracegen.resp.valid := io.lsu.exe(0).iresp.valid
io.tracegen.resp.bits := DontCare
io.tracegen.resp.bits.tag := io.lsu.exe(0).iresp.bits.uop.uopc
io.tracegen.resp.bits.size := io.lsu.exe(0).iresp.bits.uop.mem_size
io.tracegen.resp.bits.data := io.lsu.exe(0).iresp.bits.data
val store_resp_idx = PriorityEncoder((0 until rob_sz) map {i =>
!rob_respd(i) && isWrite(rob(i).cmd)
})
val can_do_store_resp = ~rob_respd(store_resp_idx) && isWrite(rob(store_resp_idx).cmd) && !isRead(rob(store_resp_idx).cmd)
when (can_do_store_resp && !io.lsu.exe(0).iresp.valid) {
rob_respd(store_resp_idx) := true.B
io.tracegen.resp.valid := true.B
io.tracegen.resp.bits.tag := rob(store_resp_idx).tag
}
when (io.lsu.exe(0).iresp.valid) {
rob_respd(io.lsu.exe(0).iresp.bits.uop.rob_idx) := true.B
}
io.lsu.exe(0).fresp.ready := true.B
io.lsu.exe(0).iresp.ready := true.B
io.lsu.exception := false.B
io.lsu.fence_dmem := false.B
io.lsu.rob_pnr_idx := rob_tail
io.lsu.commit_load_at_rob_head := false.B
io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.v3.exu.BrUpdateMasks)
io.lsu.brupdate.b2.uop := DontCare
io.lsu.brupdate.b2.mispredict := false.B
io.lsu.brupdate.b2.taken := false.B
io.lsu.brupdate.b2.cfi_type := 0.U
io.lsu.brupdate.b2.pc_sel := 0.U
io.lsu.brupdate.b2.jalr_target := 0.U
io.lsu.brupdate.b2.target_offset := 0.S(2.W)
io.lsu.rob_head_idx := rob_head
io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy
}
case class BoomTraceGenTileAttachParams(
tileParams: BoomTraceGenParams,
crossingParams: HierarchicalElementCrossingParamsLike
) extends CanAttachTile {
type TileType = BoomTraceGenTile
val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams)
}
case class BoomTraceGenParams(
wordBits: Int,
addrBits: Int,
addrBag: List[BigInt],
maxRequests: Int,
memStart: BigInt,
numGens: Int,
dcache: Option[DCacheParams] = Some(DCacheParams()),
tileId: Int = 0
) extends InstantiableTileParams[BoomTraceGenTile]
{
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = {
new BoomTraceGenTile(this, crossing, lookup)
}
val core = RocketCoreParams(nPMPs = 0) //TODO remove this
val btb = None
val icache = Some(ICacheParams())
val beuAddr = None
val blockerCtrlAddr = None
val name = None
val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, tileId)
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
val baseName = "boom_l1_tracegen"
val uniqueName = s"${baseName}_$tileId"
}
class BoomTraceGenTile private(
val params: BoomTraceGenParams,
crossing: ClockCrossingType,
lookup: LookupByHartIdImpl,
q: Parameters) extends BaseTile(params, crossing, lookup, q)
with SinksExternalInterrupts
with SourcesExternalNotifications
{
def this(params: BoomTraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
val intOutwardNode: Option[IntOutwardNode] = None
val slaveNode: TLInwardNode = TLIdentityNode()
val statusNode = BundleBridgeSource(() => new GroundTestStatus)
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(tileId)(boom_params))
val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
override lazy val module = new BoomTraceGenTileModuleImp(this)
}
class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){
val status = outer.statusNode.bundle
val halt_and_catch_fire = None
val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := outer.hartIdSinkNode.bundle
val ptw = Module(new DummyPTW(1))
ptw.io := DontCare
val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge))
val boom_shim = Module(new BoomLSUShim()(outer.boom_params))
lsu.io.ptw := DontCare
ptw.io.requestors.head.req <> lsu.io.ptw.req
lsu.io.ptw.resp := ptw.io.requestors.head.resp
outer.dcache.module.io.lsu <> lsu.io.dmem
boom_shim.io.tracegen <> tracegen.io.mem
tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered
boom_shim.io.lsu <> lsu.io.core
// Normally the PTW would use this port
lsu.io.hellacache := DontCare
lsu.io.hellacache.req.valid := false.B
outer.reportCease(Some(tracegen.io.finished))
outer.reportHalt(Some(tracegen.io.timeout))
outer.reportWFI(None)
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U
status.error.valid := false.B
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out")
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
| module BoomLSUShim( // @[tracegen.scala:20:7]
input clock, // @[tracegen.scala:20:7]
input reset, // @[tracegen.scala:20:7]
output io_lsu_exe_0_req_valid, // @[tracegen.scala:22:14]
output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14]
output [5:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[tracegen.scala:22:14]
output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_is_amo, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[tracegen.scala:22:14]
output io_lsu_exe_0_req_bits_uop_uses_stq, // @[tracegen.scala:22:14]
output [63:0] io_lsu_exe_0_req_bits_data, // @[tracegen.scala:22:14]
output [33:0] io_lsu_exe_0_req_bits_addr, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_valid, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[tracegen.scala:22:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[tracegen.scala:22:14]
input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[tracegen.scala:22:14]
input [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[tracegen.scala:22:14]
input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_br, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_taken, // @[tracegen.scala:22:14]
input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[tracegen.scala:22:14]
input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_exception, // @[tracegen.scala:22:14]
input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[tracegen.scala:22:14]
input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14]
input [63:0] io_lsu_exe_0_iresp_bits_data, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_valid, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[tracegen.scala:22:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[tracegen.scala:22:14]
input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[tracegen.scala:22:14]
input [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[tracegen.scala:22:14]
input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14]
input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_br, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_taken, // @[tracegen.scala:22:14]
input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[tracegen.scala:22:14]
input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[tracegen.scala:22:14]
input [3:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[tracegen.scala:22:14]
input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_exception, // @[tracegen.scala:22:14]
input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[tracegen.scala:22:14]
input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[tracegen.scala:22:14]
input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[tracegen.scala:22:14]
input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[tracegen.scala:22:14]
input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[tracegen.scala:22:14]
input [64:0] io_lsu_exe_0_fresp_bits_data, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_valid, // @[tracegen.scala:22:14]
output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[tracegen.scala:22:14]
output [5:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:22:14]
output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:22:14]
output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:22:14]
input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:22:14]
input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:22:14]
input io_lsu_ldq_full_0, // @[tracegen.scala:22:14]
input io_lsu_stq_full_0, // @[tracegen.scala:22:14]
input io_lsu_fp_stdata_ready, // @[tracegen.scala:22:14]
output io_lsu_commit_valids_0, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_uopc, // @[tracegen.scala:22:14]
output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:22:14]
output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:22:14]
output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:22:14]
output [2:0] io_lsu_commit_uops_0_iq_type, // @[tracegen.scala:22:14]
output [9:0] io_lsu_commit_uops_0_fu_code, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[tracegen.scala:22:14]
output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[tracegen.scala:22:14]
output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[tracegen.scala:22:14]
output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[tracegen.scala:22:14]
output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ctrl_is_load, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ctrl_is_sta, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ctrl_is_std, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_iw_state, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_iw_p1_poisoned, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_iw_p2_poisoned, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_br, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_jalr, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_jal, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_taken, // @[tracegen.scala:22:14]
output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:22:14]
output [11:0] io_lsu_commit_uops_0_csr_addr, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:22:14]
output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:22:14]
output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_exception, // @[tracegen.scala:22:14]
output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_bypassable, // @[tracegen.scala:22:14]
output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:22:14]
output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_ldst_val, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_fp_single, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:22:14]
output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:22:14]
output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:22:14]
input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:22:14]
input [5:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:22:14]
input io_lsu_clr_bsy_1_valid, // @[tracegen.scala:22:14]
input [5:0] io_lsu_clr_bsy_1_bits, // @[tracegen.scala:22:14]
input [5:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:22:14]
input io_lsu_spec_ld_wakeup_0_valid, // @[tracegen.scala:22:14]
input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[tracegen.scala:22:14]
input io_lsu_ld_miss, // @[tracegen.scala:22:14]
output [5:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:22:14]
output [5:0] io_lsu_rob_head_idx, // @[tracegen.scala:22:14]
input io_lsu_fencei_rdy, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_valid, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[tracegen.scala:22:14]
input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:22:14]
input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:22:14]
input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:22:14]
input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[tracegen.scala:22:14]
input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[tracegen.scala:22:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[tracegen.scala:22:14]
input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[tracegen.scala:22:14]
input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_br, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_jalr, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_jal, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:22:14]
input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:22:14]
input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:22:14]
input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:22:14]
input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:22:14]
input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_bypassable, // @[tracegen.scala:22:14]
input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:22:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_ldst_val, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_fp_single, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:22:14]
input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:22:14]
input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:22:14]
input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:22:14]
input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:22:14]
input io_lsu_perf_acquire, // @[tracegen.scala:22:14]
input io_lsu_perf_release, // @[tracegen.scala:22:14]
output io_tracegen_req_ready, // @[tracegen.scala:22:14]
input io_tracegen_req_valid, // @[tracegen.scala:22:14]
input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:22:14]
input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:22:14]
input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:22:14]
input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:22:14]
input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:22:14]
output io_tracegen_resp_valid, // @[tracegen.scala:22:14]
output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:22:14]
output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:22:14]
output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:22:14]
output io_tracegen_ordered // @[tracegen.scala:22:14]
);
wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[tracegen.scala:20:7]
wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:20:7]
wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:20:7]
wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[tracegen.scala:20:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:20:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:20:7]
wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[tracegen.scala:20:7]
wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[tracegen.scala:20:7]
wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:20:7]
wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:20:7]
wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:20:7]
wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:20:7]
wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:20:7]
wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:20:7]
wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:20:7]
wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_dis_uops_0_bits_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_commit_uops_0_debug_inst_0 = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:20:7]
wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:57:45]
wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:57:45]
wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:57:30]
wire [31:0] tracegen_uop_debug_inst = 32'h0; // @[tracegen.scala:57:30]
wire io_lsu_exe_0_req_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_mxcpt_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_bits_asid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_predicated = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ctrl_fcn_dw_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_iw_p1_poisoned_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_iw_p2_poisoned_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_br_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_jalr_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_jal_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_bypassable_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ldst_val_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_fp_single_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_rbk_valids_0 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_rollback = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_br = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_jalr = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_jal = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_bypassable = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_ldst_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_fp_single = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_valid = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_exception = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:20:7]
wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:20:7]
wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:20:7]
wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_32 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_33 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_34 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_35 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_36 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_37 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_38 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_39 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_40 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_41 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_42 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_43 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_44 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_45 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_46 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_47 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_48 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_49 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_50 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_51 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_52 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_53 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_54 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_55 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_56 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_57 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_58 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_59 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_60 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_61 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_62 = 1'h0; // @[tracegen.scala:35:33]
wire _rob_bsy_WIRE_63 = 1'h0; // @[tracegen.scala:35:33]
wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ctrl_is_load = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ctrl_is_sta = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ctrl_is_std = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_br = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_jalr = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_jal = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_bypassable = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_ldst_val = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_fp_single = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:57:45]
wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:45]
wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_ctrl_fcn_dw = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_iw_p1_poisoned = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_iw_p2_poisoned = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_br = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_jalr = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_jal = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_bypassable = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_ldst_val = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_fp_single = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:57:30]
wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:57:30]
wire [33:0] io_lsu_exe_0_req_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_fp_stdata_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:20:7]
wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:57:45]
wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:57:30]
wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_dis_uops_0_bits_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_commit_uops_0_iq_type_0 = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0 = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0 = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0 = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:20:7]
wire [2:0] _tracegen_uop_WIRE_iq_type = 3'h0; // @[tracegen.scala:57:45]
wire [2:0] _tracegen_uop_WIRE_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:45]
wire [2:0] _tracegen_uop_WIRE_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:45]
wire [2:0] _tracegen_uop_WIRE_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:45]
wire [2:0] tracegen_uop_iq_type = 3'h0; // @[tracegen.scala:57:30]
wire [2:0] tracegen_uop_ctrl_op2_sel = 3'h0; // @[tracegen.scala:57:30]
wire [2:0] tracegen_uop_ctrl_imm_sel = 3'h0; // @[tracegen.scala:57:30]
wire [2:0] tracegen_uop_ctrl_csr_cmd = 3'h0; // @[tracegen.scala:57:30]
wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_dis_uops_0_bits_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_commit_uops_0_fu_code_0 = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code = 10'h0; // @[tracegen.scala:20:7]
wire [9:0] _tracegen_uop_WIRE_fu_code = 10'h0; // @[tracegen.scala:57:45]
wire [9:0] tracegen_uop_fu_code = 10'h0; // @[tracegen.scala:57:30]
wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0 = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:20:7]
wire [3:0] _tracegen_uop_WIRE_ctrl_br_type = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:57:45]
wire [3:0] tracegen_uop_ctrl_br_type = 4'h0; // @[tracegen.scala:57:30]
wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:57:30]
wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:57:30]
wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:57:30]
wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:153:39]
wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:153:39]
wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_iw_state_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0 = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_brupdate_b2_target_offset = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:20:7]
wire [1:0] _tracegen_uop_WIRE_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_iw_state = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_debug_fsrc = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] _tracegen_uop_WIRE_debug_tsrc = 2'h0; // @[tracegen.scala:57:45]
wire [1:0] tracegen_uop_ctrl_op1_sel = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_iw_state = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_debug_fsrc = 2'h0; // @[tracegen.scala:57:30]
wire [1:0] tracegen_uop_debug_tsrc = 2'h0; // @[tracegen.scala:57:30]
wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0 = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:20:7]
wire [4:0] _tracegen_uop_WIRE_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:45]
wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:57:45]
wire [4:0] tracegen_uop_ctrl_op_fcn = 5'h0; // @[tracegen.scala:57:30]
wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_rob_idx = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:20:7]
wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] _tracegen_uop_WIRE_rob_idx = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:57:45]
wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:57:30]
wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:57:30]
wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:57:30]
wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:57:30]
wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:57:30]
wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:20:7]
wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:57:45]
wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:57:30]
wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_dis_uops_0_bits_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_commit_uops_0_csr_addr_0 = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr = 12'h0; // @[tracegen.scala:20:7]
wire [11:0] _tracegen_uop_WIRE_csr_addr = 12'h0; // @[tracegen.scala:57:45]
wire [11:0] tracegen_uop_csr_addr = 12'h0; // @[tracegen.scala:57:30]
wire [6:0] io_lsu_exe_0_req_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_pdst_0 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_prs1_0 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_prs2_0 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_prs3_0 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_stale_pdst_0 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_uopc = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs1 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs2 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs3 = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst = 7'h0; // @[tracegen.scala:20:7]
wire [6:0] _tracegen_uop_WIRE_uopc = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] _tracegen_uop_WIRE_pdst = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] _tracegen_uop_WIRE_prs1 = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] _tracegen_uop_WIRE_prs2 = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] _tracegen_uop_WIRE_prs3 = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] _tracegen_uop_WIRE_stale_pdst = 7'h0; // @[tracegen.scala:57:45]
wire [6:0] tracegen_uop_pdst = 7'h0; // @[tracegen.scala:57:30]
wire [6:0] tracegen_uop_prs1 = 7'h0; // @[tracegen.scala:57:30]
wire [6:0] tracegen_uop_prs2 = 7'h0; // @[tracegen.scala:57:30]
wire [6:0] tracegen_uop_prs3 = 7'h0; // @[tracegen.scala:57:30]
wire [6:0] tracegen_uop_stale_pdst = 7'h0; // @[tracegen.scala:57:30]
wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_fp_stdata_bits_data = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:20:7]
wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:57:45]
wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:57:30]
wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size = 2'h3; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:20:7]
wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:20:7]
wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:20:7]
wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:20:7]
wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:57:30]
wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:20:7]
wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:20:7]
wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits = 25'h0; // @[tracegen.scala:20:7]
wire [32:0] io_lsu_exe_0_req_bits_sfence_bits_addr = 33'h0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_iresp_ready = 1'h1; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_fresp_ready = 1'h1; // @[tracegen.scala:20:7]
wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:20:7]
wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_33 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_34 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_35 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_36 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_37 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_38 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_39 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_40 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_41 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_42 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_43 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_44 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_45 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_46 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_47 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_48 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_49 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_50 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_51 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_52 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_53 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_54 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_55 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_56 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_57 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_58 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_59 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_60 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_61 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_62 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_63 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_T_64 = 1'h1; // @[tracegen.scala:33:54]
wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_32 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_33 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_34 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_35 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_36 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_37 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_38 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_39 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_40 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_41 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_42 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_43 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_44 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_45 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_46 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_47 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_48 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_49 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_50 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_51 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_52 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_53 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_54 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_55 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_56 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_57 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_58 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_59 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_60 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_61 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_62 = 1'h1; // @[tracegen.scala:33:34]
wire _rob_respd_WIRE_63 = 1'h1; // @[tracegen.scala:33:34]
wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:20:7]
wire [63:0] _rob_respd_T = 64'hFFFFFFFFFFFFFFFF; // @[tracegen.scala:33:36]
wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size_0; // @[tracegen.scala:20:7]
wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_exe_0_iresp_bits_data_0; // @[tracegen.scala:20:7]
wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35]
wire [6:0] tracegen_uop_uopc; // @[tracegen.scala:57:30]
wire tracegen_uop_ctrl_is_load; // @[tracegen.scala:57:30]
wire tracegen_uop_ctrl_is_sta; // @[tracegen.scala:57:30]
wire tracegen_uop_ctrl_is_std; // @[tracegen.scala:57:30]
wire [5:0] tracegen_uop_rob_idx; // @[tracegen.scala:57:30]
wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:57:30]
wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:57:30]
wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:57:30]
wire tracegen_uop_is_amo; // @[tracegen.scala:57:30]
wire tracegen_uop_uses_ldq; // @[tracegen.scala:57:30]
wire tracegen_uop_uses_stq; // @[tracegen.scala:57:30]
assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:20:7, :57:30]
assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:20:7, :57:30]
wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:95:75]
wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:53:63]
assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:20:7, :57:30]
wire _io_tracegen_ordered_T; // @[tracegen.scala:164:40]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[tracegen.scala:20:7]
wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[tracegen.scala:20:7]
wire [33:0] io_lsu_exe_0_req_bits_addr_0; // @[tracegen.scala:20:7]
wire io_lsu_exe_0_req_valid_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:20:7]
wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_valids_0_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[tracegen.scala:20:7]
wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:20:7]
wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:20:7]
wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:20:7]
wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:20:7]
wire [5:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:20:7]
wire io_tracegen_req_ready_0; // @[tracegen.scala:20:7]
wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:20:7]
wire io_tracegen_resp_valid_0; // @[tracegen.scala:20:7]
wire io_tracegen_ordered_0; // @[tracegen.scala:20:7]
reg [33:0] rob_0_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_0_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_0_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_0_data; // @[tracegen.scala:32:16]
reg [33:0] rob_1_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_1_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_1_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_1_data; // @[tracegen.scala:32:16]
reg [33:0] rob_2_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_2_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_2_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_2_data; // @[tracegen.scala:32:16]
reg [33:0] rob_3_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_3_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_3_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_3_data; // @[tracegen.scala:32:16]
reg [33:0] rob_4_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_4_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_4_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_4_data; // @[tracegen.scala:32:16]
reg [33:0] rob_5_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_5_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_5_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_5_data; // @[tracegen.scala:32:16]
reg [33:0] rob_6_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_6_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_6_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_6_data; // @[tracegen.scala:32:16]
reg [33:0] rob_7_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_7_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_7_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_7_data; // @[tracegen.scala:32:16]
reg [33:0] rob_8_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_8_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_8_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_8_data; // @[tracegen.scala:32:16]
reg [33:0] rob_9_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_9_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_9_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_9_data; // @[tracegen.scala:32:16]
reg [33:0] rob_10_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_10_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_10_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_10_data; // @[tracegen.scala:32:16]
reg [33:0] rob_11_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_11_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_11_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_11_data; // @[tracegen.scala:32:16]
reg [33:0] rob_12_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_12_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_12_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_12_data; // @[tracegen.scala:32:16]
reg [33:0] rob_13_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_13_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_13_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_13_data; // @[tracegen.scala:32:16]
reg [33:0] rob_14_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_14_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_14_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_14_data; // @[tracegen.scala:32:16]
reg [33:0] rob_15_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_15_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_15_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_15_data; // @[tracegen.scala:32:16]
reg [33:0] rob_16_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_16_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_16_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_16_data; // @[tracegen.scala:32:16]
reg [33:0] rob_17_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_17_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_17_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_17_data; // @[tracegen.scala:32:16]
reg [33:0] rob_18_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_18_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_18_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_18_data; // @[tracegen.scala:32:16]
reg [33:0] rob_19_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_19_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_19_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_19_data; // @[tracegen.scala:32:16]
reg [33:0] rob_20_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_20_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_20_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_20_data; // @[tracegen.scala:32:16]
reg [33:0] rob_21_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_21_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_21_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_21_data; // @[tracegen.scala:32:16]
reg [33:0] rob_22_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_22_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_22_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_22_data; // @[tracegen.scala:32:16]
reg [33:0] rob_23_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_23_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_23_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_23_data; // @[tracegen.scala:32:16]
reg [33:0] rob_24_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_24_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_24_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_24_data; // @[tracegen.scala:32:16]
reg [33:0] rob_25_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_25_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_25_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_25_data; // @[tracegen.scala:32:16]
reg [33:0] rob_26_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_26_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_26_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_26_data; // @[tracegen.scala:32:16]
reg [33:0] rob_27_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_27_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_27_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_27_data; // @[tracegen.scala:32:16]
reg [33:0] rob_28_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_28_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_28_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_28_data; // @[tracegen.scala:32:16]
reg [33:0] rob_29_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_29_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_29_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_29_data; // @[tracegen.scala:32:16]
reg [33:0] rob_30_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_30_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_30_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_30_data; // @[tracegen.scala:32:16]
reg [33:0] rob_31_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_31_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_31_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_31_data; // @[tracegen.scala:32:16]
reg [33:0] rob_32_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_32_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_32_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_32_data; // @[tracegen.scala:32:16]
reg [33:0] rob_33_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_33_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_33_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_33_data; // @[tracegen.scala:32:16]
reg [33:0] rob_34_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_34_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_34_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_34_data; // @[tracegen.scala:32:16]
reg [33:0] rob_35_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_35_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_35_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_35_data; // @[tracegen.scala:32:16]
reg [33:0] rob_36_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_36_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_36_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_36_data; // @[tracegen.scala:32:16]
reg [33:0] rob_37_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_37_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_37_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_37_data; // @[tracegen.scala:32:16]
reg [33:0] rob_38_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_38_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_38_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_38_data; // @[tracegen.scala:32:16]
reg [33:0] rob_39_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_39_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_39_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_39_data; // @[tracegen.scala:32:16]
reg [33:0] rob_40_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_40_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_40_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_40_data; // @[tracegen.scala:32:16]
reg [33:0] rob_41_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_41_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_41_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_41_data; // @[tracegen.scala:32:16]
reg [33:0] rob_42_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_42_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_42_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_42_data; // @[tracegen.scala:32:16]
reg [33:0] rob_43_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_43_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_43_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_43_data; // @[tracegen.scala:32:16]
reg [33:0] rob_44_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_44_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_44_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_44_data; // @[tracegen.scala:32:16]
reg [33:0] rob_45_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_45_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_45_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_45_data; // @[tracegen.scala:32:16]
reg [33:0] rob_46_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_46_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_46_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_46_data; // @[tracegen.scala:32:16]
reg [33:0] rob_47_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_47_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_47_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_47_data; // @[tracegen.scala:32:16]
reg [33:0] rob_48_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_48_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_48_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_48_data; // @[tracegen.scala:32:16]
reg [33:0] rob_49_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_49_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_49_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_49_data; // @[tracegen.scala:32:16]
reg [33:0] rob_50_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_50_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_50_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_50_data; // @[tracegen.scala:32:16]
reg [33:0] rob_51_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_51_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_51_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_51_data; // @[tracegen.scala:32:16]
reg [33:0] rob_52_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_52_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_52_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_52_data; // @[tracegen.scala:32:16]
reg [33:0] rob_53_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_53_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_53_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_53_data; // @[tracegen.scala:32:16]
reg [33:0] rob_54_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_54_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_54_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_54_data; // @[tracegen.scala:32:16]
reg [33:0] rob_55_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_55_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_55_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_55_data; // @[tracegen.scala:32:16]
reg [33:0] rob_56_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_56_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_56_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_56_data; // @[tracegen.scala:32:16]
reg [33:0] rob_57_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_57_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_57_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_57_data; // @[tracegen.scala:32:16]
reg [33:0] rob_58_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_58_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_58_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_58_data; // @[tracegen.scala:32:16]
reg [33:0] rob_59_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_59_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_59_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_59_data; // @[tracegen.scala:32:16]
reg [33:0] rob_60_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_60_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_60_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_60_data; // @[tracegen.scala:32:16]
reg [33:0] rob_61_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_61_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_61_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_61_data; // @[tracegen.scala:32:16]
reg [33:0] rob_62_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_62_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_62_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_62_data; // @[tracegen.scala:32:16]
reg [33:0] rob_63_addr; // @[tracegen.scala:32:16]
reg [5:0] rob_63_tag; // @[tracegen.scala:32:16]
reg [4:0] rob_63_cmd; // @[tracegen.scala:32:16]
reg [63:0] rob_63_data; // @[tracegen.scala:32:16]
reg rob_respd_0; // @[tracegen.scala:33:26]
reg rob_respd_1; // @[tracegen.scala:33:26]
reg rob_respd_2; // @[tracegen.scala:33:26]
reg rob_respd_3; // @[tracegen.scala:33:26]
reg rob_respd_4; // @[tracegen.scala:33:26]
reg rob_respd_5; // @[tracegen.scala:33:26]
reg rob_respd_6; // @[tracegen.scala:33:26]
reg rob_respd_7; // @[tracegen.scala:33:26]
reg rob_respd_8; // @[tracegen.scala:33:26]
reg rob_respd_9; // @[tracegen.scala:33:26]
reg rob_respd_10; // @[tracegen.scala:33:26]
reg rob_respd_11; // @[tracegen.scala:33:26]
reg rob_respd_12; // @[tracegen.scala:33:26]
reg rob_respd_13; // @[tracegen.scala:33:26]
reg rob_respd_14; // @[tracegen.scala:33:26]
reg rob_respd_15; // @[tracegen.scala:33:26]
reg rob_respd_16; // @[tracegen.scala:33:26]
reg rob_respd_17; // @[tracegen.scala:33:26]
reg rob_respd_18; // @[tracegen.scala:33:26]
reg rob_respd_19; // @[tracegen.scala:33:26]
reg rob_respd_20; // @[tracegen.scala:33:26]
reg rob_respd_21; // @[tracegen.scala:33:26]
reg rob_respd_22; // @[tracegen.scala:33:26]
reg rob_respd_23; // @[tracegen.scala:33:26]
reg rob_respd_24; // @[tracegen.scala:33:26]
reg rob_respd_25; // @[tracegen.scala:33:26]
reg rob_respd_26; // @[tracegen.scala:33:26]
reg rob_respd_27; // @[tracegen.scala:33:26]
reg rob_respd_28; // @[tracegen.scala:33:26]
reg rob_respd_29; // @[tracegen.scala:33:26]
reg rob_respd_30; // @[tracegen.scala:33:26]
reg rob_respd_31; // @[tracegen.scala:33:26]
reg rob_respd_32; // @[tracegen.scala:33:26]
reg rob_respd_33; // @[tracegen.scala:33:26]
reg rob_respd_34; // @[tracegen.scala:33:26]
reg rob_respd_35; // @[tracegen.scala:33:26]
reg rob_respd_36; // @[tracegen.scala:33:26]
reg rob_respd_37; // @[tracegen.scala:33:26]
reg rob_respd_38; // @[tracegen.scala:33:26]
reg rob_respd_39; // @[tracegen.scala:33:26]
reg rob_respd_40; // @[tracegen.scala:33:26]
reg rob_respd_41; // @[tracegen.scala:33:26]
reg rob_respd_42; // @[tracegen.scala:33:26]
reg rob_respd_43; // @[tracegen.scala:33:26]
reg rob_respd_44; // @[tracegen.scala:33:26]
reg rob_respd_45; // @[tracegen.scala:33:26]
reg rob_respd_46; // @[tracegen.scala:33:26]
reg rob_respd_47; // @[tracegen.scala:33:26]
reg rob_respd_48; // @[tracegen.scala:33:26]
reg rob_respd_49; // @[tracegen.scala:33:26]
reg rob_respd_50; // @[tracegen.scala:33:26]
reg rob_respd_51; // @[tracegen.scala:33:26]
reg rob_respd_52; // @[tracegen.scala:33:26]
reg rob_respd_53; // @[tracegen.scala:33:26]
reg rob_respd_54; // @[tracegen.scala:33:26]
reg rob_respd_55; // @[tracegen.scala:33:26]
reg rob_respd_56; // @[tracegen.scala:33:26]
reg rob_respd_57; // @[tracegen.scala:33:26]
reg rob_respd_58; // @[tracegen.scala:33:26]
reg rob_respd_59; // @[tracegen.scala:33:26]
reg rob_respd_60; // @[tracegen.scala:33:26]
reg rob_respd_61; // @[tracegen.scala:33:26]
reg rob_respd_62; // @[tracegen.scala:33:26]
reg rob_respd_63; // @[tracegen.scala:33:26]
reg [6:0] rob_uop_0_uopc; // @[tracegen.scala:34:20]
reg rob_uop_0_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_0_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_0_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_0_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_0_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_0_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_0_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_1_uopc; // @[tracegen.scala:34:20]
reg rob_uop_1_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_1_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_1_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_1_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_1_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_1_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_1_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_2_uopc; // @[tracegen.scala:34:20]
reg rob_uop_2_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_2_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_2_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_2_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_2_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_2_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_2_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_3_uopc; // @[tracegen.scala:34:20]
reg rob_uop_3_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_3_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_3_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_3_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_3_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_3_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_3_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_4_uopc; // @[tracegen.scala:34:20]
reg rob_uop_4_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_4_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_4_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_4_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_4_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_4_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_4_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_5_uopc; // @[tracegen.scala:34:20]
reg rob_uop_5_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_5_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_5_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_5_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_5_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_5_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_5_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_6_uopc; // @[tracegen.scala:34:20]
reg rob_uop_6_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_6_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_6_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_6_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_6_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_6_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_6_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_7_uopc; // @[tracegen.scala:34:20]
reg rob_uop_7_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_7_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_7_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_7_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_7_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_7_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_7_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_8_uopc; // @[tracegen.scala:34:20]
reg rob_uop_8_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_8_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_8_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_8_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_8_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_8_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_8_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_9_uopc; // @[tracegen.scala:34:20]
reg rob_uop_9_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_9_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_9_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_9_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_9_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_9_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_9_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_10_uopc; // @[tracegen.scala:34:20]
reg rob_uop_10_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_10_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_10_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_10_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_10_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_10_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_10_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_11_uopc; // @[tracegen.scala:34:20]
reg rob_uop_11_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_11_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_11_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_11_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_11_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_11_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_11_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_12_uopc; // @[tracegen.scala:34:20]
reg rob_uop_12_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_12_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_12_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_12_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_12_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_12_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_12_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_13_uopc; // @[tracegen.scala:34:20]
reg rob_uop_13_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_13_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_13_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_13_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_13_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_13_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_13_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_14_uopc; // @[tracegen.scala:34:20]
reg rob_uop_14_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_14_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_14_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_14_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_14_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_14_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_14_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_15_uopc; // @[tracegen.scala:34:20]
reg rob_uop_15_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_15_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_15_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_15_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_15_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_15_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_15_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_16_uopc; // @[tracegen.scala:34:20]
reg rob_uop_16_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_16_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_16_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_16_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_16_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_16_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_16_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_17_uopc; // @[tracegen.scala:34:20]
reg rob_uop_17_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_17_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_17_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_17_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_17_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_17_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_17_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_18_uopc; // @[tracegen.scala:34:20]
reg rob_uop_18_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_18_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_18_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_18_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_18_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_18_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_18_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_19_uopc; // @[tracegen.scala:34:20]
reg rob_uop_19_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_19_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_19_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_19_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_19_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_19_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_19_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_20_uopc; // @[tracegen.scala:34:20]
reg rob_uop_20_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_20_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_20_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_20_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_20_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_20_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_20_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_21_uopc; // @[tracegen.scala:34:20]
reg rob_uop_21_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_21_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_21_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_21_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_21_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_21_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_21_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_22_uopc; // @[tracegen.scala:34:20]
reg rob_uop_22_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_22_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_22_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_22_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_22_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_22_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_22_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_23_uopc; // @[tracegen.scala:34:20]
reg rob_uop_23_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_23_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_23_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_23_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_23_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_23_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_23_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_24_uopc; // @[tracegen.scala:34:20]
reg rob_uop_24_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_24_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_24_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_24_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_24_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_24_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_24_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_25_uopc; // @[tracegen.scala:34:20]
reg rob_uop_25_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_25_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_25_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_25_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_25_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_25_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_25_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_26_uopc; // @[tracegen.scala:34:20]
reg rob_uop_26_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_26_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_26_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_26_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_26_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_26_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_26_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_27_uopc; // @[tracegen.scala:34:20]
reg rob_uop_27_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_27_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_27_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_27_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_27_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_27_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_27_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_28_uopc; // @[tracegen.scala:34:20]
reg rob_uop_28_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_28_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_28_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_28_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_28_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_28_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_28_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_29_uopc; // @[tracegen.scala:34:20]
reg rob_uop_29_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_29_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_29_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_29_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_29_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_29_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_29_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_30_uopc; // @[tracegen.scala:34:20]
reg rob_uop_30_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_30_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_30_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_30_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_30_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_30_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_30_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_31_uopc; // @[tracegen.scala:34:20]
reg rob_uop_31_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_31_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_31_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_31_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_31_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_31_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_31_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_32_uopc; // @[tracegen.scala:34:20]
reg rob_uop_32_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_32_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_32_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_32_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_32_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_32_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_32_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_32_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_32_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_32_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_33_uopc; // @[tracegen.scala:34:20]
reg rob_uop_33_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_33_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_33_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_33_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_33_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_33_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_33_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_33_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_33_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_33_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_34_uopc; // @[tracegen.scala:34:20]
reg rob_uop_34_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_34_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_34_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_34_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_34_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_34_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_34_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_34_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_34_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_34_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_35_uopc; // @[tracegen.scala:34:20]
reg rob_uop_35_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_35_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_35_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_35_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_35_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_35_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_35_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_35_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_35_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_35_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_36_uopc; // @[tracegen.scala:34:20]
reg rob_uop_36_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_36_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_36_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_36_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_36_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_36_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_36_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_36_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_36_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_36_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_37_uopc; // @[tracegen.scala:34:20]
reg rob_uop_37_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_37_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_37_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_37_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_37_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_37_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_37_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_37_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_37_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_37_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_38_uopc; // @[tracegen.scala:34:20]
reg rob_uop_38_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_38_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_38_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_38_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_38_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_38_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_38_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_38_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_38_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_38_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_39_uopc; // @[tracegen.scala:34:20]
reg rob_uop_39_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_39_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_39_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_39_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_39_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_39_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_39_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_39_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_39_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_39_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_40_uopc; // @[tracegen.scala:34:20]
reg rob_uop_40_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_40_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_40_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_40_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_40_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_40_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_40_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_40_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_40_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_40_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_41_uopc; // @[tracegen.scala:34:20]
reg rob_uop_41_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_41_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_41_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_41_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_41_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_41_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_41_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_41_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_41_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_41_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_42_uopc; // @[tracegen.scala:34:20]
reg rob_uop_42_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_42_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_42_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_42_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_42_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_42_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_42_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_42_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_42_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_42_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_43_uopc; // @[tracegen.scala:34:20]
reg rob_uop_43_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_43_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_43_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_43_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_43_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_43_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_43_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_43_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_43_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_43_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_44_uopc; // @[tracegen.scala:34:20]
reg rob_uop_44_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_44_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_44_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_44_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_44_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_44_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_44_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_44_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_44_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_44_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_45_uopc; // @[tracegen.scala:34:20]
reg rob_uop_45_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_45_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_45_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_45_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_45_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_45_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_45_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_45_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_45_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_45_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_46_uopc; // @[tracegen.scala:34:20]
reg rob_uop_46_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_46_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_46_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_46_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_46_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_46_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_46_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_46_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_46_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_46_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_47_uopc; // @[tracegen.scala:34:20]
reg rob_uop_47_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_47_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_47_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_47_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_47_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_47_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_47_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_47_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_47_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_47_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_48_uopc; // @[tracegen.scala:34:20]
reg rob_uop_48_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_48_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_48_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_48_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_48_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_48_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_48_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_48_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_48_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_48_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_49_uopc; // @[tracegen.scala:34:20]
reg rob_uop_49_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_49_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_49_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_49_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_49_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_49_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_49_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_49_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_49_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_49_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_50_uopc; // @[tracegen.scala:34:20]
reg rob_uop_50_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_50_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_50_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_50_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_50_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_50_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_50_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_50_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_50_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_50_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_51_uopc; // @[tracegen.scala:34:20]
reg rob_uop_51_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_51_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_51_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_51_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_51_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_51_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_51_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_51_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_51_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_51_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_52_uopc; // @[tracegen.scala:34:20]
reg rob_uop_52_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_52_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_52_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_52_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_52_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_52_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_52_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_52_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_52_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_52_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_53_uopc; // @[tracegen.scala:34:20]
reg rob_uop_53_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_53_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_53_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_53_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_53_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_53_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_53_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_53_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_53_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_53_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_54_uopc; // @[tracegen.scala:34:20]
reg rob_uop_54_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_54_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_54_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_54_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_54_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_54_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_54_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_54_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_54_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_54_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_55_uopc; // @[tracegen.scala:34:20]
reg rob_uop_55_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_55_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_55_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_55_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_55_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_55_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_55_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_55_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_55_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_55_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_56_uopc; // @[tracegen.scala:34:20]
reg rob_uop_56_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_56_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_56_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_56_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_56_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_56_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_56_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_56_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_56_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_56_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_57_uopc; // @[tracegen.scala:34:20]
reg rob_uop_57_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_57_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_57_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_57_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_57_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_57_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_57_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_57_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_57_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_57_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_58_uopc; // @[tracegen.scala:34:20]
reg rob_uop_58_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_58_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_58_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_58_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_58_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_58_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_58_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_58_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_58_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_58_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_59_uopc; // @[tracegen.scala:34:20]
reg rob_uop_59_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_59_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_59_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_59_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_59_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_59_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_59_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_59_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_59_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_59_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_60_uopc; // @[tracegen.scala:34:20]
reg rob_uop_60_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_60_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_60_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_60_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_60_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_60_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_60_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_60_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_60_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_60_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_61_uopc; // @[tracegen.scala:34:20]
reg rob_uop_61_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_61_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_61_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_61_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_61_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_61_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_61_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_61_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_61_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_61_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_62_uopc; // @[tracegen.scala:34:20]
reg rob_uop_62_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_62_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_62_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_62_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_62_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_62_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_62_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_62_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_62_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_62_uses_stq; // @[tracegen.scala:34:20]
reg [6:0] rob_uop_63_uopc; // @[tracegen.scala:34:20]
reg rob_uop_63_ctrl_is_load; // @[tracegen.scala:34:20]
reg rob_uop_63_ctrl_is_sta; // @[tracegen.scala:34:20]
reg rob_uop_63_ctrl_is_std; // @[tracegen.scala:34:20]
reg [5:0] rob_uop_63_rob_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_63_ldq_idx; // @[tracegen.scala:34:20]
reg [3:0] rob_uop_63_stq_idx; // @[tracegen.scala:34:20]
reg [4:0] rob_uop_63_mem_cmd; // @[tracegen.scala:34:20]
reg rob_uop_63_is_amo; // @[tracegen.scala:34:20]
reg rob_uop_63_uses_ldq; // @[tracegen.scala:34:20]
reg rob_uop_63_uses_stq; // @[tracegen.scala:34:20]
reg rob_bsy_0; // @[tracegen.scala:35:25]
reg rob_bsy_1; // @[tracegen.scala:35:25]
reg rob_bsy_2; // @[tracegen.scala:35:25]
reg rob_bsy_3; // @[tracegen.scala:35:25]
reg rob_bsy_4; // @[tracegen.scala:35:25]
reg rob_bsy_5; // @[tracegen.scala:35:25]
reg rob_bsy_6; // @[tracegen.scala:35:25]
reg rob_bsy_7; // @[tracegen.scala:35:25]
reg rob_bsy_8; // @[tracegen.scala:35:25]
reg rob_bsy_9; // @[tracegen.scala:35:25]
reg rob_bsy_10; // @[tracegen.scala:35:25]
reg rob_bsy_11; // @[tracegen.scala:35:25]
reg rob_bsy_12; // @[tracegen.scala:35:25]
reg rob_bsy_13; // @[tracegen.scala:35:25]
reg rob_bsy_14; // @[tracegen.scala:35:25]
reg rob_bsy_15; // @[tracegen.scala:35:25]
reg rob_bsy_16; // @[tracegen.scala:35:25]
reg rob_bsy_17; // @[tracegen.scala:35:25]
reg rob_bsy_18; // @[tracegen.scala:35:25]
reg rob_bsy_19; // @[tracegen.scala:35:25]
reg rob_bsy_20; // @[tracegen.scala:35:25]
reg rob_bsy_21; // @[tracegen.scala:35:25]
reg rob_bsy_22; // @[tracegen.scala:35:25]
reg rob_bsy_23; // @[tracegen.scala:35:25]
reg rob_bsy_24; // @[tracegen.scala:35:25]
reg rob_bsy_25; // @[tracegen.scala:35:25]
reg rob_bsy_26; // @[tracegen.scala:35:25]
reg rob_bsy_27; // @[tracegen.scala:35:25]
reg rob_bsy_28; // @[tracegen.scala:35:25]
reg rob_bsy_29; // @[tracegen.scala:35:25]
reg rob_bsy_30; // @[tracegen.scala:35:25]
reg rob_bsy_31; // @[tracegen.scala:35:25]
reg rob_bsy_32; // @[tracegen.scala:35:25]
reg rob_bsy_33; // @[tracegen.scala:35:25]
reg rob_bsy_34; // @[tracegen.scala:35:25]
reg rob_bsy_35; // @[tracegen.scala:35:25]
reg rob_bsy_36; // @[tracegen.scala:35:25]
reg rob_bsy_37; // @[tracegen.scala:35:25]
reg rob_bsy_38; // @[tracegen.scala:35:25]
reg rob_bsy_39; // @[tracegen.scala:35:25]
reg rob_bsy_40; // @[tracegen.scala:35:25]
reg rob_bsy_41; // @[tracegen.scala:35:25]
reg rob_bsy_42; // @[tracegen.scala:35:25]
reg rob_bsy_43; // @[tracegen.scala:35:25]
reg rob_bsy_44; // @[tracegen.scala:35:25]
reg rob_bsy_45; // @[tracegen.scala:35:25]
reg rob_bsy_46; // @[tracegen.scala:35:25]
reg rob_bsy_47; // @[tracegen.scala:35:25]
reg rob_bsy_48; // @[tracegen.scala:35:25]
reg rob_bsy_49; // @[tracegen.scala:35:25]
reg rob_bsy_50; // @[tracegen.scala:35:25]
reg rob_bsy_51; // @[tracegen.scala:35:25]
reg rob_bsy_52; // @[tracegen.scala:35:25]
reg rob_bsy_53; // @[tracegen.scala:35:25]
reg rob_bsy_54; // @[tracegen.scala:35:25]
reg rob_bsy_55; // @[tracegen.scala:35:25]
reg rob_bsy_56; // @[tracegen.scala:35:25]
reg rob_bsy_57; // @[tracegen.scala:35:25]
reg rob_bsy_58; // @[tracegen.scala:35:25]
reg rob_bsy_59; // @[tracegen.scala:35:25]
reg rob_bsy_60; // @[tracegen.scala:35:25]
reg rob_bsy_61; // @[tracegen.scala:35:25]
reg rob_bsy_62; // @[tracegen.scala:35:25]
reg rob_bsy_63; // @[tracegen.scala:35:25]
reg [5:0] rob_head; // @[tracegen.scala:36:25]
assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:20:7, :36:25]
reg [5:0] rob_tail; // @[tracegen.scala:37:25]
assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:20:7, :37:25]
assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:37:25, :57:30]
reg rob_wait_till_empty; // @[tracegen.scala:38:36]
wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:36:25, :37:25, :39:32]
wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:20:7, :39:{32,45}]
wire [63:0] _GEN = {{rob_bsy_63}, {rob_bsy_62}, {rob_bsy_61}, {rob_bsy_60}, {rob_bsy_59}, {rob_bsy_58}, {rob_bsy_57}, {rob_bsy_56}, {rob_bsy_55}, {rob_bsy_54}, {rob_bsy_53}, {rob_bsy_52}, {rob_bsy_51}, {rob_bsy_50}, {rob_bsy_49}, {rob_bsy_48}, {rob_bsy_47}, {rob_bsy_46}, {rob_bsy_45}, {rob_bsy_44}, {rob_bsy_43}, {rob_bsy_42}, {rob_bsy_41}, {rob_bsy_40}, {rob_bsy_39}, {rob_bsy_38}, {rob_bsy_37}, {rob_bsy_36}, {rob_bsy_35}, {rob_bsy_34}, {rob_bsy_33}, {rob_bsy_32}, {rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:35:25, :49:29]
wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:37:25, :49:29]
wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:38:36, :50:5]
wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:49:{29,48}, :50:5]
wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_7; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_7 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_30; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_30 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_5; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_5 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_5; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_5 = _T_1; // @[package.scala:16:47]
wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_8 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_31 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_6 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_6 = _T_2; // @[package.scala:16:47]
wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_9 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_32 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_7 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_7 = _T_3; // @[package.scala:16:47]
wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_10 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_33 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_8 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_8 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 | _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 | _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 | _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59]
wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_14; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_14 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_37; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_37 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_12; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_12 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_12; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_12 = _T_8; // @[package.scala:16:47]
wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_15 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_38 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_13 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_13 = _T_9; // @[package.scala:16:47]
wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_16 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_39 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_14 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_14 = _T_10; // @[package.scala:16:47]
wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_17 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_40 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_15 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_15 = _T_11; // @[package.scala:16:47]
wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_18 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_41 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_sta_T_16 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_std_T_16 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 | _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 | _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 | _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 | _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 | _io_tracegen_req_ready_T_18; // @[package.scala:81:59]
wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:20:7, :51:85]
wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:51:85]
assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:51:85]
wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_2 = _T_18; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 | _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44]
wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:20:7, :51:123]
wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:123]
assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:51:123]
wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66]
assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:67:92]
assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:51:123, :67:92]
wire _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_3 = _T_20; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:66]
assign _tracegen_uop_ctrl_is_load_T_28 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:66]
assign _tracegen_uop_ctrl_is_sta_T_3 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:66]
assign _tracegen_uop_ctrl_is_std_T_3 = _T_20; // @[Consts.scala:90:66]
wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 | _io_tracegen_req_ready_T_22; // @[tracegen.scala:51:{57,95,123}]
wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:51:{23,95}]
wire _io_tracegen_req_ready_T_25 = ready_for_amo | _io_tracegen_req_ready_T_24; // @[tracegen.scala:39:45, :51:{20,23}]
wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:49:48, :50:26, :51:20]
wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:37:25, :45:13]
wire [6:0] _GEN_0 = {1'h0, rob_tail} + 7'h1; // @[tracegen.scala:37:25, :45:37]
wire [6:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:45:37]
assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:45:37]
wire [6:0] _rob_tail_T_1; // @[tracegen.scala:45:37]
assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:45:37]
wire [5:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[5:0]; // @[tracegen.scala:45:37]
wire [5:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 6'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:45:{8,13,37}]
wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:36:25, :45:8, :52:32]
wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:50:26, :51:135, :52:32]
wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T = _GEN_1; // @[package.scala:16:47]
wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47]
wire _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47]
assign _tracegen_uop_ctrl_is_load_T_1 = _GEN_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 | _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 | _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 | _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 | _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 | _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 | _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 | _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 | _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 | _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 | _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 | _io_tracegen_req_ready_T_55; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 | _io_tracegen_req_ready_T_56; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68]
wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:53:{5,26}]
wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:51:135, :52:46, :53:5]
wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32]
assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_ctrl_is_load_T_25; // @[Consts.scala:90:32]
assign _tracegen_uop_ctrl_is_load_T_25 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_ctrl_is_sta_T; // @[Consts.scala:90:32]
assign _tracegen_uop_ctrl_is_sta_T = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_ctrl_is_std_T; // @[Consts.scala:90:32]
assign _tracegen_uop_ctrl_is_std_T = _GEN_3; // @[Consts.scala:90:32]
wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49]
assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:49]
assign _tracegen_uop_ctrl_is_load_T_26 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:49]
assign _tracegen_uop_ctrl_is_sta_T_1 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:49]
assign _tracegen_uop_ctrl_is_std_T_1 = _GEN_4; // @[Consts.scala:90:49]
wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 | _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}]
wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 | _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}]
wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 | _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 | _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 | _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 | _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 | _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 | _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 | _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 | _io_tracegen_req_ready_T_81; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 | _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}]
wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76]
wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:54:{5,26}]
assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:52:46, :53:63, :54:5]
assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:20:7, :53:63]
assign io_lsu_dis_uops_0_bits_uopc_0 = tracegen_uop_uopc; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:68:65]
assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = tracegen_uop_ctrl_is_load; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76]
assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = tracegen_uop_ctrl_is_sta; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76]
assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = tracegen_uop_ctrl_is_std; // @[tracegen.scala:20:7, :57:30]
assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:20:7, :57:30]
assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:20:7, :57:30]
assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:20:7, :57:30]
assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:67:64]
assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:58:65]
assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76]
assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:20:7, :57:30]
wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T | _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 | _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 | _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 | _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 | _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 | _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 | _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 | _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 | _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 | _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 | _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 | _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 | _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 | _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 | _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 | _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 | _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 | _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 | _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 | _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 | _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 | _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 | _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76]
assign _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68]
assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_49; // @[tracegen.scala:57:30, :58:65]
wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T | _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 | _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 | _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 | _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 | _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 | _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 | _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 | _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 | _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 | _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59]
assign _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 | _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_22; // @[Consts.scala:90:76]
assign tracegen_uop_uopc = {1'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:20:7, :57:30, :61:29]
wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T | _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 | _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 | _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 | _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 | _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 | _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 | _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 | _tracegen_uop_is_amo_T_15; // @[package.scala:81:59]
assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 | _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44]
assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:57:30, :67:64]
wire _tracegen_uop_ctrl_is_load_T_4 = _tracegen_uop_ctrl_is_load_T | _tracegen_uop_ctrl_is_load_T_1; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_5 = _tracegen_uop_ctrl_is_load_T_4 | _tracegen_uop_ctrl_is_load_T_2; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_6 = _tracegen_uop_ctrl_is_load_T_5 | _tracegen_uop_ctrl_is_load_T_3; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_11 = _tracegen_uop_ctrl_is_load_T_7 | _tracegen_uop_ctrl_is_load_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_12 = _tracegen_uop_ctrl_is_load_T_11 | _tracegen_uop_ctrl_is_load_T_9; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_13 = _tracegen_uop_ctrl_is_load_T_12 | _tracegen_uop_ctrl_is_load_T_10; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_19 = _tracegen_uop_ctrl_is_load_T_14 | _tracegen_uop_ctrl_is_load_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_20 = _tracegen_uop_ctrl_is_load_T_19 | _tracegen_uop_ctrl_is_load_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_21 = _tracegen_uop_ctrl_is_load_T_20 | _tracegen_uop_ctrl_is_load_T_17; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_22 = _tracegen_uop_ctrl_is_load_T_21 | _tracegen_uop_ctrl_is_load_T_18; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_23 = _tracegen_uop_ctrl_is_load_T_13 | _tracegen_uop_ctrl_is_load_T_22; // @[package.scala:81:59]
wire _tracegen_uop_ctrl_is_load_T_24 = _tracegen_uop_ctrl_is_load_T_6 | _tracegen_uop_ctrl_is_load_T_23; // @[package.scala:81:59]
wire _tracegen_uop_ctrl_is_load_T_27 = _tracegen_uop_ctrl_is_load_T_25 | _tracegen_uop_ctrl_is_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_ctrl_is_load_T_29 = _tracegen_uop_ctrl_is_load_T_27 | _tracegen_uop_ctrl_is_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_ctrl_is_load_T_34 = _tracegen_uop_ctrl_is_load_T_30 | _tracegen_uop_ctrl_is_load_T_31; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_35 = _tracegen_uop_ctrl_is_load_T_34 | _tracegen_uop_ctrl_is_load_T_32; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_36 = _tracegen_uop_ctrl_is_load_T_35 | _tracegen_uop_ctrl_is_load_T_33; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_42 = _tracegen_uop_ctrl_is_load_T_37 | _tracegen_uop_ctrl_is_load_T_38; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_43 = _tracegen_uop_ctrl_is_load_T_42 | _tracegen_uop_ctrl_is_load_T_39; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_44 = _tracegen_uop_ctrl_is_load_T_43 | _tracegen_uop_ctrl_is_load_T_40; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_45 = _tracegen_uop_ctrl_is_load_T_44 | _tracegen_uop_ctrl_is_load_T_41; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_load_T_46 = _tracegen_uop_ctrl_is_load_T_36 | _tracegen_uop_ctrl_is_load_T_45; // @[package.scala:81:59]
wire _tracegen_uop_ctrl_is_load_T_47 = _tracegen_uop_ctrl_is_load_T_29 | _tracegen_uop_ctrl_is_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _tracegen_uop_ctrl_is_load_T_48 = ~_tracegen_uop_ctrl_is_load_T_47; // @[Consts.scala:90:76]
assign _tracegen_uop_ctrl_is_load_T_49 = _tracegen_uop_ctrl_is_load_T_24 & _tracegen_uop_ctrl_is_load_T_48; // @[Consts.scala:89:68]
assign tracegen_uop_ctrl_is_load = _tracegen_uop_ctrl_is_load_T_49; // @[tracegen.scala:57:30, :68:65]
wire _tracegen_uop_ctrl_is_sta_T_2 = _tracegen_uop_ctrl_is_sta_T | _tracegen_uop_ctrl_is_sta_T_1; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_ctrl_is_sta_T_4 = _tracegen_uop_ctrl_is_sta_T_2 | _tracegen_uop_ctrl_is_sta_T_3; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_ctrl_is_sta_T_9 = _tracegen_uop_ctrl_is_sta_T_5 | _tracegen_uop_ctrl_is_sta_T_6; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_10 = _tracegen_uop_ctrl_is_sta_T_9 | _tracegen_uop_ctrl_is_sta_T_7; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_11 = _tracegen_uop_ctrl_is_sta_T_10 | _tracegen_uop_ctrl_is_sta_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_17 = _tracegen_uop_ctrl_is_sta_T_12 | _tracegen_uop_ctrl_is_sta_T_13; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_18 = _tracegen_uop_ctrl_is_sta_T_17 | _tracegen_uop_ctrl_is_sta_T_14; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_19 = _tracegen_uop_ctrl_is_sta_T_18 | _tracegen_uop_ctrl_is_sta_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_20 = _tracegen_uop_ctrl_is_sta_T_19 | _tracegen_uop_ctrl_is_sta_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_sta_T_21 = _tracegen_uop_ctrl_is_sta_T_11 | _tracegen_uop_ctrl_is_sta_T_20; // @[package.scala:81:59]
assign _tracegen_uop_ctrl_is_sta_T_22 = _tracegen_uop_ctrl_is_sta_T_4 | _tracegen_uop_ctrl_is_sta_T_21; // @[Consts.scala:87:44, :90:{59,76}]
assign tracegen_uop_ctrl_is_sta = _tracegen_uop_ctrl_is_sta_T_22; // @[Consts.scala:90:76]
wire _tracegen_uop_ctrl_is_std_T_2 = _tracegen_uop_ctrl_is_std_T | _tracegen_uop_ctrl_is_std_T_1; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_ctrl_is_std_T_4 = _tracegen_uop_ctrl_is_std_T_2 | _tracegen_uop_ctrl_is_std_T_3; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_ctrl_is_std_T_9 = _tracegen_uop_ctrl_is_std_T_5 | _tracegen_uop_ctrl_is_std_T_6; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_10 = _tracegen_uop_ctrl_is_std_T_9 | _tracegen_uop_ctrl_is_std_T_7; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_11 = _tracegen_uop_ctrl_is_std_T_10 | _tracegen_uop_ctrl_is_std_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_17 = _tracegen_uop_ctrl_is_std_T_12 | _tracegen_uop_ctrl_is_std_T_13; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_18 = _tracegen_uop_ctrl_is_std_T_17 | _tracegen_uop_ctrl_is_std_T_14; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_19 = _tracegen_uop_ctrl_is_std_T_18 | _tracegen_uop_ctrl_is_std_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_20 = _tracegen_uop_ctrl_is_std_T_19 | _tracegen_uop_ctrl_is_std_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_ctrl_is_std_T_21 = _tracegen_uop_ctrl_is_std_T_11 | _tracegen_uop_ctrl_is_std_T_20; // @[package.scala:81:59]
assign _tracegen_uop_ctrl_is_std_T_22 = _tracegen_uop_ctrl_is_std_T_4 | _tracegen_uop_ctrl_is_std_T_21; // @[Consts.scala:87:44, :90:{59,76}]
assign tracegen_uop_ctrl_is_std = _tracegen_uop_ctrl_is_std_T_22; // @[Consts.scala:90:76]
wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35]
assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35]
wire _io_lsu_exe_0_req_valid_T; // @[Decoupled.scala:51:35]
assign _io_lsu_exe_0_req_valid_T = _T; // @[Decoupled.scala:51:35]
assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35]
wire _rob_tail_T = &rob_tail; // @[tracegen.scala:37:25, :45:13]
wire [5:0] _rob_tail_T_2 = _rob_tail_T_1[5:0]; // @[tracegen.scala:45:37]
wire [5:0] _rob_tail_T_3 = _rob_tail_T ? 6'h0 : _rob_tail_T_2; // @[tracegen.scala:45:{8,13,37}]
wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:36:25, :49:29, :95:31]
wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:36:25, :37:25, :95:62]
wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:95:{31,50,62}]
wire [63:0] _GEN_5 = {{rob_respd_63}, {rob_respd_62}, {rob_respd_61}, {rob_respd_60}, {rob_respd_59}, {rob_respd_58}, {rob_respd_57}, {rob_respd_56}, {rob_respd_55}, {rob_respd_54}, {rob_respd_53}, {rob_respd_52}, {rob_respd_51}, {rob_respd_50}, {rob_respd_49}, {rob_respd_48}, {rob_respd_47}, {rob_respd_46}, {rob_respd_45}, {rob_respd_44}, {rob_respd_43}, {rob_respd_42}, {rob_respd_41}, {rob_respd_40}, {rob_respd_39}, {rob_respd_38}, {rob_respd_37}, {rob_respd_36}, {rob_respd_35}, {rob_respd_34}, {rob_respd_33}, {rob_respd_32}, {rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:33:26, :95:75]
assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:36:25, :95:{50,75}]
assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:20:7, :95:75]
wire [63:0][6:0] _GEN_6 = {{rob_uop_63_uopc}, {rob_uop_62_uopc}, {rob_uop_61_uopc}, {rob_uop_60_uopc}, {rob_uop_59_uopc}, {rob_uop_58_uopc}, {rob_uop_57_uopc}, {rob_uop_56_uopc}, {rob_uop_55_uopc}, {rob_uop_54_uopc}, {rob_uop_53_uopc}, {rob_uop_52_uopc}, {rob_uop_51_uopc}, {rob_uop_50_uopc}, {rob_uop_49_uopc}, {rob_uop_48_uopc}, {rob_uop_47_uopc}, {rob_uop_46_uopc}, {rob_uop_45_uopc}, {rob_uop_44_uopc}, {rob_uop_43_uopc}, {rob_uop_42_uopc}, {rob_uop_41_uopc}, {rob_uop_40_uopc}, {rob_uop_39_uopc}, {rob_uop_38_uopc}, {rob_uop_37_uopc}, {rob_uop_36_uopc}, {rob_uop_35_uopc}, {rob_uop_34_uopc}, {rob_uop_33_uopc}, {rob_uop_32_uopc}, {rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_uopc_0 = _GEN_6[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_7 = {{rob_uop_63_ctrl_is_load}, {rob_uop_62_ctrl_is_load}, {rob_uop_61_ctrl_is_load}, {rob_uop_60_ctrl_is_load}, {rob_uop_59_ctrl_is_load}, {rob_uop_58_ctrl_is_load}, {rob_uop_57_ctrl_is_load}, {rob_uop_56_ctrl_is_load}, {rob_uop_55_ctrl_is_load}, {rob_uop_54_ctrl_is_load}, {rob_uop_53_ctrl_is_load}, {rob_uop_52_ctrl_is_load}, {rob_uop_51_ctrl_is_load}, {rob_uop_50_ctrl_is_load}, {rob_uop_49_ctrl_is_load}, {rob_uop_48_ctrl_is_load}, {rob_uop_47_ctrl_is_load}, {rob_uop_46_ctrl_is_load}, {rob_uop_45_ctrl_is_load}, {rob_uop_44_ctrl_is_load}, {rob_uop_43_ctrl_is_load}, {rob_uop_42_ctrl_is_load}, {rob_uop_41_ctrl_is_load}, {rob_uop_40_ctrl_is_load}, {rob_uop_39_ctrl_is_load}, {rob_uop_38_ctrl_is_load}, {rob_uop_37_ctrl_is_load}, {rob_uop_36_ctrl_is_load}, {rob_uop_35_ctrl_is_load}, {rob_uop_34_ctrl_is_load}, {rob_uop_33_ctrl_is_load}, {rob_uop_32_ctrl_is_load}, {rob_uop_31_ctrl_is_load}, {rob_uop_30_ctrl_is_load}, {rob_uop_29_ctrl_is_load}, {rob_uop_28_ctrl_is_load}, {rob_uop_27_ctrl_is_load}, {rob_uop_26_ctrl_is_load}, {rob_uop_25_ctrl_is_load}, {rob_uop_24_ctrl_is_load}, {rob_uop_23_ctrl_is_load}, {rob_uop_22_ctrl_is_load}, {rob_uop_21_ctrl_is_load}, {rob_uop_20_ctrl_is_load}, {rob_uop_19_ctrl_is_load}, {rob_uop_18_ctrl_is_load}, {rob_uop_17_ctrl_is_load}, {rob_uop_16_ctrl_is_load}, {rob_uop_15_ctrl_is_load}, {rob_uop_14_ctrl_is_load}, {rob_uop_13_ctrl_is_load}, {rob_uop_12_ctrl_is_load}, {rob_uop_11_ctrl_is_load}, {rob_uop_10_ctrl_is_load}, {rob_uop_9_ctrl_is_load}, {rob_uop_8_ctrl_is_load}, {rob_uop_7_ctrl_is_load}, {rob_uop_6_ctrl_is_load}, {rob_uop_5_ctrl_is_load}, {rob_uop_4_ctrl_is_load}, {rob_uop_3_ctrl_is_load}, {rob_uop_2_ctrl_is_load}, {rob_uop_1_ctrl_is_load}, {rob_uop_0_ctrl_is_load}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_ctrl_is_load_0 = _GEN_7[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_8 = {{rob_uop_63_ctrl_is_sta}, {rob_uop_62_ctrl_is_sta}, {rob_uop_61_ctrl_is_sta}, {rob_uop_60_ctrl_is_sta}, {rob_uop_59_ctrl_is_sta}, {rob_uop_58_ctrl_is_sta}, {rob_uop_57_ctrl_is_sta}, {rob_uop_56_ctrl_is_sta}, {rob_uop_55_ctrl_is_sta}, {rob_uop_54_ctrl_is_sta}, {rob_uop_53_ctrl_is_sta}, {rob_uop_52_ctrl_is_sta}, {rob_uop_51_ctrl_is_sta}, {rob_uop_50_ctrl_is_sta}, {rob_uop_49_ctrl_is_sta}, {rob_uop_48_ctrl_is_sta}, {rob_uop_47_ctrl_is_sta}, {rob_uop_46_ctrl_is_sta}, {rob_uop_45_ctrl_is_sta}, {rob_uop_44_ctrl_is_sta}, {rob_uop_43_ctrl_is_sta}, {rob_uop_42_ctrl_is_sta}, {rob_uop_41_ctrl_is_sta}, {rob_uop_40_ctrl_is_sta}, {rob_uop_39_ctrl_is_sta}, {rob_uop_38_ctrl_is_sta}, {rob_uop_37_ctrl_is_sta}, {rob_uop_36_ctrl_is_sta}, {rob_uop_35_ctrl_is_sta}, {rob_uop_34_ctrl_is_sta}, {rob_uop_33_ctrl_is_sta}, {rob_uop_32_ctrl_is_sta}, {rob_uop_31_ctrl_is_sta}, {rob_uop_30_ctrl_is_sta}, {rob_uop_29_ctrl_is_sta}, {rob_uop_28_ctrl_is_sta}, {rob_uop_27_ctrl_is_sta}, {rob_uop_26_ctrl_is_sta}, {rob_uop_25_ctrl_is_sta}, {rob_uop_24_ctrl_is_sta}, {rob_uop_23_ctrl_is_sta}, {rob_uop_22_ctrl_is_sta}, {rob_uop_21_ctrl_is_sta}, {rob_uop_20_ctrl_is_sta}, {rob_uop_19_ctrl_is_sta}, {rob_uop_18_ctrl_is_sta}, {rob_uop_17_ctrl_is_sta}, {rob_uop_16_ctrl_is_sta}, {rob_uop_15_ctrl_is_sta}, {rob_uop_14_ctrl_is_sta}, {rob_uop_13_ctrl_is_sta}, {rob_uop_12_ctrl_is_sta}, {rob_uop_11_ctrl_is_sta}, {rob_uop_10_ctrl_is_sta}, {rob_uop_9_ctrl_is_sta}, {rob_uop_8_ctrl_is_sta}, {rob_uop_7_ctrl_is_sta}, {rob_uop_6_ctrl_is_sta}, {rob_uop_5_ctrl_is_sta}, {rob_uop_4_ctrl_is_sta}, {rob_uop_3_ctrl_is_sta}, {rob_uop_2_ctrl_is_sta}, {rob_uop_1_ctrl_is_sta}, {rob_uop_0_ctrl_is_sta}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_ctrl_is_sta_0 = _GEN_8[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_9 = {{rob_uop_63_ctrl_is_std}, {rob_uop_62_ctrl_is_std}, {rob_uop_61_ctrl_is_std}, {rob_uop_60_ctrl_is_std}, {rob_uop_59_ctrl_is_std}, {rob_uop_58_ctrl_is_std}, {rob_uop_57_ctrl_is_std}, {rob_uop_56_ctrl_is_std}, {rob_uop_55_ctrl_is_std}, {rob_uop_54_ctrl_is_std}, {rob_uop_53_ctrl_is_std}, {rob_uop_52_ctrl_is_std}, {rob_uop_51_ctrl_is_std}, {rob_uop_50_ctrl_is_std}, {rob_uop_49_ctrl_is_std}, {rob_uop_48_ctrl_is_std}, {rob_uop_47_ctrl_is_std}, {rob_uop_46_ctrl_is_std}, {rob_uop_45_ctrl_is_std}, {rob_uop_44_ctrl_is_std}, {rob_uop_43_ctrl_is_std}, {rob_uop_42_ctrl_is_std}, {rob_uop_41_ctrl_is_std}, {rob_uop_40_ctrl_is_std}, {rob_uop_39_ctrl_is_std}, {rob_uop_38_ctrl_is_std}, {rob_uop_37_ctrl_is_std}, {rob_uop_36_ctrl_is_std}, {rob_uop_35_ctrl_is_std}, {rob_uop_34_ctrl_is_std}, {rob_uop_33_ctrl_is_std}, {rob_uop_32_ctrl_is_std}, {rob_uop_31_ctrl_is_std}, {rob_uop_30_ctrl_is_std}, {rob_uop_29_ctrl_is_std}, {rob_uop_28_ctrl_is_std}, {rob_uop_27_ctrl_is_std}, {rob_uop_26_ctrl_is_std}, {rob_uop_25_ctrl_is_std}, {rob_uop_24_ctrl_is_std}, {rob_uop_23_ctrl_is_std}, {rob_uop_22_ctrl_is_std}, {rob_uop_21_ctrl_is_std}, {rob_uop_20_ctrl_is_std}, {rob_uop_19_ctrl_is_std}, {rob_uop_18_ctrl_is_std}, {rob_uop_17_ctrl_is_std}, {rob_uop_16_ctrl_is_std}, {rob_uop_15_ctrl_is_std}, {rob_uop_14_ctrl_is_std}, {rob_uop_13_ctrl_is_std}, {rob_uop_12_ctrl_is_std}, {rob_uop_11_ctrl_is_std}, {rob_uop_10_ctrl_is_std}, {rob_uop_9_ctrl_is_std}, {rob_uop_8_ctrl_is_std}, {rob_uop_7_ctrl_is_std}, {rob_uop_6_ctrl_is_std}, {rob_uop_5_ctrl_is_std}, {rob_uop_4_ctrl_is_std}, {rob_uop_3_ctrl_is_std}, {rob_uop_2_ctrl_is_std}, {rob_uop_1_ctrl_is_std}, {rob_uop_0_ctrl_is_std}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_ctrl_is_std_0 = _GEN_9[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0][5:0] _GEN_10 = {{rob_uop_63_rob_idx}, {rob_uop_62_rob_idx}, {rob_uop_61_rob_idx}, {rob_uop_60_rob_idx}, {rob_uop_59_rob_idx}, {rob_uop_58_rob_idx}, {rob_uop_57_rob_idx}, {rob_uop_56_rob_idx}, {rob_uop_55_rob_idx}, {rob_uop_54_rob_idx}, {rob_uop_53_rob_idx}, {rob_uop_52_rob_idx}, {rob_uop_51_rob_idx}, {rob_uop_50_rob_idx}, {rob_uop_49_rob_idx}, {rob_uop_48_rob_idx}, {rob_uop_47_rob_idx}, {rob_uop_46_rob_idx}, {rob_uop_45_rob_idx}, {rob_uop_44_rob_idx}, {rob_uop_43_rob_idx}, {rob_uop_42_rob_idx}, {rob_uop_41_rob_idx}, {rob_uop_40_rob_idx}, {rob_uop_39_rob_idx}, {rob_uop_38_rob_idx}, {rob_uop_37_rob_idx}, {rob_uop_36_rob_idx}, {rob_uop_35_rob_idx}, {rob_uop_34_rob_idx}, {rob_uop_33_rob_idx}, {rob_uop_32_rob_idx}, {rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0][3:0] _GEN_11 = {{rob_uop_63_ldq_idx}, {rob_uop_62_ldq_idx}, {rob_uop_61_ldq_idx}, {rob_uop_60_ldq_idx}, {rob_uop_59_ldq_idx}, {rob_uop_58_ldq_idx}, {rob_uop_57_ldq_idx}, {rob_uop_56_ldq_idx}, {rob_uop_55_ldq_idx}, {rob_uop_54_ldq_idx}, {rob_uop_53_ldq_idx}, {rob_uop_52_ldq_idx}, {rob_uop_51_ldq_idx}, {rob_uop_50_ldq_idx}, {rob_uop_49_ldq_idx}, {rob_uop_48_ldq_idx}, {rob_uop_47_ldq_idx}, {rob_uop_46_ldq_idx}, {rob_uop_45_ldq_idx}, {rob_uop_44_ldq_idx}, {rob_uop_43_ldq_idx}, {rob_uop_42_ldq_idx}, {rob_uop_41_ldq_idx}, {rob_uop_40_ldq_idx}, {rob_uop_39_ldq_idx}, {rob_uop_38_ldq_idx}, {rob_uop_37_ldq_idx}, {rob_uop_36_ldq_idx}, {rob_uop_35_ldq_idx}, {rob_uop_34_ldq_idx}, {rob_uop_33_ldq_idx}, {rob_uop_32_ldq_idx}, {rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_11[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0][3:0] _GEN_12 = {{rob_uop_63_stq_idx}, {rob_uop_62_stq_idx}, {rob_uop_61_stq_idx}, {rob_uop_60_stq_idx}, {rob_uop_59_stq_idx}, {rob_uop_58_stq_idx}, {rob_uop_57_stq_idx}, {rob_uop_56_stq_idx}, {rob_uop_55_stq_idx}, {rob_uop_54_stq_idx}, {rob_uop_53_stq_idx}, {rob_uop_52_stq_idx}, {rob_uop_51_stq_idx}, {rob_uop_50_stq_idx}, {rob_uop_49_stq_idx}, {rob_uop_48_stq_idx}, {rob_uop_47_stq_idx}, {rob_uop_46_stq_idx}, {rob_uop_45_stq_idx}, {rob_uop_44_stq_idx}, {rob_uop_43_stq_idx}, {rob_uop_42_stq_idx}, {rob_uop_41_stq_idx}, {rob_uop_40_stq_idx}, {rob_uop_39_stq_idx}, {rob_uop_38_stq_idx}, {rob_uop_37_stq_idx}, {rob_uop_36_stq_idx}, {rob_uop_35_stq_idx}, {rob_uop_34_stq_idx}, {rob_uop_33_stq_idx}, {rob_uop_32_stq_idx}, {rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_12[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0][4:0] _GEN_13 = {{rob_uop_63_mem_cmd}, {rob_uop_62_mem_cmd}, {rob_uop_61_mem_cmd}, {rob_uop_60_mem_cmd}, {rob_uop_59_mem_cmd}, {rob_uop_58_mem_cmd}, {rob_uop_57_mem_cmd}, {rob_uop_56_mem_cmd}, {rob_uop_55_mem_cmd}, {rob_uop_54_mem_cmd}, {rob_uop_53_mem_cmd}, {rob_uop_52_mem_cmd}, {rob_uop_51_mem_cmd}, {rob_uop_50_mem_cmd}, {rob_uop_49_mem_cmd}, {rob_uop_48_mem_cmd}, {rob_uop_47_mem_cmd}, {rob_uop_46_mem_cmd}, {rob_uop_45_mem_cmd}, {rob_uop_44_mem_cmd}, {rob_uop_43_mem_cmd}, {rob_uop_42_mem_cmd}, {rob_uop_41_mem_cmd}, {rob_uop_40_mem_cmd}, {rob_uop_39_mem_cmd}, {rob_uop_38_mem_cmd}, {rob_uop_37_mem_cmd}, {rob_uop_36_mem_cmd}, {rob_uop_35_mem_cmd}, {rob_uop_34_mem_cmd}, {rob_uop_33_mem_cmd}, {rob_uop_32_mem_cmd}, {rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_13[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_14 = {{rob_uop_63_is_amo}, {rob_uop_62_is_amo}, {rob_uop_61_is_amo}, {rob_uop_60_is_amo}, {rob_uop_59_is_amo}, {rob_uop_58_is_amo}, {rob_uop_57_is_amo}, {rob_uop_56_is_amo}, {rob_uop_55_is_amo}, {rob_uop_54_is_amo}, {rob_uop_53_is_amo}, {rob_uop_52_is_amo}, {rob_uop_51_is_amo}, {rob_uop_50_is_amo}, {rob_uop_49_is_amo}, {rob_uop_48_is_amo}, {rob_uop_47_is_amo}, {rob_uop_46_is_amo}, {rob_uop_45_is_amo}, {rob_uop_44_is_amo}, {rob_uop_43_is_amo}, {rob_uop_42_is_amo}, {rob_uop_41_is_amo}, {rob_uop_40_is_amo}, {rob_uop_39_is_amo}, {rob_uop_38_is_amo}, {rob_uop_37_is_amo}, {rob_uop_36_is_amo}, {rob_uop_35_is_amo}, {rob_uop_34_is_amo}, {rob_uop_33_is_amo}, {rob_uop_32_is_amo}, {rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_is_amo_0 = _GEN_14[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_15 = {{rob_uop_63_uses_ldq}, {rob_uop_62_uses_ldq}, {rob_uop_61_uses_ldq}, {rob_uop_60_uses_ldq}, {rob_uop_59_uses_ldq}, {rob_uop_58_uses_ldq}, {rob_uop_57_uses_ldq}, {rob_uop_56_uses_ldq}, {rob_uop_55_uses_ldq}, {rob_uop_54_uses_ldq}, {rob_uop_53_uses_ldq}, {rob_uop_52_uses_ldq}, {rob_uop_51_uses_ldq}, {rob_uop_50_uses_ldq}, {rob_uop_49_uses_ldq}, {rob_uop_48_uses_ldq}, {rob_uop_47_uses_ldq}, {rob_uop_46_uses_ldq}, {rob_uop_45_uses_ldq}, {rob_uop_44_uses_ldq}, {rob_uop_43_uses_ldq}, {rob_uop_42_uses_ldq}, {rob_uop_41_uses_ldq}, {rob_uop_40_uses_ldq}, {rob_uop_39_uses_ldq}, {rob_uop_38_uses_ldq}, {rob_uop_37_uses_ldq}, {rob_uop_36_uses_ldq}, {rob_uop_35_uses_ldq}, {rob_uop_34_uses_ldq}, {rob_uop_33_uses_ldq}, {rob_uop_32_uses_ldq}, {rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_15[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire [63:0] _GEN_16 = {{rob_uop_63_uses_stq}, {rob_uop_62_uses_stq}, {rob_uop_61_uses_stq}, {rob_uop_60_uses_stq}, {rob_uop_59_uses_stq}, {rob_uop_58_uses_stq}, {rob_uop_57_uses_stq}, {rob_uop_56_uses_stq}, {rob_uop_55_uses_stq}, {rob_uop_54_uses_stq}, {rob_uop_53_uses_stq}, {rob_uop_52_uses_stq}, {rob_uop_51_uses_stq}, {rob_uop_50_uses_stq}, {rob_uop_49_uses_stq}, {rob_uop_48_uses_stq}, {rob_uop_47_uses_stq}, {rob_uop_46_uses_stq}, {rob_uop_45_uses_stq}, {rob_uop_44_uses_stq}, {rob_uop_43_uses_stq}, {rob_uop_42_uses_stq}, {rob_uop_41_uses_stq}, {rob_uop_40_uses_stq}, {rob_uop_39_uses_stq}, {rob_uop_38_uses_stq}, {rob_uop_37_uses_stq}, {rob_uop_36_uses_stq}, {rob_uop_35_uses_stq}, {rob_uop_34_uses_stq}, {rob_uop_33_uses_stq}, {rob_uop_32_uses_stq}, {rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:34:20, :96:27]
assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_16[rob_head]; // @[tracegen.scala:20:7, :36:25, :96:27]
wire _rob_head_T = &rob_head; // @[tracegen.scala:36:25, :45:13]
wire [6:0] _rob_head_T_1 = {1'h0, rob_head} + 7'h1; // @[tracegen.scala:36:25, :45:37]
wire [5:0] _rob_head_T_2 = _rob_head_T_1[5:0]; // @[tracegen.scala:45:37]
wire [5:0] _rob_head_T_3 = _rob_head_T ? 6'h0 : _rob_head_T_2; // @[tracegen.scala:45:{8,13,37}] |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_99( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_26( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_193( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulRawFN_1( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_1 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_13( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_83( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_100 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module IntSyncSyncCrossingSink_n1x1_19(); // @[Crossing.scala:96:9]
wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PMA.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters}
class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
val paddr = Input(UInt())
val resp = Output(new Bundle {
val cacheable = Bool()
val r = Bool()
val w = Bool()
val pp = Bool()
val al = Bool()
val aa = Bool()
val x = Bool()
val eff = Bool()
})
})
// PMA
// check exist a slave can consume this address.
val legal_address = manager.findSafe(io.paddr).reduce(_||_)
// check utility to help check SoC property.
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
io.resp.cacheable := fastCheck(_.supportsAcquireB)
io.resp.r := fastCheck(_.supportsGet)
io.resp.w := fastCheck(_.supportsPutFull)
io.resp.pp := fastCheck(_.supportsPutPartial)
io.resp.al := fastCheck(_.supportsLogical)
io.resp.aa := fastCheck(_.supportsArithmetic)
io.resp.x := fastCheck(_.executable)
io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module PMAChecker_2( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_25; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_43; // @[PMA.scala:39:19]
wire _io_resp_pp_T_43; // @[PMA.scala:39:19]
wire _io_resp_al_T_43; // @[PMA.scala:39:19]
wire _io_resp_aa_T_43; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31]
assign _io_resp_w_T_35 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_35 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31]
assign _io_resp_al_T_35 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_35 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_11; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_11 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_45 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000040}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000080}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_55 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h80000C0}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_60 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000100}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46]
wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_65 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000140}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46]
wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_70 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000180}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46]
wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_75 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h80001C0}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46]
wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31]
assign _legal_address_T_80 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46]
wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_85; // @[Parameters.scala:137:31]
assign _legal_address_T_85 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_86 = {1'h0, _legal_address_T_85}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_87 = _legal_address_T_86 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_88 = _legal_address_T_87; // @[Parameters.scala:137:46]
wire _legal_address_T_89 = _legal_address_T_88 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_17 = _legal_address_T_89; // @[Parameters.scala:612:40]
wire [39:0] _GEN_8 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_90; // @[Parameters.scala:137:31]
assign _legal_address_T_90 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_16; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_16 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_91 = {1'h0, _legal_address_T_90}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_92 = _legal_address_T_91 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_93 = _legal_address_T_92; // @[Parameters.scala:137:46]
wire _legal_address_T_94 = _legal_address_T_93 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_18 = _legal_address_T_94; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_95 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000040}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_96 = {1'h0, _legal_address_T_95}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_97 = _legal_address_T_96 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_98 = _legal_address_T_97; // @[Parameters.scala:137:46]
wire _legal_address_T_99 = _legal_address_T_98 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_19 = _legal_address_T_99; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_100 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000080}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_101 = {1'h0, _legal_address_T_100}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_102 = _legal_address_T_101 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_103 = _legal_address_T_102; // @[Parameters.scala:137:46]
wire _legal_address_T_104 = _legal_address_T_103 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_20 = _legal_address_T_104; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_105 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h800000C0}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_106 = {1'h0, _legal_address_T_105}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_107 = _legal_address_T_106 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_108 = _legal_address_T_107; // @[Parameters.scala:137:46]
wire _legal_address_T_109 = _legal_address_T_108 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_21 = _legal_address_T_109; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_110 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000100}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_111 = {1'h0, _legal_address_T_110}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_112 = _legal_address_T_111 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_113 = _legal_address_T_112; // @[Parameters.scala:137:46]
wire _legal_address_T_114 = _legal_address_T_113 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_22 = _legal_address_T_114; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_115 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000140}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_116 = {1'h0, _legal_address_T_115}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_117 = _legal_address_T_116 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_118 = _legal_address_T_117; // @[Parameters.scala:137:46]
wire _legal_address_T_119 = _legal_address_T_118 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_23 = _legal_address_T_119; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_120 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000180}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_121 = {1'h0, _legal_address_T_120}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_122 = _legal_address_T_121 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_123 = _legal_address_T_122; // @[Parameters.scala:137:46]
wire _legal_address_T_124 = _legal_address_T_123 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_24 = _legal_address_T_124; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_125 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h800001C0}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_126 = {1'h0, _legal_address_T_125}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_127 = _legal_address_T_126 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_128 = _legal_address_T_127; // @[Parameters.scala:137:46]
wire _legal_address_T_129 = _legal_address_T_128 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_25 = _legal_address_T_129; // @[Parameters.scala:612:40]
wire _legal_address_T_130 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_131 = _legal_address_T_130 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_132 = _legal_address_T_131 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_133 = _legal_address_T_132 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_134 = _legal_address_T_133 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_135 = _legal_address_T_134 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_136 = _legal_address_T_135 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_137 = _legal_address_T_136 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_138 = _legal_address_T_137 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_139 = _legal_address_T_138 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire _legal_address_T_140 = _legal_address_T_139 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
wire _legal_address_T_141 = _legal_address_T_140 | _legal_address_WIRE_12; // @[Parameters.scala:612:40]
wire _legal_address_T_142 = _legal_address_T_141 | _legal_address_WIRE_13; // @[Parameters.scala:612:40]
wire _legal_address_T_143 = _legal_address_T_142 | _legal_address_WIRE_14; // @[Parameters.scala:612:40]
wire _legal_address_T_144 = _legal_address_T_143 | _legal_address_WIRE_15; // @[Parameters.scala:612:40]
wire _legal_address_T_145 = _legal_address_T_144 | _legal_address_WIRE_16; // @[Parameters.scala:612:40]
wire _legal_address_T_146 = _legal_address_T_145 | _legal_address_WIRE_17; // @[Parameters.scala:612:40]
wire _legal_address_T_147 = _legal_address_T_146 | _legal_address_WIRE_18; // @[Parameters.scala:612:40]
wire _legal_address_T_148 = _legal_address_T_147 | _legal_address_WIRE_19; // @[Parameters.scala:612:40]
wire _legal_address_T_149 = _legal_address_T_148 | _legal_address_WIRE_20; // @[Parameters.scala:612:40]
wire _legal_address_T_150 = _legal_address_T_149 | _legal_address_WIRE_21; // @[Parameters.scala:612:40]
wire _legal_address_T_151 = _legal_address_T_150 | _legal_address_WIRE_22; // @[Parameters.scala:612:40]
wire _legal_address_T_152 = _legal_address_T_151 | _legal_address_WIRE_23; // @[Parameters.scala:612:40]
wire _legal_address_T_153 = _legal_address_T_152 | _legal_address_WIRE_24; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_153 | _legal_address_WIRE_25; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_10 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_12 = {1'h0, _io_resp_cacheable_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_17 = {1'h0, _io_resp_cacheable_T_16}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_20; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_23 = _io_resp_cacheable_T_21; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_24; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_25 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_25; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_30 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_31 = _io_resp_w_T_30 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_32 = _io_resp_w_T_31 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_33 = _io_resp_w_T_32 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_34 = _io_resp_w_T_33 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46]
wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_42 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_42; // @[Mux.scala:30:73]
assign _io_resp_w_T_43 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_43; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_30 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_31 = _io_resp_pp_T_30 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_32 = _io_resp_pp_T_31 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_33 = _io_resp_pp_T_32 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_42 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_42; // @[Mux.scala:30:73]
assign _io_resp_pp_T_43 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_43; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_30 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_31 = _io_resp_al_T_30 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_32 = _io_resp_al_T_31 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_33 = _io_resp_al_T_32 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_34 = _io_resp_al_T_33 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46]
wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_42 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_42; // @[Mux.scala:30:73]
assign _io_resp_al_T_43 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_43; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_30 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_31 = _io_resp_aa_T_30 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_32 = _io_resp_aa_T_31 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_33 = _io_resp_aa_T_32 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_42 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_42; // @[Mux.scala:30:73]
assign _io_resp_aa_T_43 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_43; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFEE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [39:0] _io_resp_eff_T_35 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h2000}; // @[PMA.scala:18:7]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Manager.scala:
package rerocc.manager
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem._
import rerocc.bus._
case class ReRoCCManagerParams(
managerId: Int,
)
case object ReRoCCManagerControlAddress extends Field[BigInt](0x20000)
// For local PTW
class MiniDCache(reRoCCId: Int, crossing: ClockCrossingType)(implicit p: Parameters) extends DCache(0, crossing)(p) {
override def cacheClientParameters = Seq(TLMasterParameters.v1(
name = s"ReRoCC ${reRoCCId} DCache",
sourceId = IdRange(0, 1),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))
override def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"ReRoCC ${reRoCCId} DCache MMIO",
sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),
requestFifo = true))
}
class ReRoCCManager(reRoCCTileParams: ReRoCCTileParams, roccOpcode: UInt)(implicit p: Parameters) extends LazyModule {
val node = ReRoCCManagerNode(ReRoCCManagerParams(reRoCCTileParams.reroccId))
val ibufEntries = p(ReRoCCIBufEntriesKey)
override lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val manager_id = Input(UInt(log2Ceil(p(ReRoCCTileKey).size).W))
val cmd = Decoupled(new RoCCCommand)
val resp = Flipped(Decoupled(new RoCCResponse))
val busy = Input(Bool())
val ptw = Flipped(new DatapathPTWIO)
})
val (rerocc, edge) = node.in(0)
val s_idle :: s_active :: s_rel_wait :: s_sfence :: s_unbusy :: Nil = Enum(5)
val numClients = edge.cParams.clients.map(_.nCfgs).sum
val client = Reg(UInt(log2Ceil(numClients).W))
val status = Reg(new MStatus)
val ptbr = Reg(new PTBR)
val state = RegInit(s_idle)
io.ptw.ptbr := ptbr
io.ptw.hgatp := 0.U.asTypeOf(new PTBR)
io.ptw.vsatp := 0.U.asTypeOf(new PTBR)
io.ptw.sfence.valid := state === s_sfence
io.ptw.sfence.bits.rs1 := false.B
io.ptw.sfence.bits.rs2 := false.B
io.ptw.sfence.bits.addr := 0.U
io.ptw.sfence.bits.asid := 0.U
io.ptw.sfence.bits.hv := false.B
io.ptw.sfence.bits.hg := false.B
io.ptw.status := status
io.ptw.hstatus := 0.U.asTypeOf(new HStatus)
io.ptw.gstatus := 0.U.asTypeOf(new MStatus)
io.ptw.pmp.foreach(_ := 0.U.asTypeOf(new PMP))
val rr_req = Queue(rerocc.req)
val (req_first, req_last, req_beat) = ReRoCCMsgFirstLast(rr_req, true)
val rr_resp = rerocc.resp
rr_req.ready := false.B
val inst_q = Module(new Queue(new RoCCCommand, ibufEntries))
val enq_inst = Reg(new RoCCCommand)
val next_enq_inst = WireInit(enq_inst)
inst_q.io.enq.valid := false.B
inst_q.io.enq.bits := next_enq_inst
inst_q.io.enq.bits.inst.opcode := roccOpcode
// 0 -> acquire ack
// 1 -> inst ack
// 2 -> writeback
// 3 -> rel
// 4 -> unbusyack
val resp_arb = Module(new ReRoCCMsgArbiter(edge.bundle, 5, false))
rr_resp <> resp_arb.io.out
resp_arb.io.in.foreach { i => i.valid := false.B }
val status_lower = Reg(UInt(64.W))
when (rr_req.valid) {
when (rr_req.bits.opcode === ReRoCCProtocol.mAcquire) {
rr_req.ready := resp_arb.io.in(0).ready
resp_arb.io.in(0).valid := true.B
when (state === s_idle && rr_req.fire) {
state := s_active
client := rr_req.bits.client_id
}
} .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUStatus) {
rr_req.ready := !inst_q.io.deq.valid && !io.busy
when (!inst_q.io.deq.valid && !io.busy) {
when (req_first) { status_lower := rr_req.bits.data }
when (req_last) { status := Cat(rr_req.bits.data, status_lower).asTypeOf(new MStatus) }
}
} .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUPtbr) {
rr_req.ready := !inst_q.io.deq.valid && !io.busy
when (!inst_q.io.deq.valid && !io.busy) { ptbr := rr_req.bits.data.asTypeOf(new PTBR) }
} .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mInst) {
assert(state === s_active && inst_q.io.enq.ready)
rr_req.ready := true.B
when (req_beat === 0.U) {
val inst = rr_req.bits.data.asTypeOf(new RoCCInstruction)
enq_inst.inst := inst
when (!inst.xs1 ) { enq_inst.rs1 := 0.U }
when (!inst.xs2 ) { enq_inst.rs2 := 0.U }
} .otherwise {
val enq_inst_rs1 = enq_inst.inst.xs1 && req_beat === 1.U
val enq_inst_rs2 = enq_inst.inst.xs2 && req_beat === Mux(enq_inst.inst.xs1, 2.U, 1.U)
when (enq_inst_rs1) { next_enq_inst.rs1 := rr_req.bits.data }
when (enq_inst_rs2) { next_enq_inst.rs2 := rr_req.bits.data }
enq_inst := next_enq_inst
}
when (req_last) {
inst_q.io.enq.valid := true.B
assert(inst_q.io.enq.ready)
}
} .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mRelease) {
rr_req.ready := true.B
state := s_rel_wait
} .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUnbusy) {
rr_req.ready := true.B
state := s_unbusy
} .otherwise {
assert(false.B)
}
}
// acquire->ack/nack
resp_arb.io.in(0).bits.opcode := ReRoCCProtocol.sAcqResp
resp_arb.io.in(0).bits.client_id := rr_req.bits.client_id
resp_arb.io.in(0).bits.manager_id := io.manager_id
resp_arb.io.in(0).bits.data := state === s_idle
// insts -> (inst_q, inst_ack)
io.cmd.valid := inst_q.io.deq.valid && resp_arb.io.in(1).ready
io.cmd.bits := inst_q.io.deq.bits
inst_q.io.deq.ready := io.cmd.ready && resp_arb.io.in(1).ready
resp_arb.io.in(1).valid := inst_q.io.deq.valid && io.cmd.ready
resp_arb.io.in(1).bits.opcode := ReRoCCProtocol.sInstAck
resp_arb.io.in(1).bits.client_id := client
resp_arb.io.in(1).bits.manager_id := io.manager_id
resp_arb.io.in(1).bits.data := 0.U
// writebacks
val resp = Queue(io.resp)
val resp_rd = RegInit(false.B)
resp_arb.io.in(2).valid := resp.valid
resp_arb.io.in(2).bits.opcode := ReRoCCProtocol.sWrite
resp_arb.io.in(2).bits.client_id := client
resp_arb.io.in(2).bits.manager_id := io.manager_id
resp_arb.io.in(2).bits.data := Mux(resp_rd, resp.bits.rd, resp.bits.data)
when (resp_arb.io.in(2).fire) { resp_rd := !resp_rd }
resp.ready := resp_arb.io.in(2).ready && resp_rd
// release
resp_arb.io.in(3).valid := state === s_rel_wait && !io.busy && inst_q.io.count === 0.U
resp_arb.io.in(3).bits.opcode := ReRoCCProtocol.sRelResp
resp_arb.io.in(3).bits.client_id := client
resp_arb.io.in(3).bits.manager_id := io.manager_id
resp_arb.io.in(3).bits.data := 0.U
when (resp_arb.io.in(3).fire) {
state := s_sfence
}
when (state === s_sfence) { state := s_idle }
// unbusyack
resp_arb.io.in(4).valid := state === s_unbusy && !io.busy && inst_q.io.count === 0.U
resp_arb.io.in(4).bits.opcode := ReRoCCProtocol.sUnbusyAck
resp_arb.io.in(4).bits.client_id := client
resp_arb.io.in(4).bits.manager_id := io.manager_id
resp_arb.io.in(4).bits.data := 0.U
when (resp_arb.io.in(4).fire) { state := s_active }
}
}
class ReRoCCManagerTile()(implicit p: Parameters) extends LazyModule {
val reRoCCParams = p(TileKey).asInstanceOf[ReRoCCTileParams]
val reRoCCId = reRoCCParams.reroccId
def this(tileParams: ReRoCCTileParams, p: Parameters) = {
this()(p.alterMap(Map(
TileKey -> tileParams,
TileVisibilityNodeKey -> TLEphemeralNode()(ValName("rerocc_manager"))
)))
}
val reroccManagerIdSinkNode = BundleBridgeSink[UInt]()
val rocc = reRoCCParams.genRoCC.get(p)
require(rocc.opcodes.opcodes.size == 1)
val rerocc_manager = LazyModule(new ReRoCCManager(reRoCCParams, rocc.opcodes.opcodes.head))
val reRoCCNode = ReRoCCIdentityNode()
rerocc_manager.node := ReRoCCBuffer() := reRoCCNode
val tlNode = p(TileVisibilityNodeKey) // throttle before TL Node (merged ->
val tlXbar = TLXbar()
val stlNode = TLIdentityNode()
tlXbar :=* rocc.atlNode
if (reRoCCParams.mergeTLNodes) {
tlXbar :=* rocc.tlNode
} else {
tlNode :=* rocc.tlNode
}
tlNode :=* TLBuffer() :=* tlXbar
rocc.stlNode :*= stlNode
// minicache
val dcache = reRoCCParams.dcacheParams.map(_ => LazyModule(new MiniDCache(reRoCCId, SynchronousCrossing())(p)))
dcache.map(d => tlXbar := TLWidthWidget(reRoCCParams.rowBits/8) := d.node)
val hellammio: Option[HellaMMIO] = if (!dcache.isDefined) {
val h = LazyModule(new HellaMMIO(s"ReRoCC $reRoCCId MMIO"))
tlXbar := h.node
Some(h)
} else { None }
val ctrl = LazyModule(new ReRoCCManagerControl(reRoCCId, 8))
override lazy val module = new LazyModuleImp(this) {
val dcacheArb = Module(new HellaCacheArbiter(2)(p))
dcache.map(_.module.io.cpu).getOrElse(hellammio.get.module.io) <> dcacheArb.io.mem
val edge = dcache.map(_.node.edges.out(0)).getOrElse(hellammio.get.node.edges.out(0))
val ptw = Module(new PTW(1 + rocc.nPTWPorts)(edge, p))
if (dcache.isDefined) {
dcache.get.module.io.tlb_port := DontCare
dcache.get.module.io.tlb_port.req.valid := false.B
ptw.io.requestor(0) <> dcache.get.module.io.ptw
} else {
ptw.io.requestor(0) := DontCare
ptw.io.requestor(0).req.valid := false.B
}
dcacheArb.io.requestor(0) <> ptw.io.mem
val dcIF = Module(new SimpleHellaCacheIF)
dcIF.io.requestor <> rocc.module.io.mem
dcacheArb.io.requestor(1) <> dcIF.io.cache
for (i <- 0 until rocc.nPTWPorts) {
ptw.io.requestor(1+i) <> rocc.module.io.ptw(i)
}
rerocc_manager.module.io.manager_id := reroccManagerIdSinkNode.bundle
rocc.module.io.cmd <> rerocc_manager.module.io.cmd
rerocc_manager.module.io.resp <> rocc.module.io.resp
rerocc_manager.module.io.busy := rocc.module.io.busy
ptw.io.dpath <> rerocc_manager.module.io.ptw
rocc.module.io.fpu_req.ready := false.B
assert(!rocc.module.io.fpu_req.valid)
rocc.module.io.fpu_resp.valid := false.B
rocc.module.io.fpu_resp.bits := DontCare
rocc.module.io.exception := false.B
ctrl.module.io.mgr_busy := rerocc_manager.module.io.busy
ctrl.module.io.rocc_busy := rocc.module.io.busy
}
}
File Protocol.scala:
package rerocc.bus
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import rerocc.client.{ReRoCCClientParams}
import rerocc.manager.{ReRoCCManagerParams}
object ReRoCCProtocol {
val width = 3
val mAcquire = 0.U(width.W)
// beat0: data = inst
// beat1: data = mstatus[63:0]
// beat2: data = mstatus[127:64]
val mInst = 1.U(width.W)
// beat0: data = mstatus[63:0]
// beat1: data = mstatus[127:0]
val mUStatus = 2.U(width.W)
// beat0: data = ptbr
val mUPtbr = 3.U(width.W)
val mRelease = 4.U(width.W)
val mUnbusy = 5.U(width.W)
// data
// data = acquired
val sAcqResp = 0.U(width.W)
// data = 0
val sInstAck = 1.U(width.W)
// beat0: data = data
// beat1: data = rd
val sWrite = 2.U(width.W)
val sRelResp = 3.U(width.W)
val sUnbusyAck = 4.U(width.W)
val MAX_BEATS = 3
}
class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle {
val opcode = UInt(ReRoCCProtocol.width.W)
val client_id = UInt(params.clientIdBits.W)
val manager_id = UInt(params.managerIdBits.W)
val data = UInt(64.W)
}
object ReRoCCMsgFirstLast {
def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = {
val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W))
val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W))
val first = beat === 0.U
val last = Wire(Bool())
val inst = m.bits.data.asTypeOf(new RoCCInstruction)
when (m.fire && first) {
max_beat := 0.U
if (isReq) {
when (m.bits.opcode === ReRoCCProtocol.mInst) {
max_beat := inst.xs1 +& inst.xs2
} .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) {
max_beat := 1.U
}
} else {
when (m.bits.opcode === ReRoCCProtocol.sWrite) {
max_beat := 1.U
}
}
}
last := true.B
if (isReq) {
when (m.bits.opcode === ReRoCCProtocol.mUStatus) {
last := beat === max_beat && !first
} .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) {
last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat)
}
} else {
when (m.bits.opcode === ReRoCCProtocol.sWrite) {
last := beat === max_beat && !first
}
}
when (m.fire) { beat := beat + 1.U }
when (m.fire && last) {
max_beat := 0.U
beat := 0.U
}
(first, last, beat)
}
}
class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle {
val req = Decoupled(new ReRoCCMsgBundle(params))
val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params)))
}
case class EmptyParams()
object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] {
def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = {
ReRoCCEdgeParams(pu, pd)
}
def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle)
def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black */)
}
case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams))))
case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams))))
class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule {
val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s})
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, _), (out, _)) =>
out.req <> b(in.req)
in.resp <> b(out.resp)
}
}
}
object ReRoCCBuffer {
def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = {
val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p))
rerocc_buffer.node
}
}
case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)()
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module ReRoCCManager_2( // @[Manager.scala:38:9]
input clock, // @[Manager.scala:38:9]
input reset, // @[Manager.scala:38:9]
output auto_in_req_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_req_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_req_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_resp_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_resp_bits_data, // @[LazyModuleImp.scala:107:25]
input [2:0] io_manager_id, // @[Manager.scala:39:16]
input io_cmd_ready, // @[Manager.scala:39:16]
output io_cmd_valid, // @[Manager.scala:39:16]
output [6:0] io_cmd_bits_inst_funct, // @[Manager.scala:39:16]
output [4:0] io_cmd_bits_inst_rs2, // @[Manager.scala:39:16]
output [4:0] io_cmd_bits_inst_rs1, // @[Manager.scala:39:16]
output io_cmd_bits_inst_xd, // @[Manager.scala:39:16]
output io_cmd_bits_inst_xs1, // @[Manager.scala:39:16]
output io_cmd_bits_inst_xs2, // @[Manager.scala:39:16]
output [4:0] io_cmd_bits_inst_rd, // @[Manager.scala:39:16]
output [6:0] io_cmd_bits_inst_opcode, // @[Manager.scala:39:16]
output [63:0] io_cmd_bits_rs1, // @[Manager.scala:39:16]
output [63:0] io_cmd_bits_rs2, // @[Manager.scala:39:16]
output io_cmd_bits_status_debug, // @[Manager.scala:39:16]
output io_cmd_bits_status_cease, // @[Manager.scala:39:16]
output io_cmd_bits_status_wfi, // @[Manager.scala:39:16]
output [31:0] io_cmd_bits_status_isa, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_dprv, // @[Manager.scala:39:16]
output io_cmd_bits_status_dv, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_prv, // @[Manager.scala:39:16]
output io_cmd_bits_status_v, // @[Manager.scala:39:16]
output io_cmd_bits_status_sd, // @[Manager.scala:39:16]
output [22:0] io_cmd_bits_status_zero2, // @[Manager.scala:39:16]
output io_cmd_bits_status_mpv, // @[Manager.scala:39:16]
output io_cmd_bits_status_gva, // @[Manager.scala:39:16]
output io_cmd_bits_status_mbe, // @[Manager.scala:39:16]
output io_cmd_bits_status_sbe, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_sxl, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_uxl, // @[Manager.scala:39:16]
output io_cmd_bits_status_sd_rv32, // @[Manager.scala:39:16]
output [7:0] io_cmd_bits_status_zero1, // @[Manager.scala:39:16]
output io_cmd_bits_status_tsr, // @[Manager.scala:39:16]
output io_cmd_bits_status_tw, // @[Manager.scala:39:16]
output io_cmd_bits_status_tvm, // @[Manager.scala:39:16]
output io_cmd_bits_status_mxr, // @[Manager.scala:39:16]
output io_cmd_bits_status_sum, // @[Manager.scala:39:16]
output io_cmd_bits_status_mprv, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_xs, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_fs, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_mpp, // @[Manager.scala:39:16]
output [1:0] io_cmd_bits_status_vs, // @[Manager.scala:39:16]
output io_cmd_bits_status_spp, // @[Manager.scala:39:16]
output io_cmd_bits_status_mpie, // @[Manager.scala:39:16]
output io_cmd_bits_status_ube, // @[Manager.scala:39:16]
output io_cmd_bits_status_spie, // @[Manager.scala:39:16]
output io_cmd_bits_status_upie, // @[Manager.scala:39:16]
output io_cmd_bits_status_mie, // @[Manager.scala:39:16]
output io_cmd_bits_status_hie, // @[Manager.scala:39:16]
output io_cmd_bits_status_sie, // @[Manager.scala:39:16]
output io_cmd_bits_status_uie, // @[Manager.scala:39:16]
output io_resp_ready, // @[Manager.scala:39:16]
input io_resp_valid, // @[Manager.scala:39:16]
input [4:0] io_resp_bits_rd, // @[Manager.scala:39:16]
input [63:0] io_resp_bits_data, // @[Manager.scala:39:16]
input io_busy, // @[Manager.scala:39:16]
output [3:0] io_ptw_ptbr_mode, // @[Manager.scala:39:16]
output [15:0] io_ptw_ptbr_asid, // @[Manager.scala:39:16]
output [43:0] io_ptw_ptbr_ppn, // @[Manager.scala:39:16]
output io_ptw_sfence_valid, // @[Manager.scala:39:16]
output io_ptw_status_debug, // @[Manager.scala:39:16]
output io_ptw_status_cease, // @[Manager.scala:39:16]
output io_ptw_status_wfi, // @[Manager.scala:39:16]
output [31:0] io_ptw_status_isa, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_dprv, // @[Manager.scala:39:16]
output io_ptw_status_dv, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_prv, // @[Manager.scala:39:16]
output io_ptw_status_v, // @[Manager.scala:39:16]
output io_ptw_status_sd, // @[Manager.scala:39:16]
output [22:0] io_ptw_status_zero2, // @[Manager.scala:39:16]
output io_ptw_status_mpv, // @[Manager.scala:39:16]
output io_ptw_status_gva, // @[Manager.scala:39:16]
output io_ptw_status_mbe, // @[Manager.scala:39:16]
output io_ptw_status_sbe, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_sxl, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_uxl, // @[Manager.scala:39:16]
output io_ptw_status_sd_rv32, // @[Manager.scala:39:16]
output [7:0] io_ptw_status_zero1, // @[Manager.scala:39:16]
output io_ptw_status_tsr, // @[Manager.scala:39:16]
output io_ptw_status_tw, // @[Manager.scala:39:16]
output io_ptw_status_tvm, // @[Manager.scala:39:16]
output io_ptw_status_mxr, // @[Manager.scala:39:16]
output io_ptw_status_sum, // @[Manager.scala:39:16]
output io_ptw_status_mprv, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_xs, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_fs, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_mpp, // @[Manager.scala:39:16]
output [1:0] io_ptw_status_vs, // @[Manager.scala:39:16]
output io_ptw_status_spp, // @[Manager.scala:39:16]
output io_ptw_status_mpie, // @[Manager.scala:39:16]
output io_ptw_status_ube, // @[Manager.scala:39:16]
output io_ptw_status_spie, // @[Manager.scala:39:16]
output io_ptw_status_upie, // @[Manager.scala:39:16]
output io_ptw_status_mie, // @[Manager.scala:39:16]
output io_ptw_status_hie, // @[Manager.scala:39:16]
output io_ptw_status_sie, // @[Manager.scala:39:16]
output io_ptw_status_uie, // @[Manager.scala:39:16]
input io_ptw_perf_pte_miss, // @[Manager.scala:39:16]
input io_ptw_clock_enabled // @[Manager.scala:39:16]
);
wire _resp_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [4:0] _resp_q_io_deq_bits_rd; // @[Decoupled.scala:362:21]
wire [63:0] _resp_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _resp_arb_io_in_0_ready; // @[Manager.scala:91:26]
wire _resp_arb_io_in_1_ready; // @[Manager.scala:91:26]
wire _resp_arb_io_in_2_ready; // @[Manager.scala:91:26]
wire _resp_arb_io_in_3_ready; // @[Manager.scala:91:26]
wire _resp_arb_io_in_4_ready; // @[Manager.scala:91:26]
wire _inst_q_io_enq_ready; // @[Manager.scala:79:24]
wire _inst_q_io_deq_valid; // @[Manager.scala:79:24]
wire [2:0] _inst_q_io_count; // @[Manager.scala:79:24]
wire _rr_req_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _rr_req_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [3:0] _rr_req_q_io_deq_bits_client_id; // @[Decoupled.scala:362:21]
wire [63:0] _rr_req_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire auto_in_req_valid_0 = auto_in_req_valid; // @[Manager.scala:38:9]
wire [2:0] auto_in_req_bits_opcode_0 = auto_in_req_bits_opcode; // @[Manager.scala:38:9]
wire [3:0] auto_in_req_bits_client_id_0 = auto_in_req_bits_client_id; // @[Manager.scala:38:9]
wire auto_in_req_bits_manager_id_0 = auto_in_req_bits_manager_id; // @[Manager.scala:38:9]
wire [63:0] auto_in_req_bits_data_0 = auto_in_req_bits_data; // @[Manager.scala:38:9]
wire auto_in_resp_ready_0 = auto_in_resp_ready; // @[Manager.scala:38:9]
wire [2:0] io_manager_id_0 = io_manager_id; // @[Manager.scala:38:9]
wire io_cmd_ready_0 = io_cmd_ready; // @[Manager.scala:38:9]
wire io_resp_valid_0 = io_resp_valid; // @[Manager.scala:38:9]
wire [4:0] io_resp_bits_rd_0 = io_resp_bits_rd; // @[Manager.scala:38:9]
wire [63:0] io_resp_bits_data_0 = io_resp_bits_data; // @[Manager.scala:38:9]
wire io_busy_0 = io_busy; // @[Manager.scala:38:9]
wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[Manager.scala:38:9]
wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[Manager.scala:38:9]
wire io_ptw_sfence_bits_rs1 = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_sfence_bits_rs2 = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_sfence_bits_asid = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_sfence_bits_hv = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_sfence_bits_hg = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_vtsr = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_vtw = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_vtvm = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_hu = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_spvp = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_spv = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_gva = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_hstatus_vsbe = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_debug = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_cease = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_wfi = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_dv = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_v = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_sd = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mpv = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_gva = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mbe = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_sbe = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_tsr = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_tw = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_tvm = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mxr = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_sum = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mprv = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_spp = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mpie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_ube = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_spie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_upie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_mie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_hie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_sie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_gstatus_uie = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_perf_l2miss = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_perf_l2hit = 1'h0; // @[Manager.scala:38:9]
wire io_ptw_perf_pte_hit = 1'h0; // @[Manager.scala:38:9]
wire _io_ptw_hstatus_WIRE_vtsr = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_vtw = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_vtvm = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_hu = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_spvp = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_spv = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_gva = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_hstatus_WIRE_vsbe = 1'h0; // @[Manager.scala:69:35]
wire _io_ptw_gstatus_WIRE_debug = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_cease = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_wfi = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_dv = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_v = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_sd = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mpv = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_gva = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mbe = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_sbe = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_sd_rv32 = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_tsr = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_tw = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_tvm = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mxr = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_sum = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mprv = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_spp = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mpie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_ube = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_spie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_upie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_mie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_hie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_sie = 1'h0; // @[Manager.scala:70:35]
wire _io_ptw_gstatus_WIRE_uie = 1'h0; // @[Manager.scala:70:35]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Manager.scala:38:9]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Manager.scala:38:9]
wire [3:0] _io_ptw_hgatp_WIRE_mode = 4'h0; // @[Manager.scala:58:33]
wire [3:0] _io_ptw_vsatp_WIRE_mode = 4'h0; // @[Manager.scala:59:33]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Manager.scala:38:9]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Manager.scala:38:9]
wire [15:0] _io_ptw_hgatp_WIRE_asid = 16'h0; // @[Manager.scala:58:33]
wire [15:0] _io_ptw_vsatp_WIRE_asid = 16'h0; // @[Manager.scala:59:33]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Manager.scala:38:9]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Manager.scala:38:9]
wire [43:0] _io_ptw_hgatp_WIRE_ppn = 44'h0; // @[Manager.scala:58:33]
wire [43:0] _io_ptw_vsatp_WIRE_ppn = 44'h0; // @[Manager.scala:59:33]
wire [38:0] io_ptw_sfence_bits_addr = 39'h0; // @[Manager.scala:38:9]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Manager.scala:38:9]
wire [29:0] _io_ptw_hstatus_WIRE_zero6 = 30'h0; // @[Manager.scala:69:35]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[Manager.scala:38:9]
wire [1:0] _io_ptw_hstatus_WIRE_vsxl = 2'h0; // @[Manager.scala:69:35]
wire [1:0] _io_ptw_hstatus_WIRE_zero3 = 2'h0; // @[Manager.scala:69:35]
wire [1:0] _io_ptw_hstatus_WIRE_zero2 = 2'h0; // @[Manager.scala:69:35]
wire [1:0] _io_ptw_gstatus_WIRE_dprv = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_prv = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_sxl = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_uxl = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_xs = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_fs = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_mpp = 2'h0; // @[Manager.scala:70:35]
wire [1:0] _io_ptw_gstatus_WIRE_vs = 2'h0; // @[Manager.scala:70:35]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Manager.scala:38:9]
wire [8:0] _io_ptw_hstatus_WIRE_zero5 = 9'h0; // @[Manager.scala:69:35]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Manager.scala:38:9]
wire [5:0] _io_ptw_hstatus_WIRE_vgein = 6'h0; // @[Manager.scala:69:35]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Manager.scala:38:9]
wire [4:0] _io_ptw_hstatus_WIRE_zero1 = 5'h0; // @[Manager.scala:69:35]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[Manager.scala:38:9]
wire [31:0] _io_ptw_gstatus_WIRE_isa = 32'h0; // @[Manager.scala:70:35]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[Manager.scala:38:9]
wire [22:0] _io_ptw_gstatus_WIRE_zero2 = 23'h0; // @[Manager.scala:70:35]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[Manager.scala:38:9]
wire [7:0] _io_ptw_gstatus_WIRE_zero1 = 8'h0; // @[Manager.scala:70:35]
wire nodeIn_req_ready; // @[MixedNode.scala:551:17]
wire nodeIn_req_valid = auto_in_req_valid_0; // @[Manager.scala:38:9]
wire [2:0] nodeIn_req_bits_opcode = auto_in_req_bits_opcode_0; // @[Manager.scala:38:9]
wire [3:0] nodeIn_req_bits_client_id = auto_in_req_bits_client_id_0; // @[Manager.scala:38:9]
wire nodeIn_req_bits_manager_id = auto_in_req_bits_manager_id_0; // @[Manager.scala:38:9]
wire [63:0] nodeIn_req_bits_data = auto_in_req_bits_data_0; // @[Manager.scala:38:9]
wire nodeIn_resp_ready = auto_in_resp_ready_0; // @[Manager.scala:38:9]
wire nodeIn_resp_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17]
wire nodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_resp_bits_data; // @[MixedNode.scala:551:17]
wire _io_cmd_valid_T; // @[Manager.scala:153:41]
wire _io_ptw_sfence_valid_T; // @[Manager.scala:60:34]
wire auto_in_req_ready_0; // @[Manager.scala:38:9]
wire [2:0] auto_in_resp_bits_opcode_0; // @[Manager.scala:38:9]
wire [3:0] auto_in_resp_bits_client_id_0; // @[Manager.scala:38:9]
wire auto_in_resp_bits_manager_id_0; // @[Manager.scala:38:9]
wire [63:0] auto_in_resp_bits_data_0; // @[Manager.scala:38:9]
wire auto_in_resp_valid_0; // @[Manager.scala:38:9]
wire [6:0] io_cmd_bits_inst_funct_0; // @[Manager.scala:38:9]
wire [4:0] io_cmd_bits_inst_rs2_0; // @[Manager.scala:38:9]
wire [4:0] io_cmd_bits_inst_rs1_0; // @[Manager.scala:38:9]
wire io_cmd_bits_inst_xd_0; // @[Manager.scala:38:9]
wire io_cmd_bits_inst_xs1_0; // @[Manager.scala:38:9]
wire io_cmd_bits_inst_xs2_0; // @[Manager.scala:38:9]
wire [4:0] io_cmd_bits_inst_rd_0; // @[Manager.scala:38:9]
wire [6:0] io_cmd_bits_inst_opcode_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_debug_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_cease_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_wfi_0; // @[Manager.scala:38:9]
wire [31:0] io_cmd_bits_status_isa_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_dprv_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_dv_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_prv_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_v_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_sd_0; // @[Manager.scala:38:9]
wire [22:0] io_cmd_bits_status_zero2_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mpv_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_gva_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mbe_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_sbe_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_sxl_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_uxl_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_sd_rv32_0; // @[Manager.scala:38:9]
wire [7:0] io_cmd_bits_status_zero1_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_tsr_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_tw_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_tvm_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mxr_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_sum_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mprv_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_xs_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_fs_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_mpp_0; // @[Manager.scala:38:9]
wire [1:0] io_cmd_bits_status_vs_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_spp_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mpie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_ube_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_spie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_upie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_mie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_hie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_sie_0; // @[Manager.scala:38:9]
wire io_cmd_bits_status_uie_0; // @[Manager.scala:38:9]
wire [63:0] io_cmd_bits_rs1_0; // @[Manager.scala:38:9]
wire [63:0] io_cmd_bits_rs2_0; // @[Manager.scala:38:9]
wire io_cmd_valid_0; // @[Manager.scala:38:9]
wire io_resp_ready_0; // @[Manager.scala:38:9]
wire [3:0] io_ptw_ptbr_mode_0; // @[Manager.scala:38:9]
wire [15:0] io_ptw_ptbr_asid_0; // @[Manager.scala:38:9]
wire [43:0] io_ptw_ptbr_ppn_0; // @[Manager.scala:38:9]
wire io_ptw_sfence_valid_0; // @[Manager.scala:38:9]
wire io_ptw_status_debug_0; // @[Manager.scala:38:9]
wire io_ptw_status_cease_0; // @[Manager.scala:38:9]
wire io_ptw_status_wfi_0; // @[Manager.scala:38:9]
wire [31:0] io_ptw_status_isa_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_dprv_0; // @[Manager.scala:38:9]
wire io_ptw_status_dv_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_prv_0; // @[Manager.scala:38:9]
wire io_ptw_status_v_0; // @[Manager.scala:38:9]
wire io_ptw_status_sd_0; // @[Manager.scala:38:9]
wire [22:0] io_ptw_status_zero2_0; // @[Manager.scala:38:9]
wire io_ptw_status_mpv_0; // @[Manager.scala:38:9]
wire io_ptw_status_gva_0; // @[Manager.scala:38:9]
wire io_ptw_status_mbe_0; // @[Manager.scala:38:9]
wire io_ptw_status_sbe_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_sxl_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_uxl_0; // @[Manager.scala:38:9]
wire io_ptw_status_sd_rv32_0; // @[Manager.scala:38:9]
wire [7:0] io_ptw_status_zero1_0; // @[Manager.scala:38:9]
wire io_ptw_status_tsr_0; // @[Manager.scala:38:9]
wire io_ptw_status_tw_0; // @[Manager.scala:38:9]
wire io_ptw_status_tvm_0; // @[Manager.scala:38:9]
wire io_ptw_status_mxr_0; // @[Manager.scala:38:9]
wire io_ptw_status_sum_0; // @[Manager.scala:38:9]
wire io_ptw_status_mprv_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_xs_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_fs_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_mpp_0; // @[Manager.scala:38:9]
wire [1:0] io_ptw_status_vs_0; // @[Manager.scala:38:9]
wire io_ptw_status_spp_0; // @[Manager.scala:38:9]
wire io_ptw_status_mpie_0; // @[Manager.scala:38:9]
wire io_ptw_status_ube_0; // @[Manager.scala:38:9]
wire io_ptw_status_spie_0; // @[Manager.scala:38:9]
wire io_ptw_status_upie_0; // @[Manager.scala:38:9]
wire io_ptw_status_mie_0; // @[Manager.scala:38:9]
wire io_ptw_status_hie_0; // @[Manager.scala:38:9]
wire io_ptw_status_sie_0; // @[Manager.scala:38:9]
wire io_ptw_status_uie_0; // @[Manager.scala:38:9]
assign auto_in_req_ready_0 = nodeIn_req_ready; // @[Manager.scala:38:9]
assign auto_in_resp_valid_0 = nodeIn_resp_valid; // @[Manager.scala:38:9]
assign auto_in_resp_bits_opcode_0 = nodeIn_resp_bits_opcode; // @[Manager.scala:38:9]
assign auto_in_resp_bits_client_id_0 = nodeIn_resp_bits_client_id; // @[Manager.scala:38:9]
assign auto_in_resp_bits_manager_id_0 = nodeIn_resp_bits_manager_id; // @[Manager.scala:38:9]
assign auto_in_resp_bits_data_0 = nodeIn_resp_bits_data; // @[Manager.scala:38:9]
reg [3:0] client; // @[Manager.scala:52:21]
reg status_debug; // @[Manager.scala:53:21]
assign io_ptw_status_debug_0 = status_debug; // @[Manager.scala:38:9, :53:21]
reg status_cease; // @[Manager.scala:53:21]
assign io_ptw_status_cease_0 = status_cease; // @[Manager.scala:38:9, :53:21]
reg status_wfi; // @[Manager.scala:53:21]
assign io_ptw_status_wfi_0 = status_wfi; // @[Manager.scala:38:9, :53:21]
reg [31:0] status_isa; // @[Manager.scala:53:21]
assign io_ptw_status_isa_0 = status_isa; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_dprv; // @[Manager.scala:53:21]
assign io_ptw_status_dprv_0 = status_dprv; // @[Manager.scala:38:9, :53:21]
reg status_dv; // @[Manager.scala:53:21]
assign io_ptw_status_dv_0 = status_dv; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_prv; // @[Manager.scala:53:21]
assign io_ptw_status_prv_0 = status_prv; // @[Manager.scala:38:9, :53:21]
reg status_v; // @[Manager.scala:53:21]
assign io_ptw_status_v_0 = status_v; // @[Manager.scala:38:9, :53:21]
reg status_sd; // @[Manager.scala:53:21]
assign io_ptw_status_sd_0 = status_sd; // @[Manager.scala:38:9, :53:21]
reg [22:0] status_zero2; // @[Manager.scala:53:21]
assign io_ptw_status_zero2_0 = status_zero2; // @[Manager.scala:38:9, :53:21]
reg status_mpv; // @[Manager.scala:53:21]
assign io_ptw_status_mpv_0 = status_mpv; // @[Manager.scala:38:9, :53:21]
reg status_gva; // @[Manager.scala:53:21]
assign io_ptw_status_gva_0 = status_gva; // @[Manager.scala:38:9, :53:21]
reg status_mbe; // @[Manager.scala:53:21]
assign io_ptw_status_mbe_0 = status_mbe; // @[Manager.scala:38:9, :53:21]
reg status_sbe; // @[Manager.scala:53:21]
assign io_ptw_status_sbe_0 = status_sbe; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_sxl; // @[Manager.scala:53:21]
assign io_ptw_status_sxl_0 = status_sxl; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_uxl; // @[Manager.scala:53:21]
assign io_ptw_status_uxl_0 = status_uxl; // @[Manager.scala:38:9, :53:21]
reg status_sd_rv32; // @[Manager.scala:53:21]
assign io_ptw_status_sd_rv32_0 = status_sd_rv32; // @[Manager.scala:38:9, :53:21]
reg [7:0] status_zero1; // @[Manager.scala:53:21]
assign io_ptw_status_zero1_0 = status_zero1; // @[Manager.scala:38:9, :53:21]
reg status_tsr; // @[Manager.scala:53:21]
assign io_ptw_status_tsr_0 = status_tsr; // @[Manager.scala:38:9, :53:21]
reg status_tw; // @[Manager.scala:53:21]
assign io_ptw_status_tw_0 = status_tw; // @[Manager.scala:38:9, :53:21]
reg status_tvm; // @[Manager.scala:53:21]
assign io_ptw_status_tvm_0 = status_tvm; // @[Manager.scala:38:9, :53:21]
reg status_mxr; // @[Manager.scala:53:21]
assign io_ptw_status_mxr_0 = status_mxr; // @[Manager.scala:38:9, :53:21]
reg status_sum; // @[Manager.scala:53:21]
assign io_ptw_status_sum_0 = status_sum; // @[Manager.scala:38:9, :53:21]
reg status_mprv; // @[Manager.scala:53:21]
assign io_ptw_status_mprv_0 = status_mprv; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_xs; // @[Manager.scala:53:21]
assign io_ptw_status_xs_0 = status_xs; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_fs; // @[Manager.scala:53:21]
assign io_ptw_status_fs_0 = status_fs; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_mpp; // @[Manager.scala:53:21]
assign io_ptw_status_mpp_0 = status_mpp; // @[Manager.scala:38:9, :53:21]
reg [1:0] status_vs; // @[Manager.scala:53:21]
assign io_ptw_status_vs_0 = status_vs; // @[Manager.scala:38:9, :53:21]
reg status_spp; // @[Manager.scala:53:21]
assign io_ptw_status_spp_0 = status_spp; // @[Manager.scala:38:9, :53:21]
reg status_mpie; // @[Manager.scala:53:21]
assign io_ptw_status_mpie_0 = status_mpie; // @[Manager.scala:38:9, :53:21]
reg status_ube; // @[Manager.scala:53:21]
assign io_ptw_status_ube_0 = status_ube; // @[Manager.scala:38:9, :53:21]
reg status_spie; // @[Manager.scala:53:21]
assign io_ptw_status_spie_0 = status_spie; // @[Manager.scala:38:9, :53:21]
reg status_upie; // @[Manager.scala:53:21]
assign io_ptw_status_upie_0 = status_upie; // @[Manager.scala:38:9, :53:21]
reg status_mie; // @[Manager.scala:53:21]
assign io_ptw_status_mie_0 = status_mie; // @[Manager.scala:38:9, :53:21]
reg status_hie; // @[Manager.scala:53:21]
assign io_ptw_status_hie_0 = status_hie; // @[Manager.scala:38:9, :53:21]
reg status_sie; // @[Manager.scala:53:21]
assign io_ptw_status_sie_0 = status_sie; // @[Manager.scala:38:9, :53:21]
reg status_uie; // @[Manager.scala:53:21]
assign io_ptw_status_uie_0 = status_uie; // @[Manager.scala:38:9, :53:21]
reg [3:0] ptbr_mode; // @[Manager.scala:54:19]
assign io_ptw_ptbr_mode_0 = ptbr_mode; // @[Manager.scala:38:9, :54:19]
reg [15:0] ptbr_asid; // @[Manager.scala:54:19]
assign io_ptw_ptbr_asid_0 = ptbr_asid; // @[Manager.scala:38:9, :54:19]
reg [43:0] ptbr_ppn; // @[Manager.scala:54:19]
assign io_ptw_ptbr_ppn_0 = ptbr_ppn; // @[Manager.scala:38:9, :54:19]
reg [2:0] state; // @[Manager.scala:55:24]
assign _io_ptw_sfence_valid_T = state == 3'h3; // @[Manager.scala:55:24, :60:34]
assign io_ptw_sfence_valid_0 = _io_ptw_sfence_valid_T; // @[Manager.scala:38:9, :60:34]
reg [1:0] req_beat; // @[Protocol.scala:54:23]
reg [1:0] max_beat; // @[Protocol.scala:55:27]
wire req_first = req_beat == 2'h0; // @[Protocol.scala:54:23, :56:22]
wire req_last; // @[Protocol.scala:57:20]
wire [6:0] _inst_T_7; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_6; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_5; // @[Protocol.scala:58:36]
wire _inst_T_4; // @[Protocol.scala:58:36]
wire _inst_T_3; // @[Protocol.scala:58:36]
wire _inst_T_2; // @[Protocol.scala:58:36]
wire [4:0] _inst_T_1; // @[Protocol.scala:58:36]
wire [6:0] _inst_T; // @[Protocol.scala:58:36]
wire [6:0] inst_funct; // @[Protocol.scala:58:36]
wire [4:0] inst_rs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rs1; // @[Protocol.scala:58:36]
wire inst_xd; // @[Protocol.scala:58:36]
wire inst_xs1; // @[Protocol.scala:58:36]
wire inst_xs2; // @[Protocol.scala:58:36]
wire [4:0] inst_rd; // @[Protocol.scala:58:36]
wire [6:0] inst_opcode; // @[Protocol.scala:58:36]
wire [31:0] _inst_WIRE = _rr_req_q_io_deq_bits_data[31:0]; // @[Decoupled.scala:362:21]
wire [31:0] _inst_WIRE_1 = _rr_req_q_io_deq_bits_data[31:0]; // @[Decoupled.scala:362:21]
assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36]
assign inst_opcode = _inst_T; // @[Protocol.scala:58:36]
assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36]
assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36]
assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36]
assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36]
assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36]
assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36]
assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36]
assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36]
assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36]
assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36]
assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36]
assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36]
assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36]
assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36]
wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32]
wire _T_13 = _rr_req_q_io_deq_bits_opcode == 3'h2; // @[Decoupled.scala:362:21]
wire _GEN = req_beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22]
wire _last_T; // @[Protocol.scala:77:22]
assign _last_T = _GEN; // @[Protocol.scala:77:22]
wire _last_T_6; // @[Protocol.scala:79:57]
assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57]
wire _last_T_1 = ~req_first; // @[Protocol.scala:56:22, :77:38]
wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}]
wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28]
wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41]
wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}]
wire _last_T_7 = req_first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}]
wire _GEN_0 = _rr_req_q_io_deq_bits_opcode != 3'h1; // @[Decoupled.scala:362:21]
assign req_last = _T_13 ? _last_T_2 : _GEN_0 | _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}]
wire [2:0] _beat_T = {1'h0, req_beat} + 3'h1; // @[Protocol.scala:54:23, :87:34]
wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34]
reg [6:0] enq_inst_inst_funct; // @[Manager.scala:80:23]
wire [6:0] next_enq_inst_inst_funct = enq_inst_inst_funct; // @[Manager.scala:80:23, :81:33]
reg [4:0] enq_inst_inst_rs2; // @[Manager.scala:80:23]
wire [4:0] next_enq_inst_inst_rs2 = enq_inst_inst_rs2; // @[Manager.scala:80:23, :81:33]
reg [4:0] enq_inst_inst_rs1; // @[Manager.scala:80:23]
wire [4:0] next_enq_inst_inst_rs1 = enq_inst_inst_rs1; // @[Manager.scala:80:23, :81:33]
reg enq_inst_inst_xd; // @[Manager.scala:80:23]
wire next_enq_inst_inst_xd = enq_inst_inst_xd; // @[Manager.scala:80:23, :81:33]
reg enq_inst_inst_xs1; // @[Manager.scala:80:23]
wire next_enq_inst_inst_xs1 = enq_inst_inst_xs1; // @[Manager.scala:80:23, :81:33]
reg enq_inst_inst_xs2; // @[Manager.scala:80:23]
wire next_enq_inst_inst_xs2 = enq_inst_inst_xs2; // @[Manager.scala:80:23, :81:33]
reg [4:0] enq_inst_inst_rd; // @[Manager.scala:80:23]
wire [4:0] next_enq_inst_inst_rd = enq_inst_inst_rd; // @[Manager.scala:80:23, :81:33]
reg [6:0] enq_inst_inst_opcode; // @[Manager.scala:80:23]
wire [6:0] next_enq_inst_inst_opcode = enq_inst_inst_opcode; // @[Manager.scala:80:23, :81:33]
reg [63:0] enq_inst_rs1; // @[Manager.scala:80:23]
reg [63:0] enq_inst_rs2; // @[Manager.scala:80:23]
reg enq_inst_status_debug; // @[Manager.scala:80:23]
wire next_enq_inst_status_debug = enq_inst_status_debug; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_cease; // @[Manager.scala:80:23]
wire next_enq_inst_status_cease = enq_inst_status_cease; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_wfi; // @[Manager.scala:80:23]
wire next_enq_inst_status_wfi = enq_inst_status_wfi; // @[Manager.scala:80:23, :81:33]
reg [31:0] enq_inst_status_isa; // @[Manager.scala:80:23]
wire [31:0] next_enq_inst_status_isa = enq_inst_status_isa; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_dprv; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_dprv = enq_inst_status_dprv; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_dv; // @[Manager.scala:80:23]
wire next_enq_inst_status_dv = enq_inst_status_dv; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_prv; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_prv = enq_inst_status_prv; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_v; // @[Manager.scala:80:23]
wire next_enq_inst_status_v = enq_inst_status_v; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_sd; // @[Manager.scala:80:23]
wire next_enq_inst_status_sd = enq_inst_status_sd; // @[Manager.scala:80:23, :81:33]
reg [22:0] enq_inst_status_zero2; // @[Manager.scala:80:23]
wire [22:0] next_enq_inst_status_zero2 = enq_inst_status_zero2; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mpv; // @[Manager.scala:80:23]
wire next_enq_inst_status_mpv = enq_inst_status_mpv; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_gva; // @[Manager.scala:80:23]
wire next_enq_inst_status_gva = enq_inst_status_gva; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mbe; // @[Manager.scala:80:23]
wire next_enq_inst_status_mbe = enq_inst_status_mbe; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_sbe; // @[Manager.scala:80:23]
wire next_enq_inst_status_sbe = enq_inst_status_sbe; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_sxl; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_sxl = enq_inst_status_sxl; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_uxl; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_uxl = enq_inst_status_uxl; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_sd_rv32; // @[Manager.scala:80:23]
wire next_enq_inst_status_sd_rv32 = enq_inst_status_sd_rv32; // @[Manager.scala:80:23, :81:33]
reg [7:0] enq_inst_status_zero1; // @[Manager.scala:80:23]
wire [7:0] next_enq_inst_status_zero1 = enq_inst_status_zero1; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_tsr; // @[Manager.scala:80:23]
wire next_enq_inst_status_tsr = enq_inst_status_tsr; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_tw; // @[Manager.scala:80:23]
wire next_enq_inst_status_tw = enq_inst_status_tw; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_tvm; // @[Manager.scala:80:23]
wire next_enq_inst_status_tvm = enq_inst_status_tvm; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mxr; // @[Manager.scala:80:23]
wire next_enq_inst_status_mxr = enq_inst_status_mxr; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_sum; // @[Manager.scala:80:23]
wire next_enq_inst_status_sum = enq_inst_status_sum; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mprv; // @[Manager.scala:80:23]
wire next_enq_inst_status_mprv = enq_inst_status_mprv; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_xs; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_xs = enq_inst_status_xs; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_fs; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_fs = enq_inst_status_fs; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_mpp; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_mpp = enq_inst_status_mpp; // @[Manager.scala:80:23, :81:33]
reg [1:0] enq_inst_status_vs; // @[Manager.scala:80:23]
wire [1:0] next_enq_inst_status_vs = enq_inst_status_vs; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_spp; // @[Manager.scala:80:23]
wire next_enq_inst_status_spp = enq_inst_status_spp; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mpie; // @[Manager.scala:80:23]
wire next_enq_inst_status_mpie = enq_inst_status_mpie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_ube; // @[Manager.scala:80:23]
wire next_enq_inst_status_ube = enq_inst_status_ube; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_spie; // @[Manager.scala:80:23]
wire next_enq_inst_status_spie = enq_inst_status_spie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_upie; // @[Manager.scala:80:23]
wire next_enq_inst_status_upie = enq_inst_status_upie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_mie; // @[Manager.scala:80:23]
wire next_enq_inst_status_mie = enq_inst_status_mie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_hie; // @[Manager.scala:80:23]
wire next_enq_inst_status_hie = enq_inst_status_hie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_sie; // @[Manager.scala:80:23]
wire next_enq_inst_status_sie = enq_inst_status_sie; // @[Manager.scala:80:23, :81:33]
reg enq_inst_status_uie; // @[Manager.scala:80:23]
wire next_enq_inst_status_uie = enq_inst_status_uie; // @[Manager.scala:80:23, :81:33]
wire [63:0] next_enq_inst_rs1; // @[Manager.scala:81:33]
wire [63:0] next_enq_inst_rs2; // @[Manager.scala:81:33]
reg [63:0] status_lower; // @[Manager.scala:95:27]
wire _q_io_deq_ready_T = ~_inst_q_io_deq_valid; // @[Manager.scala:79:24, :106:25]
wire _q_io_deq_ready_T_1 = ~io_busy_0; // @[Manager.scala:38:9, :106:49]
wire _q_io_deq_ready_T_2 = _q_io_deq_ready_T & _q_io_deq_ready_T_1; // @[Manager.scala:106:{25,46,49}]
wire [127:0] _status_T = {_rr_req_q_io_deq_bits_data, status_lower}; // @[Decoupled.scala:362:21]
wire _status_T_37; // @[Manager.scala:109:83]
wire _status_T_36; // @[Manager.scala:109:83]
wire _status_T_35; // @[Manager.scala:109:83]
wire [31:0] _status_T_34; // @[Manager.scala:109:83]
wire [1:0] _status_T_33; // @[Manager.scala:109:83]
wire _status_T_32; // @[Manager.scala:109:83]
wire [1:0] _status_T_31; // @[Manager.scala:109:83]
wire _status_T_30; // @[Manager.scala:109:83]
wire _status_T_29; // @[Manager.scala:109:83]
wire [22:0] _status_T_28; // @[Manager.scala:109:83]
wire _status_T_27; // @[Manager.scala:109:83]
wire _status_T_26; // @[Manager.scala:109:83]
wire _status_T_25; // @[Manager.scala:109:83]
wire _status_T_24; // @[Manager.scala:109:83]
wire [1:0] _status_T_23; // @[Manager.scala:109:83]
wire [1:0] _status_T_22; // @[Manager.scala:109:83]
wire _status_T_21; // @[Manager.scala:109:83]
wire [7:0] _status_T_20; // @[Manager.scala:109:83]
wire _status_T_19; // @[Manager.scala:109:83]
wire _status_T_18; // @[Manager.scala:109:83]
wire _status_T_17; // @[Manager.scala:109:83]
wire _status_T_16; // @[Manager.scala:109:83]
wire _status_T_15; // @[Manager.scala:109:83]
wire _status_T_14; // @[Manager.scala:109:83]
wire [1:0] _status_T_13; // @[Manager.scala:109:83]
wire [1:0] _status_T_12; // @[Manager.scala:109:83]
wire [1:0] _status_T_11; // @[Manager.scala:109:83]
wire [1:0] _status_T_10; // @[Manager.scala:109:83]
wire _status_T_9; // @[Manager.scala:109:83]
wire _status_T_8; // @[Manager.scala:109:83]
wire _status_T_7; // @[Manager.scala:109:83]
wire _status_T_6; // @[Manager.scala:109:83]
wire _status_T_5; // @[Manager.scala:109:83]
wire _status_T_4; // @[Manager.scala:109:83]
wire _status_T_3; // @[Manager.scala:109:83]
wire _status_T_2; // @[Manager.scala:109:83]
wire _status_T_1; // @[Manager.scala:109:83]
wire [104:0] _status_WIRE_1 = _status_T[104:0]; // @[Manager.scala:109:{42,83}]
assign _status_T_1 = _status_WIRE_1[0]; // @[Manager.scala:109:83]
wire _status_WIRE_uie = _status_T_1; // @[Manager.scala:109:83]
assign _status_T_2 = _status_WIRE_1[1]; // @[Manager.scala:109:83]
wire _status_WIRE_sie = _status_T_2; // @[Manager.scala:109:83]
assign _status_T_3 = _status_WIRE_1[2]; // @[Manager.scala:109:83]
wire _status_WIRE_hie = _status_T_3; // @[Manager.scala:109:83]
assign _status_T_4 = _status_WIRE_1[3]; // @[Manager.scala:109:83]
wire _status_WIRE_mie = _status_T_4; // @[Manager.scala:109:83]
assign _status_T_5 = _status_WIRE_1[4]; // @[Manager.scala:109:83]
wire _status_WIRE_upie = _status_T_5; // @[Manager.scala:109:83]
assign _status_T_6 = _status_WIRE_1[5]; // @[Manager.scala:109:83]
wire _status_WIRE_spie = _status_T_6; // @[Manager.scala:109:83]
assign _status_T_7 = _status_WIRE_1[6]; // @[Manager.scala:109:83]
wire _status_WIRE_ube = _status_T_7; // @[Manager.scala:109:83]
assign _status_T_8 = _status_WIRE_1[7]; // @[Manager.scala:109:83]
wire _status_WIRE_mpie = _status_T_8; // @[Manager.scala:109:83]
assign _status_T_9 = _status_WIRE_1[8]; // @[Manager.scala:109:83]
wire _status_WIRE_spp = _status_T_9; // @[Manager.scala:109:83]
assign _status_T_10 = _status_WIRE_1[10:9]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_vs = _status_T_10; // @[Manager.scala:109:83]
assign _status_T_11 = _status_WIRE_1[12:11]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_mpp = _status_T_11; // @[Manager.scala:109:83]
assign _status_T_12 = _status_WIRE_1[14:13]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_fs = _status_T_12; // @[Manager.scala:109:83]
assign _status_T_13 = _status_WIRE_1[16:15]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_xs = _status_T_13; // @[Manager.scala:109:83]
assign _status_T_14 = _status_WIRE_1[17]; // @[Manager.scala:109:83]
wire _status_WIRE_mprv = _status_T_14; // @[Manager.scala:109:83]
assign _status_T_15 = _status_WIRE_1[18]; // @[Manager.scala:109:83]
wire _status_WIRE_sum = _status_T_15; // @[Manager.scala:109:83]
assign _status_T_16 = _status_WIRE_1[19]; // @[Manager.scala:109:83]
wire _status_WIRE_mxr = _status_T_16; // @[Manager.scala:109:83]
assign _status_T_17 = _status_WIRE_1[20]; // @[Manager.scala:109:83]
wire _status_WIRE_tvm = _status_T_17; // @[Manager.scala:109:83]
assign _status_T_18 = _status_WIRE_1[21]; // @[Manager.scala:109:83]
wire _status_WIRE_tw = _status_T_18; // @[Manager.scala:109:83]
assign _status_T_19 = _status_WIRE_1[22]; // @[Manager.scala:109:83]
wire _status_WIRE_tsr = _status_T_19; // @[Manager.scala:109:83]
assign _status_T_20 = _status_WIRE_1[30:23]; // @[Manager.scala:109:83]
wire [7:0] _status_WIRE_zero1 = _status_T_20; // @[Manager.scala:109:83]
assign _status_T_21 = _status_WIRE_1[31]; // @[Manager.scala:109:83]
wire _status_WIRE_sd_rv32 = _status_T_21; // @[Manager.scala:109:83]
assign _status_T_22 = _status_WIRE_1[33:32]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_uxl = _status_T_22; // @[Manager.scala:109:83]
assign _status_T_23 = _status_WIRE_1[35:34]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_sxl = _status_T_23; // @[Manager.scala:109:83]
assign _status_T_24 = _status_WIRE_1[36]; // @[Manager.scala:109:83]
wire _status_WIRE_sbe = _status_T_24; // @[Manager.scala:109:83]
assign _status_T_25 = _status_WIRE_1[37]; // @[Manager.scala:109:83]
wire _status_WIRE_mbe = _status_T_25; // @[Manager.scala:109:83]
assign _status_T_26 = _status_WIRE_1[38]; // @[Manager.scala:109:83]
wire _status_WIRE_gva = _status_T_26; // @[Manager.scala:109:83]
assign _status_T_27 = _status_WIRE_1[39]; // @[Manager.scala:109:83]
wire _status_WIRE_mpv = _status_T_27; // @[Manager.scala:109:83]
assign _status_T_28 = _status_WIRE_1[62:40]; // @[Manager.scala:109:83]
wire [22:0] _status_WIRE_zero2 = _status_T_28; // @[Manager.scala:109:83]
assign _status_T_29 = _status_WIRE_1[63]; // @[Manager.scala:109:83]
wire _status_WIRE_sd = _status_T_29; // @[Manager.scala:109:83]
assign _status_T_30 = _status_WIRE_1[64]; // @[Manager.scala:109:83]
wire _status_WIRE_v = _status_T_30; // @[Manager.scala:109:83]
assign _status_T_31 = _status_WIRE_1[66:65]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_prv = _status_T_31; // @[Manager.scala:109:83]
assign _status_T_32 = _status_WIRE_1[67]; // @[Manager.scala:109:83]
wire _status_WIRE_dv = _status_T_32; // @[Manager.scala:109:83]
assign _status_T_33 = _status_WIRE_1[69:68]; // @[Manager.scala:109:83]
wire [1:0] _status_WIRE_dprv = _status_T_33; // @[Manager.scala:109:83]
assign _status_T_34 = _status_WIRE_1[101:70]; // @[Manager.scala:109:83]
wire [31:0] _status_WIRE_isa = _status_T_34; // @[Manager.scala:109:83]
assign _status_T_35 = _status_WIRE_1[102]; // @[Manager.scala:109:83]
wire _status_WIRE_wfi = _status_T_35; // @[Manager.scala:109:83]
assign _status_T_36 = _status_WIRE_1[103]; // @[Manager.scala:109:83]
wire _status_WIRE_cease = _status_T_36; // @[Manager.scala:109:83]
assign _status_T_37 = _status_WIRE_1[104]; // @[Manager.scala:109:83]
wire _status_WIRE_debug = _status_T_37; // @[Manager.scala:109:83]
wire _T_17 = _rr_req_q_io_deq_bits_opcode == 3'h3; // @[Decoupled.scala:362:21]
wire _q_io_deq_ready_T_3 = ~_inst_q_io_deq_valid; // @[Manager.scala:79:24, :112:25]
wire _q_io_deq_ready_T_4 = ~io_busy_0; // @[Manager.scala:38:9, :112:49]
wire _q_io_deq_ready_T_5 = _q_io_deq_ready_T_3 & _q_io_deq_ready_T_4; // @[Manager.scala:112:{25,46,49}]
wire [3:0] _ptbr_T_2; // @[Manager.scala:113:84]
wire [15:0] _ptbr_T_1; // @[Manager.scala:113:84]
wire [43:0] _ptbr_T; // @[Manager.scala:113:84]
wire [63:0] _ptbr_WIRE_1; // @[Manager.scala:113:84]
assign _ptbr_T = _ptbr_WIRE_1[43:0]; // @[Manager.scala:113:84]
wire [43:0] _ptbr_WIRE_ppn = _ptbr_T; // @[Manager.scala:113:84]
assign _ptbr_T_1 = _ptbr_WIRE_1[59:44]; // @[Manager.scala:113:84]
wire [15:0] _ptbr_WIRE_asid = _ptbr_T_1; // @[Manager.scala:113:84]
assign _ptbr_T_2 = _ptbr_WIRE_1[63:60]; // @[Manager.scala:113:84]
wire [3:0] _ptbr_WIRE_mode = _ptbr_T_2; // @[Manager.scala:113:84]
wire _T_21 = _rr_req_q_io_deq_bits_opcode == 3'h1; // @[Decoupled.scala:362:21]
wire [6:0] _inst_T_15; // @[Manager.scala:119:47]
wire [4:0] _inst_T_14; // @[Manager.scala:119:47]
wire [4:0] _inst_T_13; // @[Manager.scala:119:47]
wire _inst_T_12; // @[Manager.scala:119:47]
wire _inst_T_11; // @[Manager.scala:119:47]
wire _inst_T_10; // @[Manager.scala:119:47]
wire [4:0] _inst_T_9; // @[Manager.scala:119:47]
wire [6:0] _inst_T_8; // @[Manager.scala:119:47]
wire [6:0] inst_1_funct; // @[Manager.scala:119:47]
wire [4:0] inst_1_rs2; // @[Manager.scala:119:47]
wire [4:0] inst_1_rs1; // @[Manager.scala:119:47]
wire inst_1_xd; // @[Manager.scala:119:47]
wire inst_1_xs1; // @[Manager.scala:119:47]
wire inst_1_xs2; // @[Manager.scala:119:47]
wire [4:0] inst_1_rd; // @[Manager.scala:119:47]
wire [6:0] inst_1_opcode; // @[Manager.scala:119:47]
assign _inst_T_8 = _inst_WIRE_1[6:0]; // @[Manager.scala:119:47]
assign inst_1_opcode = _inst_T_8; // @[Manager.scala:119:47]
assign _inst_T_9 = _inst_WIRE_1[11:7]; // @[Manager.scala:119:47]
assign inst_1_rd = _inst_T_9; // @[Manager.scala:119:47]
assign _inst_T_10 = _inst_WIRE_1[12]; // @[Manager.scala:119:47]
assign inst_1_xs2 = _inst_T_10; // @[Manager.scala:119:47]
assign _inst_T_11 = _inst_WIRE_1[13]; // @[Manager.scala:119:47]
assign inst_1_xs1 = _inst_T_11; // @[Manager.scala:119:47]
assign _inst_T_12 = _inst_WIRE_1[14]; // @[Manager.scala:119:47]
assign inst_1_xd = _inst_T_12; // @[Manager.scala:119:47]
assign _inst_T_13 = _inst_WIRE_1[19:15]; // @[Manager.scala:119:47]
assign inst_1_rs1 = _inst_T_13; // @[Manager.scala:119:47]
assign _inst_T_14 = _inst_WIRE_1[24:20]; // @[Manager.scala:119:47]
assign inst_1_rs2 = _inst_T_14; // @[Manager.scala:119:47]
assign _inst_T_15 = _inst_WIRE_1[31:25]; // @[Manager.scala:119:47]
assign inst_1_funct = _inst_T_15; // @[Manager.scala:119:47]
wire _enq_inst_rs1_T = req_beat == 2'h1; // @[Manager.scala:124:65]
wire enq_inst_rs1_0 = enq_inst_inst_xs1 & _enq_inst_rs1_T; // @[Manager.scala:80:23, :124:{53,65}]
wire [1:0] _enq_inst_rs2_T = enq_inst_inst_xs1 ? 2'h2 : 2'h1; // @[Manager.scala:80:23, :125:72]
wire _enq_inst_rs2_T_1 = req_beat == _enq_inst_rs2_T; // @[Manager.scala:125:{65,72}]
wire enq_inst_rs2_0 = enq_inst_inst_xs2 & _enq_inst_rs2_T_1; // @[Manager.scala:80:23, :125:{53,65}]
wire _GEN_1 = ~(|_rr_req_q_io_deq_bits_opcode) | _T_13 | _T_17; // @[Decoupled.scala:362:21]
assign next_enq_inst_rs1 = ~_rr_req_q_io_deq_valid | _GEN_1 | ~_T_21 | req_first | ~enq_inst_rs1_0 ? enq_inst_rs1 : _rr_req_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
assign next_enq_inst_rs2 = ~_rr_req_q_io_deq_valid | _GEN_1 | ~_T_21 | req_first | ~enq_inst_rs2_0 ? enq_inst_rs2 : _rr_req_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _T_33 = _rr_req_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21]
wire _T_34 = _rr_req_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21]
wire rr_req_q_io_deq_ready = _rr_req_q_io_deq_valid & ((|_rr_req_q_io_deq_bits_opcode) ? (_T_13 ? _q_io_deq_ready_T_2 : _T_17 ? _q_io_deq_ready_T_5 : _T_21 | _T_33 | _T_34) : _resp_arb_io_in_0_ready); // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File ScratchpadSlavePort.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{SimpleDevice}
import freechips.rocketchip.tilelink.{TLManagerNode, TLSlavePortParameters, TLSlaveParameters, TLBundleA, TLMessages, TLAtomics}
import freechips.rocketchip.util.UIntIsOneOf
import freechips.rocketchip.util.DataToAugmentedData
/* This adapter converts between diplomatic TileLink and non-diplomatic HellaCacheIO */
class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule {
def this(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) = {
this(Seq(address), coreDataBytes, usingAtomics)
}
val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = device.reg("mem"),
regionType = RegionType.IDEMPOTENT,
executable = true,
supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
supportsLogical = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
supportsPutPartial = TransferSizes(1, coreDataBytes),
supportsPutFull = TransferSizes(1, coreDataBytes),
supportsGet = TransferSizes(1, coreDataBytes),
fifoId = Some(0))), // requests handled in FIFO order
beatBytes = coreDataBytes,
minLatency = 1)))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val dmem = new HellaCacheIO
})
require(coreDataBytes * 8 == io.dmem.resp.bits.data.getWidth, "ScratchpadSlavePort is misconfigured: coreDataBytes must match D$ data width")
val (tl_in, edge) = node.in(0)
val s_ready :: s_wait1 :: s_wait2 :: s_replay :: s_init :: s_grant :: Nil = Enum(6)
val state = RegInit(s_init)
val dmem_req_valid = Wire(Bool())
when (state === s_wait1) { state := s_wait2 }
when (state === s_init && tl_in.a.valid) { state := s_ready }
when (io.dmem.resp.valid) { state := s_grant }
when (tl_in.d.fire) { state := s_ready }
when (io.dmem.s2_nack) { state := s_replay }
when (dmem_req_valid && io.dmem.req.ready) { state := s_wait1 }
val acq = Reg(tl_in.a.bits.cloneType)
when (tl_in.a.fire) { acq := tl_in.a.bits }
def formCacheReq(a: TLBundleA) = {
val req = Wire(new HellaCacheReq)
req.cmd := MuxLookup(a.opcode, M_XRD)(Array(
TLMessages.PutFullData -> M_XWR,
TLMessages.PutPartialData -> M_PWR,
TLMessages.ArithmeticData -> MuxLookup(a.param, M_XRD)(Array(
TLAtomics.MIN -> M_XA_MIN,
TLAtomics.MAX -> M_XA_MAX,
TLAtomics.MINU -> M_XA_MINU,
TLAtomics.MAXU -> M_XA_MAXU,
TLAtomics.ADD -> M_XA_ADD)),
TLMessages.LogicalData -> MuxLookup(a.param, M_XRD)(Array(
TLAtomics.XOR -> M_XA_XOR,
TLAtomics.OR -> M_XA_OR,
TLAtomics.AND -> M_XA_AND,
TLAtomics.SWAP -> M_XA_SWAP)),
TLMessages.Get -> M_XRD))
// Convert full PutPartial into PutFull to work around RMWs causing X-prop problems.
// Also prevent cmd becoming X out of reset by checking for s_init.
val mask_full = {
val desired_mask = new StoreGen(a.size, a.address, 0.U, coreDataBytes).mask
(a.mask | ~desired_mask).andR
}
when (state === s_init || (a.opcode === TLMessages.PutPartialData && mask_full)) {
req.cmd := M_XWR
}
req.size := a.size
req.signed := false.B
req.addr := a.address
req.tag := 0.U
req.phys := true.B
req.no_xcpt := true.B
req.no_resp := false.B
req.data := 0.U
req.no_alloc := false.B
req.mask := 0.U
req.dprv := 0.U
req.dv := false.B
req
}
// ready_likely assumes that a valid response in s_wait2 is the vastly
// common case. In the uncommon case, we'll erroneously send a request,
// then s1_kill it the following cycle.
val ready_likely = state.isOneOf(s_ready, s_wait2)
val ready = state === s_ready || state === s_wait2 && io.dmem.resp.valid && tl_in.d.ready
dmem_req_valid := (tl_in.a.valid && ready) || state === s_replay
val dmem_req_valid_likely = (tl_in.a.valid && ready_likely) || state === s_replay
io.dmem.keep_clock_enabled := DontCare
io.dmem.req.valid := dmem_req_valid_likely
tl_in.a.ready := io.dmem.req.ready && ready
io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))
io.dmem.s1_data.data := acq.data
io.dmem.s1_data.mask := acq.mask
io.dmem.s1_kill := state =/= s_wait1
io.dmem.s2_kill := false.B
tl_in.d.valid := io.dmem.resp.valid || state === s_grant
tl_in.d.bits := Mux(acq.opcode.isOneOf(TLMessages.PutFullData, TLMessages.PutPartialData),
edge.AccessAck(acq),
edge.AccessAck(acq, 0.U))
tl_in.d.bits.data := io.dmem.resp.bits.data_raw.holdUnless(state === s_wait2)
// Tie off unused channels
tl_in.b.valid := false.B
tl_in.c.ready := true.B
tl_in.e.ready := true.B
}
}
| module ScratchpadSlavePort( // @[ScratchpadSlavePort.scala:43:9]
input clock, // @[ScratchpadSlavePort.scala:43:9]
input reset, // @[ScratchpadSlavePort.scala:43:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_dmem_req_ready, // @[ScratchpadSlavePort.scala:44:16]
output io_dmem_req_valid, // @[ScratchpadSlavePort.scala:44:16]
output [33:0] io_dmem_req_bits_addr, // @[ScratchpadSlavePort.scala:44:16]
output [4:0] io_dmem_req_bits_cmd, // @[ScratchpadSlavePort.scala:44:16]
output [1:0] io_dmem_req_bits_size, // @[ScratchpadSlavePort.scala:44:16]
output io_dmem_s1_kill, // @[ScratchpadSlavePort.scala:44:16]
output [63:0] io_dmem_s1_data_data, // @[ScratchpadSlavePort.scala:44:16]
output [7:0] io_dmem_s1_data_mask, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_nack, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_nack_cause_raw, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_uncached, // @[ScratchpadSlavePort.scala:44:16]
input [31:0] io_dmem_s2_paddr, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_resp_valid, // @[ScratchpadSlavePort.scala:44:16]
input [33:0] io_dmem_resp_bits_addr, // @[ScratchpadSlavePort.scala:44:16]
input [6:0] io_dmem_resp_bits_tag, // @[ScratchpadSlavePort.scala:44:16]
input [4:0] io_dmem_resp_bits_cmd, // @[ScratchpadSlavePort.scala:44:16]
input [1:0] io_dmem_resp_bits_size, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_resp_bits_signed, // @[ScratchpadSlavePort.scala:44:16]
input [1:0] io_dmem_resp_bits_dprv, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_resp_bits_dv, // @[ScratchpadSlavePort.scala:44:16]
input [63:0] io_dmem_resp_bits_data, // @[ScratchpadSlavePort.scala:44:16]
input [7:0] io_dmem_resp_bits_mask, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_resp_bits_replay, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_resp_bits_has_data, // @[ScratchpadSlavePort.scala:44:16]
input [63:0] io_dmem_resp_bits_data_word_bypass, // @[ScratchpadSlavePort.scala:44:16]
input [63:0] io_dmem_resp_bits_data_raw, // @[ScratchpadSlavePort.scala:44:16]
input [63:0] io_dmem_resp_bits_store_data, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_replay_next, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_ma_ld, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_ma_st, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_pf_ld, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_pf_st, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_ae_ld, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_s2_xcpt_ae_st, // @[ScratchpadSlavePort.scala:44:16]
input [33:0] io_dmem_s2_gpa, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_ordered, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_store_pending, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_acquire, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_grant, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_blocked, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_canAcceptStoreThenLoad, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_canAcceptStoreThenRMW, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_canAcceptLoadThenLoad, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_storeBufferEmptyAfterLoad, // @[ScratchpadSlavePort.scala:44:16]
input io_dmem_perf_storeBufferEmptyAfterStore // @[ScratchpadSlavePort.scala:44:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[ScratchpadSlavePort.scala:43:9]
wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[ScratchpadSlavePort.scala:43:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[ScratchpadSlavePort.scala:43:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[ScratchpadSlavePort.scala:43:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[ScratchpadSlavePort.scala:43:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[ScratchpadSlavePort.scala:43:9]
wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[ScratchpadSlavePort.scala:43:9]
wire [33:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[ScratchpadSlavePort.scala:43:9]
wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[ScratchpadSlavePort.scala:43:9]
wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[ScratchpadSlavePort.scala:43:9]
wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[ScratchpadSlavePort.scala:43:9]
wire [33:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_ordered_0 = io_dmem_ordered; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [2:0] nodeIn_d_bits_d_1_opcode = 3'h1; // @[Edges.scala:810:17]
wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[ScratchpadSlavePort.scala:43:9]
wire [7:0] io_dmem_req_bits_req_mask = 8'h0; // @[ScratchpadSlavePort.scala:66:21]
wire [63:0] io_dmem_req_bits_data = 64'h0; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_req_bits_req_data = 64'h0; // @[ScratchpadSlavePort.scala:66:21]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [63:0] nodeIn_d_bits_d_1_data = 64'h0; // @[Edges.scala:810:17]
wire [63:0] _nodeIn_d_bits_T_3_data = 64'h0; // @[ScratchpadSlavePort.scala:126:24]
wire [6:0] io_dmem_req_bits_tag = 7'h0; // @[ScratchpadSlavePort.scala:43:9]
wire [6:0] io_dmem_req_bits_req_tag = 7'h0; // @[ScratchpadSlavePort.scala:66:21]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] io_dmem_req_bits_dprv = 2'h0; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] io_dmem_req_bits_req_dprv = 2'h0; // @[ScratchpadSlavePort.scala:66:21]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [1:0] nodeIn_d_bits_d_1_param = 2'h0; // @[Edges.scala:810:17]
wire [1:0] _nodeIn_d_bits_T_3_param = 2'h0; // @[ScratchpadSlavePort.scala:126:24]
wire io_dmem_req_bits_phys = 1'h1; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_no_xcpt = 1'h1; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_clock_enabled = 1'h1; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_req_phys = 1'h1; // @[ScratchpadSlavePort.scala:66:21]
wire io_dmem_req_bits_req_no_xcpt = 1'h1; // @[ScratchpadSlavePort.scala:66:21]
wire auto_in_d_bits_sink = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire auto_in_d_bits_denied = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_signed = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_dv = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_no_resp = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_bits_no_alloc = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_kill = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s2_gpa_is_pte = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_release = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_perf_tlbMiss = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_keep_clock_enabled = 1'h0; // @[ScratchpadSlavePort.scala:43:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire io_dmem_req_bits_req_signed = 1'h0; // @[ScratchpadSlavePort.scala:66:21]
wire io_dmem_req_bits_req_dv = 1'h0; // @[ScratchpadSlavePort.scala:66:21]
wire io_dmem_req_bits_req_no_resp = 1'h0; // @[ScratchpadSlavePort.scala:66:21]
wire io_dmem_req_bits_req_no_alloc = 1'h0; // @[ScratchpadSlavePort.scala:66:21]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_1_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_1_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_1_corrupt = 1'h0; // @[Edges.scala:810:17]
wire _nodeIn_d_bits_T_3_sink = 1'h0; // @[ScratchpadSlavePort.scala:126:24]
wire _nodeIn_d_bits_T_3_denied = 1'h0; // @[ScratchpadSlavePort.scala:126:24]
wire _nodeIn_d_bits_T_3_corrupt = 1'h0; // @[ScratchpadSlavePort.scala:126:24]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[ScratchpadSlavePort.scala:43:9]
wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[ScratchpadSlavePort.scala:43:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[ScratchpadSlavePort.scala:43:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[ScratchpadSlavePort.scala:43:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[ScratchpadSlavePort.scala:43:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[ScratchpadSlavePort.scala:43:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire dmem_req_valid_likely; // @[ScratchpadSlavePort.scala:114:65]
wire [33:0] io_dmem_req_bits_req_addr; // @[ScratchpadSlavePort.scala:66:21]
wire [4:0] io_dmem_req_bits_req_cmd; // @[ScratchpadSlavePort.scala:66:21]
wire [1:0] io_dmem_req_bits_req_size; // @[ScratchpadSlavePort.scala:66:21]
wire _io_dmem_s1_kill_T; // @[ScratchpadSlavePort.scala:122:30]
wire auto_in_a_ready_0; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] auto_in_d_bits_size_0; // @[ScratchpadSlavePort.scala:43:9]
wire [12:0] auto_in_d_bits_source_0; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] auto_in_d_bits_data_0; // @[ScratchpadSlavePort.scala:43:9]
wire auto_in_d_valid_0; // @[ScratchpadSlavePort.scala:43:9]
wire [33:0] io_dmem_req_bits_addr_0; // @[ScratchpadSlavePort.scala:43:9]
wire [4:0] io_dmem_req_bits_cmd_0; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] io_dmem_req_bits_size_0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_req_valid_0; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] io_dmem_s1_data_data_0; // @[ScratchpadSlavePort.scala:43:9]
wire [7:0] io_dmem_s1_data_mask_0; // @[ScratchpadSlavePort.scala:43:9]
wire io_dmem_s1_kill_0; // @[ScratchpadSlavePort.scala:43:9]
wire _nodeIn_a_ready_T; // @[ScratchpadSlavePort.scala:118:40]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[ScratchpadSlavePort.scala:43:9]
wire _nodeIn_d_valid_T_1; // @[ScratchpadSlavePort.scala:125:41]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[ScratchpadSlavePort.scala:43:9]
wire [2:0] _nodeIn_d_bits_T_3_opcode; // @[ScratchpadSlavePort.scala:126:24]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ScratchpadSlavePort.scala:43:9]
wire [1:0] _nodeIn_d_bits_T_3_size; // @[ScratchpadSlavePort.scala:126:24]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[ScratchpadSlavePort.scala:43:9]
wire [12:0] _nodeIn_d_bits_T_3_source; // @[ScratchpadSlavePort.scala:126:24]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[ScratchpadSlavePort.scala:43:9]
wire [63:0] _nodeIn_d_bits_data_T_1; // @[package.scala:88:42]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[ScratchpadSlavePort.scala:43:9]
reg [2:0] state; // @[ScratchpadSlavePort.scala:53:24]
wire _dmem_req_valid_T_2; // @[ScratchpadSlavePort.scala:113:48]
wire dmem_req_valid; // @[ScratchpadSlavePort.scala:54:30]
wire _io_dmem_req_bits_T_2 = state == 3'h4; // @[ScratchpadSlavePort.scala:53:24, :56:17, :89:19]
reg [2:0] acq_opcode; // @[ScratchpadSlavePort.scala:62:18]
reg [2:0] acq_param; // @[ScratchpadSlavePort.scala:62:18]
reg [1:0] acq_size; // @[ScratchpadSlavePort.scala:62:18]
wire [1:0] nodeIn_d_bits_d_size = acq_size; // @[Edges.scala:792:17]
wire [1:0] nodeIn_d_bits_d_1_size = acq_size; // @[Edges.scala:810:17]
reg [12:0] acq_source; // @[ScratchpadSlavePort.scala:62:18]
wire [12:0] nodeIn_d_bits_d_source = acq_source; // @[Edges.scala:792:17]
wire [12:0] nodeIn_d_bits_d_1_source = acq_source; // @[Edges.scala:810:17]
reg [31:0] acq_address; // @[ScratchpadSlavePort.scala:62:18]
reg [7:0] acq_mask; // @[ScratchpadSlavePort.scala:62:18]
assign io_dmem_s1_data_mask_0 = acq_mask; // @[ScratchpadSlavePort.scala:43:9, :62:18]
reg [63:0] acq_data; // @[ScratchpadSlavePort.scala:62:18]
assign io_dmem_s1_data_data_0 = acq_data; // @[ScratchpadSlavePort.scala:43:9, :62:18]
reg acq_corrupt; // @[ScratchpadSlavePort.scala:62:18]
wire _GEN = state == 3'h0; // @[package.scala:16:47]
wire _ready_likely_T; // @[package.scala:16:47]
assign _ready_likely_T = _GEN; // @[package.scala:16:47]
wire _ready_T; // @[ScratchpadSlavePort.scala:112:23]
assign _ready_T = _GEN; // @[package.scala:16:47]
wire _GEN_0 = state == 3'h2; // @[package.scala:16:47]
wire _ready_likely_T_1; // @[package.scala:16:47]
assign _ready_likely_T_1 = _GEN_0; // @[package.scala:16:47]
wire _ready_T_1; // @[ScratchpadSlavePort.scala:112:44]
assign _ready_T_1 = _GEN_0; // @[package.scala:16:47]
wire _nodeIn_d_bits_data_T; // @[ScratchpadSlavePort.scala:129:70]
assign _nodeIn_d_bits_data_T = _GEN_0; // @[package.scala:16:47]
wire ready_likely = _ready_likely_T | _ready_likely_T_1; // @[package.scala:16:47, :81:59]
wire _ready_T_2 = _ready_T_1 & io_dmem_resp_valid_0; // @[ScratchpadSlavePort.scala:43:9, :112:{44,56}]
wire _ready_T_3 = _ready_T_2 & nodeIn_d_ready; // @[ScratchpadSlavePort.scala:112:{56,78}]
wire ready = _ready_T | _ready_T_3; // @[ScratchpadSlavePort.scala:112:{23,35,78}]
wire _dmem_req_valid_T = nodeIn_a_valid & ready; // @[ScratchpadSlavePort.scala:112:35, :113:38]
wire _GEN_1 = state == 3'h3; // @[ScratchpadSlavePort.scala:53:24, :67:44, :113:57]
wire _dmem_req_valid_T_1; // @[ScratchpadSlavePort.scala:113:57]
assign _dmem_req_valid_T_1 = _GEN_1; // @[ScratchpadSlavePort.scala:113:57]
wire _dmem_req_valid_likely_T_1; // @[ScratchpadSlavePort.scala:114:74]
assign _dmem_req_valid_likely_T_1 = _GEN_1; // @[ScratchpadSlavePort.scala:113:57, :114:74]
wire _io_dmem_req_bits_T; // @[ScratchpadSlavePort.scala:119:48]
assign _io_dmem_req_bits_T = _GEN_1; // @[ScratchpadSlavePort.scala:113:57, :119:48]
assign _dmem_req_valid_T_2 = _dmem_req_valid_T | _dmem_req_valid_T_1; // @[ScratchpadSlavePort.scala:113:{38,48,57}]
assign dmem_req_valid = _dmem_req_valid_T_2; // @[ScratchpadSlavePort.scala:54:30, :113:48]
wire _dmem_req_valid_likely_T = nodeIn_a_valid & ready_likely; // @[package.scala:81:59]
assign dmem_req_valid_likely = _dmem_req_valid_likely_T | _dmem_req_valid_likely_T_1; // @[ScratchpadSlavePort.scala:114:{48,65,74}]
assign io_dmem_req_valid_0 = dmem_req_valid_likely; // @[ScratchpadSlavePort.scala:43:9, :114:65]
assign _nodeIn_a_ready_T = io_dmem_req_ready_0 & ready; // @[ScratchpadSlavePort.scala:43:9, :112:35, :118:40]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[ScratchpadSlavePort.scala:118:40]
wire [2:0] _io_dmem_req_bits_T_1_opcode = _io_dmem_req_bits_T ? acq_opcode : nodeIn_a_bits_opcode; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [2:0] _io_dmem_req_bits_T_1_param = _io_dmem_req_bits_T ? acq_param : nodeIn_a_bits_param; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [1:0] _io_dmem_req_bits_T_1_size = _io_dmem_req_bits_T ? acq_size : nodeIn_a_bits_size; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [12:0] _io_dmem_req_bits_T_1_source = _io_dmem_req_bits_T ? acq_source : nodeIn_a_bits_source; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [31:0] _io_dmem_req_bits_T_1_address = _io_dmem_req_bits_T ? acq_address : nodeIn_a_bits_address; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [7:0] _io_dmem_req_bits_T_1_mask = _io_dmem_req_bits_T ? acq_mask : nodeIn_a_bits_mask; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire [63:0] _io_dmem_req_bits_T_1_data = _io_dmem_req_bits_T ? acq_data : nodeIn_a_bits_data; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
wire _io_dmem_req_bits_T_1_corrupt = _io_dmem_req_bits_T ? acq_corrupt : nodeIn_a_bits_corrupt; // @[ScratchpadSlavePort.scala:62:18, :119:{41,48}]
assign io_dmem_req_bits_req_size = _io_dmem_req_bits_T_1_size; // @[ScratchpadSlavePort.scala:66:21, :119:41]
wire [1:0] io_dmem_req_bits_mask_full_desired_mask_size = _io_dmem_req_bits_T_1_size; // @[ScratchpadSlavePort.scala:119:41]
assign io_dmem_req_bits_addr_0 = io_dmem_req_bits_req_addr; // @[ScratchpadSlavePort.scala:43:9, :66:21]
assign io_dmem_req_bits_cmd_0 = io_dmem_req_bits_req_cmd; // @[ScratchpadSlavePort.scala:43:9, :66:21]
assign io_dmem_req_bits_size_0 = io_dmem_req_bits_req_size; // @[ScratchpadSlavePort.scala:43:9, :66:21]
wire _GEN_2 = _io_dmem_req_bits_T_1_param == 3'h0; // @[ScratchpadSlavePort.scala:70:63, :119:41]
wire _io_dmem_req_bits_req_cmd_T; // @[ScratchpadSlavePort.scala:70:63]
assign _io_dmem_req_bits_req_cmd_T = _GEN_2; // @[ScratchpadSlavePort.scala:70:63]
wire _io_dmem_req_bits_req_cmd_T_10; // @[ScratchpadSlavePort.scala:76:63]
assign _io_dmem_req_bits_req_cmd_T_10 = _GEN_2; // @[ScratchpadSlavePort.scala:70:63, :76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_1 = _io_dmem_req_bits_req_cmd_T ? 4'hC : 4'h0; // @[ScratchpadSlavePort.scala:70:63]
wire _GEN_3 = _io_dmem_req_bits_T_1_param == 3'h1; // @[ScratchpadSlavePort.scala:67:44, :70:63, :119:41]
wire _io_dmem_req_bits_req_cmd_T_2; // @[ScratchpadSlavePort.scala:70:63]
assign _io_dmem_req_bits_req_cmd_T_2 = _GEN_3; // @[ScratchpadSlavePort.scala:70:63]
wire _io_dmem_req_bits_req_cmd_T_12; // @[ScratchpadSlavePort.scala:76:63]
assign _io_dmem_req_bits_req_cmd_T_12 = _GEN_3; // @[ScratchpadSlavePort.scala:70:63, :76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_3 = _io_dmem_req_bits_req_cmd_T_2 ? 4'hD : _io_dmem_req_bits_req_cmd_T_1; // @[ScratchpadSlavePort.scala:70:63]
wire _GEN_4 = _io_dmem_req_bits_T_1_param == 3'h2; // @[ScratchpadSlavePort.scala:67:44, :70:63, :119:41]
wire _io_dmem_req_bits_req_cmd_T_4; // @[ScratchpadSlavePort.scala:70:63]
assign _io_dmem_req_bits_req_cmd_T_4 = _GEN_4; // @[ScratchpadSlavePort.scala:70:63]
wire _io_dmem_req_bits_req_cmd_T_14; // @[ScratchpadSlavePort.scala:76:63]
assign _io_dmem_req_bits_req_cmd_T_14 = _GEN_4; // @[ScratchpadSlavePort.scala:70:63, :76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_5 = _io_dmem_req_bits_req_cmd_T_4 ? 4'hE : _io_dmem_req_bits_req_cmd_T_3; // @[ScratchpadSlavePort.scala:70:63]
wire _GEN_5 = _io_dmem_req_bits_T_1_param == 3'h3; // @[ScratchpadSlavePort.scala:67:44, :70:63, :119:41]
wire _io_dmem_req_bits_req_cmd_T_6; // @[ScratchpadSlavePort.scala:70:63]
assign _io_dmem_req_bits_req_cmd_T_6 = _GEN_5; // @[ScratchpadSlavePort.scala:70:63]
wire _io_dmem_req_bits_req_cmd_T_16; // @[ScratchpadSlavePort.scala:76:63]
assign _io_dmem_req_bits_req_cmd_T_16 = _GEN_5; // @[ScratchpadSlavePort.scala:70:63, :76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_7 = _io_dmem_req_bits_req_cmd_T_6 ? 4'hF : _io_dmem_req_bits_req_cmd_T_5; // @[ScratchpadSlavePort.scala:70:63]
wire _io_dmem_req_bits_req_cmd_T_8 = _io_dmem_req_bits_T_1_param == 3'h4; // @[ScratchpadSlavePort.scala:70:63, :119:41]
wire [3:0] _io_dmem_req_bits_req_cmd_T_9 = _io_dmem_req_bits_req_cmd_T_8 ? 4'h8 : _io_dmem_req_bits_req_cmd_T_7; // @[ScratchpadSlavePort.scala:70:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_11 = _io_dmem_req_bits_req_cmd_T_10 ? 4'h9 : 4'h0; // @[ScratchpadSlavePort.scala:76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_13 = _io_dmem_req_bits_req_cmd_T_12 ? 4'hA : _io_dmem_req_bits_req_cmd_T_11; // @[ScratchpadSlavePort.scala:76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_15 = _io_dmem_req_bits_req_cmd_T_14 ? 4'hB : _io_dmem_req_bits_req_cmd_T_13; // @[ScratchpadSlavePort.scala:76:63]
wire [3:0] _io_dmem_req_bits_req_cmd_T_17 = _io_dmem_req_bits_req_cmd_T_16 ? 4'h4 : _io_dmem_req_bits_req_cmd_T_15; // @[ScratchpadSlavePort.scala:76:63]
wire _io_dmem_req_bits_req_cmd_T_18 = _io_dmem_req_bits_T_1_opcode == 3'h0; // @[ScratchpadSlavePort.scala:67:44, :119:41]
wire _io_dmem_req_bits_req_cmd_T_19 = _io_dmem_req_bits_req_cmd_T_18; // @[ScratchpadSlavePort.scala:67:44]
wire _GEN_6 = _io_dmem_req_bits_T_1_opcode == 3'h1; // @[ScratchpadSlavePort.scala:67:44, :119:41]
wire _io_dmem_req_bits_req_cmd_T_20; // @[ScratchpadSlavePort.scala:67:44]
assign _io_dmem_req_bits_req_cmd_T_20 = _GEN_6; // @[ScratchpadSlavePort.scala:67:44]
wire _io_dmem_req_bits_T_3; // @[ScratchpadSlavePort.scala:89:43]
assign _io_dmem_req_bits_T_3 = _GEN_6; // @[ScratchpadSlavePort.scala:67:44, :89:43]
wire [4:0] _io_dmem_req_bits_req_cmd_T_21 = _io_dmem_req_bits_req_cmd_T_20 ? 5'h11 : {4'h0, _io_dmem_req_bits_req_cmd_T_19}; // @[ScratchpadSlavePort.scala:67:44]
wire _io_dmem_req_bits_req_cmd_T_22 = _io_dmem_req_bits_T_1_opcode == 3'h2; // @[ScratchpadSlavePort.scala:67:44, :119:41]
wire [4:0] _io_dmem_req_bits_req_cmd_T_23 = _io_dmem_req_bits_req_cmd_T_22 ? {1'h0, _io_dmem_req_bits_req_cmd_T_9} : _io_dmem_req_bits_req_cmd_T_21; // @[ScratchpadSlavePort.scala:67:44, :70:63]
wire _io_dmem_req_bits_req_cmd_T_24 = _io_dmem_req_bits_T_1_opcode == 3'h3; // @[ScratchpadSlavePort.scala:67:44, :119:41]
wire [4:0] _io_dmem_req_bits_req_cmd_T_25 = _io_dmem_req_bits_req_cmd_T_24 ? {1'h0, _io_dmem_req_bits_req_cmd_T_17} : _io_dmem_req_bits_req_cmd_T_23; // @[ScratchpadSlavePort.scala:67:44, :76:63]
wire _io_dmem_req_bits_req_cmd_T_26 = _io_dmem_req_bits_T_1_opcode == 3'h4; // @[ScratchpadSlavePort.scala:67:44, :119:41]
wire [4:0] _io_dmem_req_bits_req_cmd_T_27 = _io_dmem_req_bits_req_cmd_T_26 ? 5'h0 : _io_dmem_req_bits_req_cmd_T_25; // @[ScratchpadSlavePort.scala:67:44]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T = _io_dmem_req_bits_T_1_address[0]; // @[ScratchpadSlavePort.scala:119:41]
wire _io_dmem_req_bits_mask_full_desired_mask_lower_T = _io_dmem_req_bits_T_1_address[0]; // @[ScratchpadSlavePort.scala:119:41]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_1 = _io_dmem_req_bits_mask_full_desired_mask_upper_T; // @[AMOALU.scala:20:{22,27}]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_2 = |io_dmem_req_bits_mask_full_desired_mask_size; // @[AMOALU.scala:11:18, :20:53]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_3 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_2; // @[AMOALU.scala:20:{47,53}]
wire io_dmem_req_bits_mask_full_desired_mask_upper = _io_dmem_req_bits_mask_full_desired_mask_upper_T_1 | _io_dmem_req_bits_mask_full_desired_mask_upper_T_3; // @[AMOALU.scala:20:{22,42,47}]
wire io_dmem_req_bits_mask_full_desired_mask_lower = ~_io_dmem_req_bits_mask_full_desired_mask_lower_T; // @[AMOALU.scala:21:{22,27}]
wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_T = {io_dmem_req_bits_mask_full_desired_mask_upper, io_dmem_req_bits_mask_full_desired_mask_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_4 = _io_dmem_req_bits_T_1_address[1]; // @[ScratchpadSlavePort.scala:119:41]
wire _io_dmem_req_bits_mask_full_desired_mask_lower_T_1 = _io_dmem_req_bits_T_1_address[1]; // @[ScratchpadSlavePort.scala:119:41]
wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_5 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_4 ? _io_dmem_req_bits_mask_full_desired_mask_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_6 = io_dmem_req_bits_mask_full_desired_mask_size[1]; // @[AMOALU.scala:11:18, :20:53]
wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_7 = {2{_io_dmem_req_bits_mask_full_desired_mask_upper_T_6}}; // @[AMOALU.scala:20:{47,53}]
wire [1:0] io_dmem_req_bits_mask_full_desired_mask_upper_1 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_5 | _io_dmem_req_bits_mask_full_desired_mask_upper_T_7; // @[AMOALU.scala:20:{22,42,47}]
wire [1:0] io_dmem_req_bits_mask_full_desired_mask_lower_1 = _io_dmem_req_bits_mask_full_desired_mask_lower_T_1 ? 2'h0 : _io_dmem_req_bits_mask_full_desired_mask_T; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_T_1 = {io_dmem_req_bits_mask_full_desired_mask_upper_1, io_dmem_req_bits_mask_full_desired_mask_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_8 = _io_dmem_req_bits_T_1_address[2]; // @[ScratchpadSlavePort.scala:119:41]
wire _io_dmem_req_bits_mask_full_desired_mask_lower_T_2 = _io_dmem_req_bits_T_1_address[2]; // @[ScratchpadSlavePort.scala:119:41]
wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_9 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_8 ? _io_dmem_req_bits_mask_full_desired_mask_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _io_dmem_req_bits_mask_full_desired_mask_upper_T_10 = &io_dmem_req_bits_mask_full_desired_mask_size; // @[AMOALU.scala:11:18, :20:53]
wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_11 = {4{_io_dmem_req_bits_mask_full_desired_mask_upper_T_10}}; // @[AMOALU.scala:20:{47,53}]
wire [3:0] io_dmem_req_bits_mask_full_desired_mask_upper_2 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_9 | _io_dmem_req_bits_mask_full_desired_mask_upper_T_11; // @[AMOALU.scala:20:{22,42,47}]
wire [3:0] io_dmem_req_bits_mask_full_desired_mask_lower_2 = _io_dmem_req_bits_mask_full_desired_mask_lower_T_2 ? 4'h0 : _io_dmem_req_bits_mask_full_desired_mask_T_1; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [7:0] io_dmem_req_bits_mask_full_desired_mask = {io_dmem_req_bits_mask_full_desired_mask_upper_2, io_dmem_req_bits_mask_full_desired_mask_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire [7:0] _io_dmem_req_bits_mask_full_T = ~io_dmem_req_bits_mask_full_desired_mask; // @[ScratchpadSlavePort.scala:87:19]
wire [7:0] _io_dmem_req_bits_mask_full_T_1 = _io_dmem_req_bits_T_1_mask | _io_dmem_req_bits_mask_full_T; // @[ScratchpadSlavePort.scala:87:{17,19}, :119:41]
wire io_dmem_req_bits_mask_full = &_io_dmem_req_bits_mask_full_T_1; // @[ScratchpadSlavePort.scala:87:{17,34}]
wire _io_dmem_req_bits_T_4 = _io_dmem_req_bits_T_3 & io_dmem_req_bits_mask_full; // @[ScratchpadSlavePort.scala:87:34, :89:{43,73}]
wire _io_dmem_req_bits_T_5 = _io_dmem_req_bits_T_2 | _io_dmem_req_bits_T_4; // @[ScratchpadSlavePort.scala:89:{19,30,73}]
assign io_dmem_req_bits_req_cmd = _io_dmem_req_bits_T_5 ? 5'h1 : _io_dmem_req_bits_req_cmd_T_27; // @[ScratchpadSlavePort.scala:66:21, :67:{15,44}, :89:{30,88}, :90:17]
assign io_dmem_req_bits_req_addr = {2'h0, _io_dmem_req_bits_T_1_address}; // @[ScratchpadSlavePort.scala:66:21, :95:16, :119:41]
assign _io_dmem_s1_kill_T = state != 3'h1; // @[ScratchpadSlavePort.scala:53:24, :67:44, :122:30]
assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T; // @[ScratchpadSlavePort.scala:43:9, :122:30]
wire _nodeIn_d_valid_T = state == 3'h5; // @[ScratchpadSlavePort.scala:53:24, :125:50]
assign _nodeIn_d_valid_T_1 = io_dmem_resp_valid_0 | _nodeIn_d_valid_T; // @[ScratchpadSlavePort.scala:43:9, :125:{41,50}]
assign nodeIn_d_valid = _nodeIn_d_valid_T_1; // @[ScratchpadSlavePort.scala:125:41]
wire _nodeIn_d_bits_T = acq_opcode == 3'h0; // @[package.scala:16:47]
wire _nodeIn_d_bits_T_1 = acq_opcode == 3'h1; // @[package.scala:16:47]
wire _nodeIn_d_bits_T_2 = _nodeIn_d_bits_T | _nodeIn_d_bits_T_1; // @[package.scala:16:47, :81:59]
assign _nodeIn_d_bits_T_3_opcode = {2'h0, ~_nodeIn_d_bits_T_2}; // @[package.scala:81:59]
assign _nodeIn_d_bits_T_3_size = _nodeIn_d_bits_T_2 ? nodeIn_d_bits_d_size : nodeIn_d_bits_d_1_size; // @[package.scala:81:59]
assign _nodeIn_d_bits_T_3_source = _nodeIn_d_bits_T_2 ? nodeIn_d_bits_d_source : nodeIn_d_bits_d_1_source; // @[package.scala:81:59]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_3_opcode; // @[ScratchpadSlavePort.scala:126:24]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_3_size; // @[ScratchpadSlavePort.scala:126:24]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_3_source; // @[ScratchpadSlavePort.scala:126:24]
reg [63:0] nodeIn_d_bits_data_r; // @[package.scala:88:63]
assign _nodeIn_d_bits_data_T_1 = _nodeIn_d_bits_data_T ? io_dmem_resp_bits_data_raw_0 : nodeIn_d_bits_data_r; // @[package.scala:88:{42,63}]
assign nodeIn_d_bits_data = _nodeIn_d_bits_data_T_1; // @[package.scala:88:42]
always @(posedge clock) begin // @[ScratchpadSlavePort.scala:43:9]
if (reset) // @[ScratchpadSlavePort.scala:43:9]
state <= 3'h4; // @[ScratchpadSlavePort.scala:53:24]
else if (dmem_req_valid & io_dmem_req_ready_0) // @[ScratchpadSlavePort.scala:43:9, :54:30, :60:26]
state <= 3'h1; // @[ScratchpadSlavePort.scala:53:24, :67:44]
else if (io_dmem_s2_nack_0) // @[ScratchpadSlavePort.scala:43:9]
state <= 3'h3; // @[ScratchpadSlavePort.scala:53:24, :67:44]
else if (nodeIn_d_ready & nodeIn_d_valid) // @[Decoupled.scala:51:35]
state <= 3'h0; // @[ScratchpadSlavePort.scala:53:24]
else if (io_dmem_resp_valid_0) // @[ScratchpadSlavePort.scala:43:9]
state <= 3'h5; // @[ScratchpadSlavePort.scala:53:24]
else if (_io_dmem_req_bits_T_2 & nodeIn_a_valid) // @[ScratchpadSlavePort.scala:56:28, :89:19]
state <= 3'h0; // @[ScratchpadSlavePort.scala:53:24]
else if (state == 3'h1) // @[ScratchpadSlavePort.scala:53:24, :55:17, :67:44]
state <= 3'h2; // @[ScratchpadSlavePort.scala:53:24, :67:44]
if (nodeIn_a_ready & nodeIn_a_valid) begin // @[Decoupled.scala:51:35]
acq_opcode <= nodeIn_a_bits_opcode; // @[ScratchpadSlavePort.scala:62:18]
acq_param <= nodeIn_a_bits_param; // @[ScratchpadSlavePort.scala:62:18]
acq_size <= nodeIn_a_bits_size; // @[ScratchpadSlavePort.scala:62:18]
acq_source <= nodeIn_a_bits_source; // @[ScratchpadSlavePort.scala:62:18]
acq_address <= nodeIn_a_bits_address; // @[ScratchpadSlavePort.scala:62:18]
acq_mask <= nodeIn_a_bits_mask; // @[ScratchpadSlavePort.scala:62:18]
acq_data <= nodeIn_a_bits_data; // @[ScratchpadSlavePort.scala:62:18]
acq_corrupt <= nodeIn_a_bits_corrupt; // @[ScratchpadSlavePort.scala:62:18]
end
if (_nodeIn_d_bits_data_T) // @[ScratchpadSlavePort.scala:129:70]
nodeIn_d_bits_data_r <= io_dmem_resp_bits_data_raw_0; // @[package.scala:88:63]
always @(posedge)
assign auto_in_a_ready = auto_in_a_ready_0; // @[ScratchpadSlavePort.scala:43:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[ScratchpadSlavePort.scala:43:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[ScratchpadSlavePort.scala:43:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[ScratchpadSlavePort.scala:43:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[ScratchpadSlavePort.scala:43:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_req_valid = io_dmem_req_valid_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_req_bits_addr = io_dmem_req_bits_addr_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_req_bits_cmd = io_dmem_req_bits_cmd_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_req_bits_size = io_dmem_req_bits_size_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_s1_kill = io_dmem_s1_kill_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_s1_data_data = io_dmem_s1_data_data_0; // @[ScratchpadSlavePort.scala:43:9]
assign io_dmem_s1_data_mask = io_dmem_s1_data_mask_0; // @[ScratchpadSlavePort.scala:43:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_250( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_506 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_454( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module l2_tlb_ram_0( // @[DescribedSRAM.scala:17:26]
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [44:0] RW0_wdata,
output [44:0] RW0_rdata
);
l2_tlb_ram_0_ext l2_tlb_ram_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module FPU_2( // @[FPU.scala:735:7]
input clock, // @[FPU.scala:735:7]
input reset, // @[FPU.scala:735:7]
input [2:0] io_hartid, // @[FPU.scala:736:14]
input [63:0] io_time, // @[FPU.scala:736:14]
input [31:0] io_inst, // @[FPU.scala:736:14]
input [63:0] io_fromint_data, // @[FPU.scala:736:14]
input [2:0] io_fcsr_rm, // @[FPU.scala:736:14]
output io_fcsr_flags_valid, // @[FPU.scala:736:14]
output [4:0] io_fcsr_flags_bits, // @[FPU.scala:736:14]
output [63:0] io_store_data, // @[FPU.scala:736:14]
output [63:0] io_toint_data, // @[FPU.scala:736:14]
input io_ll_resp_val, // @[FPU.scala:736:14]
input [2:0] io_ll_resp_type, // @[FPU.scala:736:14]
input [4:0] io_ll_resp_tag, // @[FPU.scala:736:14]
input [63:0] io_ll_resp_data, // @[FPU.scala:736:14]
input io_valid, // @[FPU.scala:736:14]
output io_fcsr_rdy, // @[FPU.scala:736:14]
output io_nack_mem, // @[FPU.scala:736:14]
output io_illegal_rm, // @[FPU.scala:736:14]
input io_killx, // @[FPU.scala:736:14]
input io_killm, // @[FPU.scala:736:14]
output io_dec_ldst, // @[FPU.scala:736:14]
output io_dec_wen, // @[FPU.scala:736:14]
output io_dec_ren1, // @[FPU.scala:736:14]
output io_dec_ren2, // @[FPU.scala:736:14]
output io_dec_ren3, // @[FPU.scala:736:14]
output io_dec_swap12, // @[FPU.scala:736:14]
output io_dec_swap23, // @[FPU.scala:736:14]
output [1:0] io_dec_typeTagIn, // @[FPU.scala:736:14]
output [1:0] io_dec_typeTagOut, // @[FPU.scala:736:14]
output io_dec_fromint, // @[FPU.scala:736:14]
output io_dec_toint, // @[FPU.scala:736:14]
output io_dec_fastpipe, // @[FPU.scala:736:14]
output io_dec_fma, // @[FPU.scala:736:14]
output io_dec_div, // @[FPU.scala:736:14]
output io_dec_sqrt, // @[FPU.scala:736:14]
output io_dec_wflags, // @[FPU.scala:736:14]
output io_dec_vec, // @[FPU.scala:736:14]
output io_sboard_set, // @[FPU.scala:736:14]
output io_sboard_clr, // @[FPU.scala:736:14]
output [4:0] io_sboard_clra, // @[FPU.scala:736:14]
input io_keep_clock_enabled // @[FPU.scala:736:14]
);
wire wdata_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire wdata_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire wdata_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire _divSqrt_2_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [64:0] _divSqrt_2_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_2_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [32:0] _divSqrt_1_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_1_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [16:0] _divSqrt_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_io_exceptionFlags; // @[FPU.scala:1027:55]
wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:919:28]
wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:919:28]
wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:913:28]
wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:913:28]
wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:891:20]
wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:891:20]
wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:886:20]
wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:886:20]
wire [2:0] _fpiu_io_out_bits_in_rm; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in1; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in2; // @[FPU.scala:876:20]
wire _fpiu_io_out_bits_lt; // @[FPU.scala:876:20]
wire [4:0] _fpiu_io_out_bits_exc; // @[FPU.scala:876:20]
wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:872:20]
wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:872:20]
wire [64:0] _regfile_ext_R0_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R1_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R2_data; // @[FPU.scala:818:20]
wire [2:0] io_hartid_0 = io_hartid; // @[FPU.scala:735:7]
wire [63:0] io_time_0 = io_time; // @[FPU.scala:735:7]
wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:735:7]
wire [63:0] io_fromint_data_0 = io_fromint_data; // @[FPU.scala:735:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[FPU.scala:735:7]
wire io_ll_resp_val_0 = io_ll_resp_val; // @[FPU.scala:735:7]
wire [2:0] io_ll_resp_type_0 = io_ll_resp_type; // @[FPU.scala:735:7]
wire [4:0] io_ll_resp_tag_0 = io_ll_resp_tag; // @[FPU.scala:735:7]
wire [63:0] io_ll_resp_data_0 = io_ll_resp_data; // @[FPU.scala:735:7]
wire io_valid_0 = io_valid; // @[FPU.scala:735:7]
wire io_killx_0 = io_killx; // @[FPU.scala:735:7]
wire io_killm_0 = io_killm; // @[FPU.scala:735:7]
wire io_keep_clock_enabled_0 = io_keep_clock_enabled; // @[FPU.scala:735:7]
wire frfWriteBundle_0_clock = clock; // @[FPU.scala:805:44]
wire frfWriteBundle_0_reset = reset; // @[FPU.scala:805:44]
wire frfWriteBundle_1_clock = clock; // @[FPU.scala:805:44]
wire frfWriteBundle_1_reset = reset; // @[FPU.scala:805:44]
wire clock_en = 1'h1; // @[FPU.scala:735:7, :745:31]
wire _killm_T_1 = 1'h1; // @[FPU.scala:735:7, :785:44]
wire prevOK_prevOK = 1'h1; // @[FPU.scala:384:33, :735:7]
wire _wdata_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42, :735:7]
wire _wdata_opts_bigger_T = 1'h1; // @[FPU.scala:249:56, :735:7]
wire _wdata_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42, :735:7]
wire _wdata_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56, :735:7]
wire prevOK_prevOK_1 = 1'h1; // @[FPU.scala:384:33, :735:7]
wire _io_cp_req_ready_T_3 = 1'h1; // @[FPU.scala:735:7, :991:39]
wire _io_nack_mem_T_2 = 1'h1; // @[FPU.scala:735:7, :1003:86]
wire _io_sboard_set_T = 1'h1; // @[FPU.scala:735:7, :1006:36]
wire _io_sboard_clr_T = 1'h1; // @[FPU.scala:735:7, :1007:20]
wire _clock_en_reg_T = 1'h1; // @[FPU.scala:735:7, :1051:19]
wire _clock_en_reg_T_1 = 1'h1; // @[FPU.scala:735:7, :1051:37]
wire _clock_en_reg_T_2 = 1'h1; // @[FPU.scala:735:7, :1052:27]
wire _clock_en_reg_T_3 = 1'h1; // @[FPU.scala:735:7, :1053:14]
wire _clock_en_reg_T_4 = 1'h1; // @[FPU.scala:735:7, :1054:15]
wire _clock_en_reg_T_5 = 1'h1; // @[FPU.scala:735:7, :1055:19]
wire _clock_en_reg_T_6 = 1'h1; // @[FPU.scala:735:7, :1055:35]
wire _clock_en_reg_T_7 = 1'h1; // @[FPU.scala:735:7, :1056:18]
wire _clock_en_reg_T_9 = 1'h1; // @[FPU.scala:735:7, :1056:33]
wire _clock_en_reg_T_10 = 1'h1; // @[FPU.scala:735:7, :1057:13]
wire _clock_en_reg_T_11 = 1'h1; // @[FPU.scala:735:7, :1057:33]
wire io_cp_req_valid = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ldst = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_wen = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren1 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren2 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren3 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_swap12 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_swap23 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fromint = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_toint = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fastpipe = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fma = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_div = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_sqrt = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_wflags = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_vec = 1'h0; // @[FPU.scala:735:7]
wire io_cp_resp_ready = 1'h0; // @[FPU.scala:735:7]
wire ex_cp_valid = 1'h0; // @[Decoupled.scala:51:35]
wire cp_ctrl_ldst = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_wen = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren1 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren2 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren3 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_swap12 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_swap23 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fromint = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_toint = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fastpipe = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fma = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_div = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_sqrt = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_wflags = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_vec = 1'h0; // @[FPU.scala:794:21]
wire frfWriteBundle_0_excpt = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_0_valid = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_0_wrenx = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_excpt = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_valid = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_wrenx = 1'h0; // @[FPU.scala:805:44]
wire _wbInfo_0_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _wbInfo_1_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _wbInfo_2_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _io_cp_req_ready_T_2 = 1'h0; // @[FPU.scala:991:55]
wire [64:0] io_cp_req_bits_in1 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] io_cp_req_bits_in2 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] io_cp_req_bits_in3 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31]
wire [2:0] io_v_sew = 3'h0; // @[FPU.scala:735:7]
wire [2:0] io_cp_req_bits_rm = 3'h0; // @[FPU.scala:735:7]
wire [2:0] frfWriteBundle_0_priv_mode = 3'h0; // @[FPU.scala:805:44]
wire [2:0] frfWriteBundle_1_priv_mode = 3'h0; // @[FPU.scala:805:44]
wire [1:0] io_cp_req_bits_typeTagIn = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_typeTagOut = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_fmaCmd = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_typ = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_fmt = 2'h0; // @[FPU.scala:735:7]
wire [1:0] cp_ctrl_typeTagIn = 2'h0; // @[FPU.scala:794:21]
wire [1:0] cp_ctrl_typeTagOut = 2'h0; // @[FPU.scala:794:21]
wire [4:0] io_cp_resp_bits_exc = 5'h0; // @[FPU.scala:735:7]
wire [4:0] frfWriteBundle_0_rd0src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_0_rd1src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_rd0src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_rd1src = 5'h0; // @[FPU.scala:805:44]
wire [64:0] _divSqrt_wdata_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire [32:0] _divSqrt_wdata_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26]
wire [31:0] frfWriteBundle_0_inst = 32'h0; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_1_inst = 32'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_pc = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_rd0val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_rd1val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_pc = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_rd0val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_rd1val = 64'h0; // @[FPU.scala:805:44]
wire _io_fcsr_flags_valid_T_2; // @[FPU.scala:995:56]
wire [4:0] _io_fcsr_flags_bits_T_5; // @[FPU.scala:998:42]
wire _io_fcsr_rdy_T_8; // @[FPU.scala:1002:18]
wire _io_nack_mem_T_3; // @[FPU.scala:1003:83]
wire _io_illegal_rm_T_8; // @[FPU.scala:1011:53]
wire id_ctrl_ldst; // @[FPU.scala:752:25]
wire id_ctrl_wen; // @[FPU.scala:752:25]
wire id_ctrl_ren1; // @[FPU.scala:752:25]
wire id_ctrl_ren2; // @[FPU.scala:752:25]
wire id_ctrl_ren3; // @[FPU.scala:752:25]
wire id_ctrl_swap12; // @[FPU.scala:752:25]
wire id_ctrl_swap23; // @[FPU.scala:752:25]
wire [1:0] id_ctrl_typeTagIn; // @[FPU.scala:752:25]
wire [1:0] id_ctrl_typeTagOut; // @[FPU.scala:752:25]
wire id_ctrl_fromint; // @[FPU.scala:752:25]
wire id_ctrl_toint; // @[FPU.scala:752:25]
wire id_ctrl_fastpipe; // @[FPU.scala:752:25]
wire id_ctrl_fma; // @[FPU.scala:752:25]
wire id_ctrl_div; // @[FPU.scala:752:25]
wire id_ctrl_sqrt; // @[FPU.scala:752:25]
wire id_ctrl_wflags; // @[FPU.scala:752:25]
wire id_ctrl_vec; // @[FPU.scala:752:25]
wire _io_sboard_set_T_8; // @[FPU.scala:1006:49]
wire _io_sboard_clr_T_6; // @[FPU.scala:1007:33]
wire [4:0] waddr; // @[FPU.scala:963:18]
wire _io_cp_req_ready_T_6; // @[FPU.scala:991:71]
wire io_fcsr_flags_valid_0; // @[FPU.scala:735:7]
wire [4:0] io_fcsr_flags_bits_0; // @[FPU.scala:735:7]
wire io_dec_ldst_0; // @[FPU.scala:735:7]
wire io_dec_wen_0; // @[FPU.scala:735:7]
wire io_dec_ren1_0; // @[FPU.scala:735:7]
wire io_dec_ren2_0; // @[FPU.scala:735:7]
wire io_dec_ren3_0; // @[FPU.scala:735:7]
wire io_dec_swap12_0; // @[FPU.scala:735:7]
wire io_dec_swap23_0; // @[FPU.scala:735:7]
wire [1:0] io_dec_typeTagIn_0; // @[FPU.scala:735:7]
wire [1:0] io_dec_typeTagOut_0; // @[FPU.scala:735:7]
wire io_dec_fromint_0; // @[FPU.scala:735:7]
wire io_dec_toint_0; // @[FPU.scala:735:7]
wire io_dec_fastpipe_0; // @[FPU.scala:735:7]
wire io_dec_fma_0; // @[FPU.scala:735:7]
wire io_dec_div_0; // @[FPU.scala:735:7]
wire io_dec_sqrt_0; // @[FPU.scala:735:7]
wire io_dec_wflags_0; // @[FPU.scala:735:7]
wire io_dec_vec_0; // @[FPU.scala:735:7]
wire io_cp_req_ready; // @[FPU.scala:735:7]
wire [64:0] io_cp_resp_bits_data; // @[FPU.scala:735:7]
wire io_cp_resp_valid; // @[FPU.scala:735:7]
wire [63:0] io_store_data_0; // @[FPU.scala:735:7]
wire [63:0] io_toint_data_0; // @[FPU.scala:735:7]
wire io_fcsr_rdy_0; // @[FPU.scala:735:7]
wire io_nack_mem_0; // @[FPU.scala:735:7]
wire io_illegal_rm_0; // @[FPU.scala:735:7]
wire io_sboard_set_0; // @[FPU.scala:735:7]
wire io_sboard_clr_0; // @[FPU.scala:735:7]
wire [4:0] io_sboard_clra_0; // @[FPU.scala:735:7]
assign io_dec_ldst_0 = id_ctrl_ldst; // @[FPU.scala:735:7, :752:25]
assign io_dec_wen_0 = id_ctrl_wen; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren1_0 = id_ctrl_ren1; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren2_0 = id_ctrl_ren2; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren3_0 = id_ctrl_ren3; // @[FPU.scala:735:7, :752:25]
assign io_dec_swap12_0 = id_ctrl_swap12; // @[FPU.scala:735:7, :752:25]
assign io_dec_swap23_0 = id_ctrl_swap23; // @[FPU.scala:735:7, :752:25]
assign io_dec_typeTagIn_0 = id_ctrl_typeTagIn; // @[FPU.scala:735:7, :752:25]
assign io_dec_typeTagOut_0 = id_ctrl_typeTagOut; // @[FPU.scala:735:7, :752:25]
assign io_dec_fromint_0 = id_ctrl_fromint; // @[FPU.scala:735:7, :752:25]
assign io_dec_toint_0 = id_ctrl_toint; // @[FPU.scala:735:7, :752:25]
assign io_dec_fastpipe_0 = id_ctrl_fastpipe; // @[FPU.scala:735:7, :752:25]
assign io_dec_fma_0 = id_ctrl_fma; // @[FPU.scala:735:7, :752:25]
assign io_dec_div_0 = id_ctrl_div; // @[FPU.scala:735:7, :752:25]
assign io_dec_sqrt_0 = id_ctrl_sqrt; // @[FPU.scala:735:7, :752:25]
assign io_dec_wflags_0 = id_ctrl_wflags; // @[FPU.scala:735:7, :752:25]
assign io_dec_vec_0 = id_ctrl_vec; // @[FPU.scala:735:7, :752:25]
reg ex_reg_valid; // @[FPU.scala:767:29]
wire req_valid = ex_reg_valid; // @[FPU.scala:767:29, :780:32]
reg [31:0] ex_reg_inst; // @[FPU.scala:768:30]
reg ex_reg_ctrl_ldst; // @[FPU.scala:769:30]
wire ex_ctrl_ldst = ex_reg_ctrl_ldst; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_wen; // @[FPU.scala:769:30]
wire ex_ctrl_wen = ex_reg_ctrl_wen; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren1; // @[FPU.scala:769:30]
wire ex_ctrl_ren1 = ex_reg_ctrl_ren1; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren2; // @[FPU.scala:769:30]
wire ex_ctrl_ren2 = ex_reg_ctrl_ren2; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren3; // @[FPU.scala:769:30]
wire ex_ctrl_ren3 = ex_reg_ctrl_ren3; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_swap12; // @[FPU.scala:769:30]
wire ex_ctrl_swap12 = ex_reg_ctrl_swap12; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_swap23; // @[FPU.scala:769:30]
wire ex_ctrl_swap23 = ex_reg_ctrl_swap23; // @[FPU.scala:769:30, :800:20]
reg [1:0] ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30]
wire [1:0] ex_ctrl_typeTagIn = ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30, :800:20]
reg [1:0] ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30]
wire [1:0] ex_ctrl_typeTagOut = ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fromint; // @[FPU.scala:769:30]
wire ex_ctrl_fromint = ex_reg_ctrl_fromint; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_toint; // @[FPU.scala:769:30]
wire ex_ctrl_toint = ex_reg_ctrl_toint; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30]
wire ex_ctrl_fastpipe = ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fma; // @[FPU.scala:769:30]
wire ex_ctrl_fma = ex_reg_ctrl_fma; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_div; // @[FPU.scala:769:30]
wire ex_ctrl_div = ex_reg_ctrl_div; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_sqrt; // @[FPU.scala:769:30]
wire ex_ctrl_sqrt = ex_reg_ctrl_sqrt; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_wflags; // @[FPU.scala:769:30]
wire ex_ctrl_wflags = ex_reg_ctrl_wflags; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_vec; // @[FPU.scala:769:30]
wire ex_ctrl_vec = ex_reg_ctrl_vec; // @[FPU.scala:769:30, :800:20]
reg [4:0] ex_ra_0; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T = ex_ra_0; // @[FPU.scala:770:31, :832:37]
reg [4:0] ex_ra_1; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T_2 = ex_ra_1; // @[FPU.scala:770:31, :832:37]
reg [4:0] ex_ra_2; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T_4 = ex_ra_2; // @[FPU.scala:770:31, :832:37]
reg load_wb; // @[FPU.scala:773:24]
wire frfWriteBundle_0_wrenf = load_wb; // @[FPU.scala:773:24, :805:44]
wire [1:0] _load_wb_typeTag_T = io_ll_resp_type_0[1:0]; // @[FPU.scala:735:7, :774:50]
wire [2:0] _load_wb_typeTag_T_1 = {1'h0, _load_wb_typeTag_T} - 3'h1; // @[FPU.scala:774:{50,56}]
wire [1:0] _load_wb_typeTag_T_2 = _load_wb_typeTag_T_1[1:0]; // @[FPU.scala:774:56]
reg [1:0] load_wb_typeTag; // @[FPU.scala:774:34]
reg [63:0] load_wb_data; // @[FPU.scala:775:31]
reg [4:0] load_wb_tag; // @[FPU.scala:776:30]
wire [4:0] frfWriteBundle_0_wrdst = load_wb_tag; // @[FPU.scala:776:30, :805:44]
reg mem_reg_valid; // @[FPU.scala:784:30]
wire _killm_T = io_killm_0 | io_nack_mem_0; // @[FPU.scala:735:7, :785:25]
wire killm = _killm_T; // @[FPU.scala:785:{25,41}]
wire _killx_T = mem_reg_valid & killm; // @[FPU.scala:784:30, :785:41, :789:41]
wire killx = io_killx_0 | _killx_T; // @[FPU.scala:735:7, :789:{24,41}]
wire _mem_reg_valid_T = ~killx; // @[FPU.scala:789:24, :790:36]
wire _mem_reg_valid_T_1 = ex_reg_valid & _mem_reg_valid_T; // @[FPU.scala:767:29, :790:{33,36}]
wire _mem_reg_valid_T_2 = _mem_reg_valid_T_1; // @[FPU.scala:790:{33,43}]
reg [31:0] mem_reg_inst; // @[FPU.scala:791:31]
wire _wb_reg_valid_T = ~killm; // @[FPU.scala:785:41, :792:48]
wire _wb_reg_valid_T_1 = _wb_reg_valid_T; // @[FPU.scala:792:{48,55}]
wire _wb_reg_valid_T_2 = mem_reg_valid & _wb_reg_valid_T_1; // @[FPU.scala:784:30, :792:{44,55}]
reg wb_reg_valid; // @[FPU.scala:792:29]
wire _io_sboard_set_T_1 = wb_reg_valid; // @[FPU.scala:792:29, :1006:33]
wire sfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire [1:0] sfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] fpiu_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] dfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] hfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] sfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] fpiu_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] dfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] hfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
reg mem_ctrl_ldst; // @[FPU.scala:801:27]
reg mem_ctrl_wen; // @[FPU.scala:801:27]
reg mem_ctrl_ren1; // @[FPU.scala:801:27]
reg mem_ctrl_ren2; // @[FPU.scala:801:27]
reg mem_ctrl_ren3; // @[FPU.scala:801:27]
reg mem_ctrl_swap12; // @[FPU.scala:801:27]
reg mem_ctrl_swap23; // @[FPU.scala:801:27]
reg [1:0] mem_ctrl_typeTagIn; // @[FPU.scala:801:27]
reg [1:0] mem_ctrl_typeTagOut; // @[FPU.scala:801:27]
reg mem_ctrl_fromint; // @[FPU.scala:801:27]
wire _memLatencyMask_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :926:23]
wire _wbInfo_0_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
wire _wbInfo_1_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
wire _wbInfo_2_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
reg mem_ctrl_toint; // @[FPU.scala:801:27]
reg mem_ctrl_fastpipe; // @[FPU.scala:801:27]
wire _memLatencyMask_T = mem_ctrl_fastpipe; // @[FPU.scala:801:27, :926:23]
reg mem_ctrl_fma; // @[FPU.scala:801:27]
reg mem_ctrl_div; // @[FPU.scala:801:27]
reg mem_ctrl_sqrt; // @[FPU.scala:801:27]
reg mem_ctrl_wflags; // @[FPU.scala:801:27]
reg mem_ctrl_vec; // @[FPU.scala:801:27]
reg wb_ctrl_ldst; // @[FPU.scala:802:26]
reg wb_ctrl_wen; // @[FPU.scala:802:26]
reg wb_ctrl_ren1; // @[FPU.scala:802:26]
reg wb_ctrl_ren2; // @[FPU.scala:802:26]
reg wb_ctrl_ren3; // @[FPU.scala:802:26]
reg wb_ctrl_swap12; // @[FPU.scala:802:26]
reg wb_ctrl_swap23; // @[FPU.scala:802:26]
reg [1:0] wb_ctrl_typeTagIn; // @[FPU.scala:802:26]
reg [1:0] wb_ctrl_typeTagOut; // @[FPU.scala:802:26]
reg wb_ctrl_fromint; // @[FPU.scala:802:26]
reg wb_ctrl_toint; // @[FPU.scala:802:26]
reg wb_ctrl_fastpipe; // @[FPU.scala:802:26]
reg wb_ctrl_fma; // @[FPU.scala:802:26]
reg wb_ctrl_div; // @[FPU.scala:802:26]
reg wb_ctrl_sqrt; // @[FPU.scala:802:26]
reg wb_ctrl_wflags; // @[FPU.scala:802:26]
reg wb_ctrl_vec; // @[FPU.scala:802:26]
wire [31:0] _frfWriteBundle_0_timer_T; // @[FPU.scala:810:23]
wire [63:0] _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10]
wire [63:0] frfWriteBundle_0_hartid; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_0_timer; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_wrdata; // @[FPU.scala:805:44]
wire [31:0] _frfWriteBundle_1_timer_T; // @[FPU.scala:810:23]
wire [63:0] _frfWriteBundle_1_wrdata_T_5; // @[FPU.scala:446:10]
wire [63:0] frfWriteBundle_1_hartid; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_1_timer; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_wrdst; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_wrdata; // @[FPU.scala:805:44]
wire frfWriteBundle_1_wrenf; // @[FPU.scala:805:44]
wire [63:0] _GEN = {61'h0, io_hartid_0}; // @[FPU.scala:735:7, :809:14]
assign frfWriteBundle_0_hartid = _GEN; // @[FPU.scala:805:44, :809:14]
assign frfWriteBundle_1_hartid = _GEN; // @[FPU.scala:805:44, :809:14]
assign _frfWriteBundle_0_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23]
assign _frfWriteBundle_1_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23]
assign frfWriteBundle_0_timer = _frfWriteBundle_0_timer_T; // @[FPU.scala:805:44, :810:23]
assign frfWriteBundle_1_timer = _frfWriteBundle_1_timer_T; // @[FPU.scala:805:44, :810:23]
wire _wdata_T = load_wb_typeTag == 2'h1; // @[package.scala:39:86]
wire [63:0] _wdata_T_1 = _wdata_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}]
wire _wdata_T_2 = load_wb_typeTag == 2'h2; // @[package.scala:39:86]
wire [63:0] _wdata_T_3 = _wdata_T_2 ? 64'h0 : _wdata_T_1; // @[package.scala:39:{76,86}]
wire _wdata_T_4 = &load_wb_typeTag; // @[package.scala:39:86]
wire [63:0] _wdata_T_5 = _wdata_T_4 ? 64'h0 : _wdata_T_3; // @[package.scala:39:{76,86}]
wire [63:0] _wdata_T_6 = _wdata_T_5 | load_wb_data; // @[package.scala:39:76]
wire wdata_rawIn_sign = _wdata_T_6[63]; // @[FPU.scala:431:23]
wire wdata_rawIn_sign_0 = wdata_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [10:0] wdata_rawIn_expIn = _wdata_T_6[62:52]; // @[FPU.scala:431:23]
wire [51:0] wdata_rawIn_fractIn = _wdata_T_6[51:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn = wdata_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn = wdata_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T = wdata_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_1 = wdata_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_2 = wdata_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_3 = wdata_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_4 = wdata_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_5 = wdata_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_6 = wdata_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_7 = wdata_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_8 = wdata_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_9 = wdata_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_10 = wdata_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_11 = wdata_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_12 = wdata_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_13 = wdata_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_14 = wdata_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_15 = wdata_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_16 = wdata_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_17 = wdata_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_18 = wdata_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_19 = wdata_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_20 = wdata_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_21 = wdata_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_22 = wdata_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_23 = wdata_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_24 = wdata_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_25 = wdata_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_26 = wdata_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_27 = wdata_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_28 = wdata_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_29 = wdata_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_30 = wdata_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_31 = wdata_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_32 = wdata_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_33 = wdata_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_34 = wdata_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_35 = wdata_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_36 = wdata_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_37 = wdata_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_38 = wdata_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_39 = wdata_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_40 = wdata_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_41 = wdata_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_42 = wdata_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_43 = wdata_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_44 = wdata_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_45 = wdata_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_46 = wdata_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_47 = wdata_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_48 = wdata_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_49 = wdata_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_50 = wdata_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_51 = wdata_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21]
wire [5:0] _wdata_rawIn_normDist_T_52 = {5'h19, ~_wdata_rawIn_normDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_53 = _wdata_rawIn_normDist_T_2 ? 6'h31 : _wdata_rawIn_normDist_T_52; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_54 = _wdata_rawIn_normDist_T_3 ? 6'h30 : _wdata_rawIn_normDist_T_53; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_55 = _wdata_rawIn_normDist_T_4 ? 6'h2F : _wdata_rawIn_normDist_T_54; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_56 = _wdata_rawIn_normDist_T_5 ? 6'h2E : _wdata_rawIn_normDist_T_55; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_57 = _wdata_rawIn_normDist_T_6 ? 6'h2D : _wdata_rawIn_normDist_T_56; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_58 = _wdata_rawIn_normDist_T_7 ? 6'h2C : _wdata_rawIn_normDist_T_57; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_59 = _wdata_rawIn_normDist_T_8 ? 6'h2B : _wdata_rawIn_normDist_T_58; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_60 = _wdata_rawIn_normDist_T_9 ? 6'h2A : _wdata_rawIn_normDist_T_59; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_61 = _wdata_rawIn_normDist_T_10 ? 6'h29 : _wdata_rawIn_normDist_T_60; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_62 = _wdata_rawIn_normDist_T_11 ? 6'h28 : _wdata_rawIn_normDist_T_61; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_63 = _wdata_rawIn_normDist_T_12 ? 6'h27 : _wdata_rawIn_normDist_T_62; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_64 = _wdata_rawIn_normDist_T_13 ? 6'h26 : _wdata_rawIn_normDist_T_63; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_65 = _wdata_rawIn_normDist_T_14 ? 6'h25 : _wdata_rawIn_normDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_66 = _wdata_rawIn_normDist_T_15 ? 6'h24 : _wdata_rawIn_normDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_67 = _wdata_rawIn_normDist_T_16 ? 6'h23 : _wdata_rawIn_normDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_68 = _wdata_rawIn_normDist_T_17 ? 6'h22 : _wdata_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_69 = _wdata_rawIn_normDist_T_18 ? 6'h21 : _wdata_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_70 = _wdata_rawIn_normDist_T_19 ? 6'h20 : _wdata_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_71 = _wdata_rawIn_normDist_T_20 ? 6'h1F : _wdata_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_72 = _wdata_rawIn_normDist_T_21 ? 6'h1E : _wdata_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_73 = _wdata_rawIn_normDist_T_22 ? 6'h1D : _wdata_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_74 = _wdata_rawIn_normDist_T_23 ? 6'h1C : _wdata_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_75 = _wdata_rawIn_normDist_T_24 ? 6'h1B : _wdata_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_76 = _wdata_rawIn_normDist_T_25 ? 6'h1A : _wdata_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_77 = _wdata_rawIn_normDist_T_26 ? 6'h19 : _wdata_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_78 = _wdata_rawIn_normDist_T_27 ? 6'h18 : _wdata_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_79 = _wdata_rawIn_normDist_T_28 ? 6'h17 : _wdata_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_80 = _wdata_rawIn_normDist_T_29 ? 6'h16 : _wdata_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_81 = _wdata_rawIn_normDist_T_30 ? 6'h15 : _wdata_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_82 = _wdata_rawIn_normDist_T_31 ? 6'h14 : _wdata_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_83 = _wdata_rawIn_normDist_T_32 ? 6'h13 : _wdata_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_84 = _wdata_rawIn_normDist_T_33 ? 6'h12 : _wdata_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_85 = _wdata_rawIn_normDist_T_34 ? 6'h11 : _wdata_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_86 = _wdata_rawIn_normDist_T_35 ? 6'h10 : _wdata_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_87 = _wdata_rawIn_normDist_T_36 ? 6'hF : _wdata_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_88 = _wdata_rawIn_normDist_T_37 ? 6'hE : _wdata_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_89 = _wdata_rawIn_normDist_T_38 ? 6'hD : _wdata_rawIn_normDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_90 = _wdata_rawIn_normDist_T_39 ? 6'hC : _wdata_rawIn_normDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_91 = _wdata_rawIn_normDist_T_40 ? 6'hB : _wdata_rawIn_normDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_92 = _wdata_rawIn_normDist_T_41 ? 6'hA : _wdata_rawIn_normDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_93 = _wdata_rawIn_normDist_T_42 ? 6'h9 : _wdata_rawIn_normDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_94 = _wdata_rawIn_normDist_T_43 ? 6'h8 : _wdata_rawIn_normDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_95 = _wdata_rawIn_normDist_T_44 ? 6'h7 : _wdata_rawIn_normDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_96 = _wdata_rawIn_normDist_T_45 ? 6'h6 : _wdata_rawIn_normDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_97 = _wdata_rawIn_normDist_T_46 ? 6'h5 : _wdata_rawIn_normDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_98 = _wdata_rawIn_normDist_T_47 ? 6'h4 : _wdata_rawIn_normDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_99 = _wdata_rawIn_normDist_T_48 ? 6'h3 : _wdata_rawIn_normDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_100 = _wdata_rawIn_normDist_T_49 ? 6'h2 : _wdata_rawIn_normDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_101 = _wdata_rawIn_normDist_T_50 ? 6'h1 : _wdata_rawIn_normDist_T_100; // @[Mux.scala:50:70]
wire [5:0] wdata_rawIn_normDist = _wdata_rawIn_normDist_T_51 ? 6'h0 : _wdata_rawIn_normDist_T_101; // @[Mux.scala:50:70]
wire [114:0] _wdata_rawIn_subnormFract_T = {63'h0, wdata_rawIn_fractIn} << wdata_rawIn_normDist; // @[Mux.scala:50:70]
wire [50:0] _wdata_rawIn_subnormFract_T_1 = _wdata_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [51:0] wdata_rawIn_subnormFract = {_wdata_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [11:0] _wdata_rawIn_adjustedExp_T = {6'h3F, ~wdata_rawIn_normDist}; // @[Mux.scala:50:70]
wire [11:0] _wdata_rawIn_adjustedExp_T_1 = wdata_rawIn_isZeroExpIn ? _wdata_rawIn_adjustedExp_T : {1'h0, wdata_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_2 = wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [10:0] _wdata_rawIn_adjustedExp_T_3 = {9'h100, _wdata_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [12:0] _wdata_rawIn_adjustedExp_T_4 = {1'h0, _wdata_rawIn_adjustedExp_T_1} + {2'h0, _wdata_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [11:0] wdata_rawIn_adjustedExp = _wdata_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9]
wire [11:0] _wdata_rawIn_out_sExp_T = wdata_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero = wdata_rawIn_isZeroExpIn & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_isZero_0 = wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T = wdata_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial = &_wdata_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_9 = wdata_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [12:0] _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [53:0] _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [12:0] wdata_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [53:0] wdata_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T = ~wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_1 = wdata_rawIn_isSpecial & _wdata_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_isNaN = _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T = wdata_rawIn_isSpecial & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_isInf = _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_1 = {1'h0, _wdata_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_sExp = _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T = ~wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_1 = {1'h0, _wdata_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [51:0] _wdata_rawIn_out_sig_T_2 = wdata_rawIn_isZeroExpIn ? wdata_rawIn_subnormFract : wdata_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_3 = {_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_sig = _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_7 = wdata_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_8 = wdata_rawIn_isZero_0 ? 3'h0 : _wdata_T_7; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_10 = {_wdata_T_8[2:1], _wdata_T_8[0] | _wdata_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_11 = {wdata_rawIn_sign_0, _wdata_T_10}; // @[recFNFromFN.scala:47:20, :48:76]
wire [8:0] _wdata_T_12 = wdata_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23]
wire [12:0] _wdata_T_13 = {_wdata_T_11, _wdata_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [51:0] _wdata_T_14 = wdata_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22]
wire [64:0] _wdata_T_15 = {_wdata_T_13, _wdata_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire wdata_rawIn_sign_1 = _wdata_T_6[31]; // @[FPU.scala:431:23]
wire wdata_rawIn_1_sign = wdata_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] wdata_rawIn_expIn_1 = _wdata_T_6[30:23]; // @[FPU.scala:431:23]
wire [22:0] wdata_rawIn_fractIn_1 = _wdata_T_6[22:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_1 = wdata_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn_1 = wdata_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T_102 = wdata_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_103 = wdata_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_104 = wdata_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_105 = wdata_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_106 = wdata_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_107 = wdata_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_108 = wdata_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_109 = wdata_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_110 = wdata_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_111 = wdata_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_112 = wdata_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_113 = wdata_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_114 = wdata_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_115 = wdata_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_116 = wdata_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_117 = wdata_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_118 = wdata_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_119 = wdata_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_120 = wdata_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_121 = wdata_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_122 = wdata_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_123 = wdata_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_124 = wdata_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _wdata_rawIn_normDist_T_125 = _wdata_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_126 = _wdata_rawIn_normDist_T_104 ? 5'h14 : _wdata_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_127 = _wdata_rawIn_normDist_T_105 ? 5'h13 : _wdata_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_128 = _wdata_rawIn_normDist_T_106 ? 5'h12 : _wdata_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_129 = _wdata_rawIn_normDist_T_107 ? 5'h11 : _wdata_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_130 = _wdata_rawIn_normDist_T_108 ? 5'h10 : _wdata_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_131 = _wdata_rawIn_normDist_T_109 ? 5'hF : _wdata_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_132 = _wdata_rawIn_normDist_T_110 ? 5'hE : _wdata_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_133 = _wdata_rawIn_normDist_T_111 ? 5'hD : _wdata_rawIn_normDist_T_132; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_134 = _wdata_rawIn_normDist_T_112 ? 5'hC : _wdata_rawIn_normDist_T_133; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_135 = _wdata_rawIn_normDist_T_113 ? 5'hB : _wdata_rawIn_normDist_T_134; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_136 = _wdata_rawIn_normDist_T_114 ? 5'hA : _wdata_rawIn_normDist_T_135; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_137 = _wdata_rawIn_normDist_T_115 ? 5'h9 : _wdata_rawIn_normDist_T_136; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_138 = _wdata_rawIn_normDist_T_116 ? 5'h8 : _wdata_rawIn_normDist_T_137; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_139 = _wdata_rawIn_normDist_T_117 ? 5'h7 : _wdata_rawIn_normDist_T_138; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_140 = _wdata_rawIn_normDist_T_118 ? 5'h6 : _wdata_rawIn_normDist_T_139; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_141 = _wdata_rawIn_normDist_T_119 ? 5'h5 : _wdata_rawIn_normDist_T_140; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_142 = _wdata_rawIn_normDist_T_120 ? 5'h4 : _wdata_rawIn_normDist_T_141; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_143 = _wdata_rawIn_normDist_T_121 ? 5'h3 : _wdata_rawIn_normDist_T_142; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_144 = _wdata_rawIn_normDist_T_122 ? 5'h2 : _wdata_rawIn_normDist_T_143; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_145 = _wdata_rawIn_normDist_T_123 ? 5'h1 : _wdata_rawIn_normDist_T_144; // @[Mux.scala:50:70]
wire [4:0] wdata_rawIn_normDist_1 = _wdata_rawIn_normDist_T_124 ? 5'h0 : _wdata_rawIn_normDist_T_145; // @[Mux.scala:50:70]
wire [53:0] _wdata_rawIn_subnormFract_T_2 = {31'h0, wdata_rawIn_fractIn_1} << wdata_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _wdata_rawIn_subnormFract_T_3 = _wdata_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] wdata_rawIn_subnormFract_1 = {_wdata_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _wdata_rawIn_adjustedExp_T_5 = {4'hF, ~wdata_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _wdata_rawIn_adjustedExp_T_6 = wdata_rawIn_isZeroExpIn_1 ? _wdata_rawIn_adjustedExp_T_5 : {1'h0, wdata_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_7 = wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _wdata_rawIn_adjustedExp_T_8 = {6'h20, _wdata_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _wdata_rawIn_adjustedExp_T_9 = {1'h0, _wdata_rawIn_adjustedExp_T_6} + {2'h0, _wdata_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] wdata_rawIn_adjustedExp_1 = _wdata_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _wdata_rawIn_out_sExp_T_2 = wdata_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero_1 = wdata_rawIn_isZeroExpIn_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_1_isZero = wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T_1 = wdata_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial_1 = &_wdata_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_18 = wdata_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] wdata_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] wdata_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T_2 = ~wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_3 = wdata_rawIn_isSpecial_1 & _wdata_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_1_isNaN = _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T_1 = wdata_rawIn_isSpecial_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_1_isInf = _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_3 = {1'h0, _wdata_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_1_sExp = _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T_4 = ~wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_5 = {1'h0, _wdata_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _wdata_rawIn_out_sig_T_6 = wdata_rawIn_isZeroExpIn_1 ? wdata_rawIn_subnormFract_1 : wdata_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_7 = {_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_1_sig = _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_16 = wdata_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_17 = wdata_rawIn_1_isZero ? 3'h0 : _wdata_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_19 = {_wdata_T_17[2:1], _wdata_T_17[0] | _wdata_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_20 = {wdata_rawIn_1_sign, _wdata_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _wdata_T_21 = wdata_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _wdata_T_22 = {_wdata_T_20, _wdata_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _wdata_T_23 = wdata_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] _wdata_T_24 = {_wdata_T_22, _wdata_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire wdata_rawIn_sign_2 = _wdata_T_6[15]; // @[FPU.scala:431:23]
wire wdata_rawIn_2_sign = wdata_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [4:0] wdata_rawIn_expIn_2 = _wdata_T_6[14:10]; // @[FPU.scala:431:23]
wire [9:0] wdata_rawIn_fractIn_2 = _wdata_T_6[9:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_2 = wdata_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn_2 = wdata_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T_146 = wdata_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_147 = wdata_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_148 = wdata_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_149 = wdata_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_150 = wdata_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_151 = wdata_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_152 = wdata_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_153 = wdata_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_154 = wdata_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_155 = wdata_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire [3:0] _wdata_rawIn_normDist_T_156 = {3'h4, ~_wdata_rawIn_normDist_T_147}; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_157 = _wdata_rawIn_normDist_T_148 ? 4'h7 : _wdata_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_158 = _wdata_rawIn_normDist_T_149 ? 4'h6 : _wdata_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_159 = _wdata_rawIn_normDist_T_150 ? 4'h5 : _wdata_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_160 = _wdata_rawIn_normDist_T_151 ? 4'h4 : _wdata_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_161 = _wdata_rawIn_normDist_T_152 ? 4'h3 : _wdata_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_162 = _wdata_rawIn_normDist_T_153 ? 4'h2 : _wdata_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_163 = _wdata_rawIn_normDist_T_154 ? 4'h1 : _wdata_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [3:0] wdata_rawIn_normDist_2 = _wdata_rawIn_normDist_T_155 ? 4'h0 : _wdata_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [24:0] _wdata_rawIn_subnormFract_T_4 = {15'h0, wdata_rawIn_fractIn_2} << wdata_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [8:0] _wdata_rawIn_subnormFract_T_5 = _wdata_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [9:0] wdata_rawIn_subnormFract_2 = {_wdata_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [5:0] _wdata_rawIn_adjustedExp_T_10 = {2'h3, ~wdata_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_adjustedExp_T_11 = wdata_rawIn_isZeroExpIn_2 ? _wdata_rawIn_adjustedExp_T_10 : {1'h0, wdata_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_12 = wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [4:0] _wdata_rawIn_adjustedExp_T_13 = {3'h4, _wdata_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [6:0] _wdata_rawIn_adjustedExp_T_14 = {1'h0, _wdata_rawIn_adjustedExp_T_11} + {2'h0, _wdata_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [5:0] wdata_rawIn_adjustedExp_2 = _wdata_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9]
wire [5:0] _wdata_rawIn_out_sExp_T_4 = wdata_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero_2 = wdata_rawIn_isZeroExpIn_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_2_isZero = wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T_2 = wdata_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial_2 = &_wdata_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_27 = wdata_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [6:0] _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [11:0] _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [6:0] wdata_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [11:0] wdata_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T_4 = ~wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_5 = wdata_rawIn_isSpecial_2 & _wdata_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_2_isNaN = _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T_2 = wdata_rawIn_isSpecial_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_2_isInf = _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_5 = {1'h0, _wdata_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_2_sExp = _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T_8 = ~wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_9 = {1'h0, _wdata_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [9:0] _wdata_rawIn_out_sig_T_10 = wdata_rawIn_isZeroExpIn_2 ? wdata_rawIn_subnormFract_2 : wdata_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_11 = {_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_2_sig = _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_25 = wdata_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_26 = wdata_rawIn_2_isZero ? 3'h0 : _wdata_T_25; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_28 = {_wdata_T_26[2:1], _wdata_T_26[0] | _wdata_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_29 = {wdata_rawIn_2_sign, _wdata_T_28}; // @[recFNFromFN.scala:47:20, :48:76]
wire [2:0] _wdata_T_30 = wdata_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23]
wire [6:0] _wdata_T_31 = {_wdata_T_29, _wdata_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [9:0] _wdata_T_32 = wdata_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22]
wire [16:0] _wdata_T_33 = {_wdata_T_31, _wdata_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [3:0] _wdata_swizzledNaN_T = _wdata_T_24[32:29]; // @[FPU.scala:337:8]
wire [6:0] _wdata_swizzledNaN_T_1 = _wdata_T_24[22:16]; // @[FPU.scala:338:8]
wire [6:0] _wdata_swizzledNaN_T_5 = _wdata_T_24[22:16]; // @[FPU.scala:338:8, :341:8]
wire _wdata_swizzledNaN_T_2 = &_wdata_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}]
wire [3:0] _wdata_swizzledNaN_T_3 = _wdata_T_24[27:24]; // @[FPU.scala:339:8]
wire _wdata_swizzledNaN_T_4 = _wdata_T_33[15]; // @[FPU.scala:340:8]
wire _wdata_swizzledNaN_T_6 = _wdata_T_33[16]; // @[FPU.scala:342:8]
wire [14:0] _wdata_swizzledNaN_T_7 = _wdata_T_33[14:0]; // @[FPU.scala:343:8]
wire [7:0] wdata_swizzledNaN_lo_hi = {_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [22:0] wdata_swizzledNaN_lo = {wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [4:0] wdata_swizzledNaN_hi_lo = {_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] wdata_swizzledNaN_hi_hi = {_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [9:0] wdata_swizzledNaN_hi = {wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_swizzledNaN = {wdata_swizzledNaN_hi, wdata_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [2:0] _wdata_T_34 = _wdata_T_24[31:29]; // @[FPU.scala:249:25]
wire _wdata_T_35 = &_wdata_T_34; // @[FPU.scala:249:{25,56}]
wire [32:0] _wdata_T_36 = _wdata_T_35 ? wdata_swizzledNaN : _wdata_T_24; // @[FPU.scala:249:56, :336:26, :344:8]
wire [3:0] _wdata_swizzledNaN_T_8 = _wdata_T_15[64:61]; // @[FPU.scala:337:8]
wire [19:0] _wdata_swizzledNaN_T_9 = _wdata_T_15[51:32]; // @[FPU.scala:338:8]
wire [19:0] _wdata_swizzledNaN_T_13 = _wdata_T_15[51:32]; // @[FPU.scala:338:8, :341:8]
wire _wdata_swizzledNaN_T_10 = &_wdata_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}]
wire [6:0] _wdata_swizzledNaN_T_11 = _wdata_T_15[59:53]; // @[FPU.scala:339:8]
wire _wdata_swizzledNaN_T_12 = _wdata_T_36[31]; // @[FPU.scala:340:8, :344:8]
wire _wdata_swizzledNaN_T_14 = _wdata_T_36[32]; // @[FPU.scala:342:8, :344:8]
wire [30:0] _wdata_swizzledNaN_T_15 = _wdata_T_36[30:0]; // @[FPU.scala:343:8, :344:8]
wire [20:0] wdata_swizzledNaN_lo_hi_1 = {_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [51:0] wdata_swizzledNaN_lo_1 = {wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8]
wire [7:0] wdata_swizzledNaN_hi_lo_1 = {_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] wdata_swizzledNaN_hi_hi_1 = {_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [12:0] wdata_swizzledNaN_hi_1 = {wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_swizzledNaN_1 = {wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [2:0] _wdata_T_37 = _wdata_T_15[63:61]; // @[FPU.scala:249:25]
wire _wdata_T_38 = &_wdata_T_37; // @[FPU.scala:249:{25,56}]
wire [64:0] wdata = _wdata_T_38 ? wdata_swizzledNaN_1 : _wdata_T_15; // @[FPU.scala:249:56, :336:26, :344:8]
wire _unswizzled_T = wdata[31]; // @[FPU.scala:344:8, :381:10]
wire _frfWriteBundle_0_wrdata_prevRecoded_T = wdata[31]; // @[FPU.scala:344:8, :381:10, :442:10]
wire _unswizzled_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10]
wire _frfWriteBundle_0_wrdata_prevRecoded_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10, :443:10]
wire [30:0] _unswizzled_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10]
wire [30:0] _frfWriteBundle_0_wrdata_prevRecoded_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10, :444:10]
wire [1:0] unswizzled_hi = {_unswizzled_T, _unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [32:0] unswizzled = {unswizzled_hi, _unswizzled_T_2}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_T = wdata[64:60]; // @[FPU.scala:332:49, :344:8]
wire _prevOK_T_1 = &_prevOK_T; // @[FPU.scala:332:{49,84}]
wire _prevOK_T_2 = ~_prevOK_T_1; // @[FPU.scala:332:84, :384:20]
wire _prevOK_unswizzled_T = unswizzled[15]; // @[FPU.scala:380:27, :381:10]
wire _prevOK_unswizzled_T_1 = unswizzled[23]; // @[FPU.scala:380:27, :382:10]
wire [14:0] _prevOK_unswizzled_T_2 = unswizzled[14:0]; // @[FPU.scala:380:27, :383:10]
wire [1:0] prevOK_unswizzled_hi = {_prevOK_unswizzled_T, _prevOK_unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [16:0] prevOK_unswizzled = {prevOK_unswizzled_hi, _prevOK_unswizzled_T_2}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_prevOK_T = unswizzled[32:28]; // @[FPU.scala:332:49, :380:27]
wire _prevOK_prevOK_T_1 = &_prevOK_prevOK_T; // @[FPU.scala:332:{49,84}]
wire _prevOK_prevOK_T_2 = ~_prevOK_prevOK_T_1; // @[FPU.scala:332:84, :384:20]
wire [2:0] _prevOK_curOK_T = unswizzled[31:29]; // @[FPU.scala:249:25, :380:27]
wire _prevOK_curOK_T_1 = &_prevOK_curOK_T; // @[FPU.scala:249:{25,56}]
wire _prevOK_curOK_T_2 = ~_prevOK_curOK_T_1; // @[FPU.scala:249:56, :385:19]
wire _prevOK_curOK_T_3 = unswizzled[28]; // @[FPU.scala:380:27, :385:35]
wire [6:0] _prevOK_curOK_T_4 = unswizzled[22:16]; // @[FPU.scala:380:27, :385:60]
wire _prevOK_curOK_T_5 = &_prevOK_curOK_T_4; // @[FPU.scala:385:{60,96}]
wire _prevOK_curOK_T_6 = _prevOK_curOK_T_3 == _prevOK_curOK_T_5; // @[FPU.scala:385:{35,55,96}]
wire prevOK_curOK = _prevOK_curOK_T_2 | _prevOK_curOK_T_6; // @[FPU.scala:385:{19,31,55}]
wire _prevOK_T_3 = prevOK_curOK; // @[FPU.scala:385:31, :386:14]
wire prevOK = _prevOK_T_2 | _prevOK_T_3; // @[FPU.scala:384:{20,33}, :386:14]
wire [2:0] _curOK_T = wdata[63:61]; // @[FPU.scala:249:25, :344:8]
wire [2:0] _frfWriteBundle_0_wrdata_T_1 = wdata[63:61]; // @[FPU.scala:249:25, :344:8]
wire _curOK_T_1 = &_curOK_T; // @[FPU.scala:249:{25,56}]
wire _curOK_T_2 = ~_curOK_T_1; // @[FPU.scala:249:56, :385:19]
wire _curOK_T_3 = wdata[60]; // @[FPU.scala:344:8, :385:35]
wire [19:0] _curOK_T_4 = wdata[51:32]; // @[FPU.scala:344:8, :385:60]
wire _curOK_T_5 = &_curOK_T_4; // @[FPU.scala:385:{60,96}]
wire _curOK_T_6 = _curOK_T_3 == _curOK_T_5; // @[FPU.scala:385:{35,55,96}]
wire curOK = _curOK_T_2 | _curOK_T_6; // @[FPU.scala:385:{19,31,55}]
wire [11:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = wdata[63:52]; // @[FPU.scala:344:8]
wire [2:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = wdata[64]; // @[FPU.scala:344:8]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = wdata[51:0]; // @[FPU.scala:344:8]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] frfWriteBundle_0_wrdata_unrecoded_denormFract = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? 11'h0 : _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = {11{_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] frfWriteBundle_0_wrdata_unrecoded_expOut = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf ? 52'h0 : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] frfWriteBundle_0_wrdata_unrecoded_fractOut = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_unrecoded_denormFract : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] frfWriteBundle_0_wrdata_unrecoded_hi = {frfWriteBundle_0_wrdata_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] frfWriteBundle_0_wrdata_unrecoded = {frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] frfWriteBundle_0_wrdata_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] frfWriteBundle_0_wrdata_prevRecoded = {frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevRecoded[31:23]; // @[FPU.scala:441:28]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevRecoded[32]; // @[FPU.scala:441:28]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevRecoded[22:0]; // @[FPU.scala:441:28]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = {8{_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = frfWriteBundle_0_wrdata_prevRecoded[15]; // @[FPU.scala:441:28, :442:10]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = frfWriteBundle_0_wrdata_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = &_frfWriteBundle_0_wrdata_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded : _frfWriteBundle_0_wrdata_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded = {_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _frfWriteBundle_0_wrdata_T = frfWriteBundle_0_wrdata_unrecoded[63:32]; // @[FPU.scala:446:21]
wire _frfWriteBundle_0_wrdata_T_2 = &_frfWriteBundle_0_wrdata_T_1; // @[FPU.scala:249:{25,56}]
wire [31:0] _frfWriteBundle_0_wrdata_T_3 = frfWriteBundle_0_wrdata_unrecoded[31:0]; // @[FPU.scala:446:81]
wire [31:0] _frfWriteBundle_0_wrdata_T_4 = _frfWriteBundle_0_wrdata_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded : _frfWriteBundle_0_wrdata_T_3; // @[FPU.scala:249:56, :446:{10,44,81}]
assign _frfWriteBundle_0_wrdata_T_5 = {_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4}; // @[FPU.scala:446:{10,21,44}]
assign frfWriteBundle_0_wrdata = _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10, :805:44]
wire [4:0] _ex_rs_T_1 = _ex_rs_T; // @[FPU.scala:832:37]
wire [4:0] _ex_rs_T_3 = _ex_rs_T_2; // @[FPU.scala:832:37]
wire [4:0] _ex_rs_T_5 = _ex_rs_T_4; // @[FPU.scala:832:37]
wire [4:0] _ex_ra_0_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51]
wire [4:0] _ex_ra_1_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51, :836:50]
wire [4:0] _ex_ra_0_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50]
wire [4:0] _ex_ra_2_T = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :840:50]
wire [4:0] _ex_ra_1_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :841:70]
wire [4:0] _ex_ra_2_T_1 = io_inst_0[31:27]; // @[FPU.scala:735:7, :843:46]
wire [2:0] _ex_rm_T = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:30]
wire [2:0] _ex_rm_T_2 = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:{30,70}]
wire _ex_rm_T_1 = &_ex_rm_T; // @[FPU.scala:845:{30,38}]
wire [2:0] ex_rm = _ex_rm_T_1 ? io_fcsr_rm_0 : _ex_rm_T_2; // @[FPU.scala:735:7, :845:{18,38,70}]
wire [2:0] sfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] fpiu_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] dfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] hfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire _GEN_0 = req_valid & ex_ctrl_fma; // @[FPU.scala:780:32, :800:20, :873:33]
wire _sfma_io_in_valid_T; // @[FPU.scala:873:33]
assign _sfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33]
wire _dfma_io_in_valid_T; // @[FPU.scala:914:41]
assign _dfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :914:41]
wire _hfma_io_in_valid_T; // @[FPU.scala:920:41]
assign _hfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :920:41]
wire _GEN_1 = ex_ctrl_typeTagOut == 2'h1; // @[FPU.scala:800:20, :873:70]
wire _sfma_io_in_valid_T_1; // @[FPU.scala:873:70]
assign _sfma_io_in_valid_T_1 = _GEN_1; // @[FPU.scala:873:70]
wire _write_port_busy_T_2; // @[FPU.scala:911:72]
assign _write_port_busy_T_2 = _GEN_1; // @[FPU.scala:873:70, :911:72]
wire _write_port_busy_T_20; // @[FPU.scala:911:72]
assign _write_port_busy_T_20 = _GEN_1; // @[FPU.scala:873:70, :911:72]
wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[FPU.scala:873:{33,48,70}]
wire [1:0] _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [1:0] _sfma_io_in_bits_req_typ_T; // @[FPU.scala:855:27]
wire [1:0] _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:856:27]
wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] sfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] sfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in1_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in1_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in1_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in1_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in1_prev_prev_0_1 = sfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in1_oks_1 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox & sfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in1_floats_2 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_1 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in2_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in2_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in2_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in2_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in2_prev_prev_0_1 = sfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in2_oks_1 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox & sfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in2_floats_2 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_1 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :853:13]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in3_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in3_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in3_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in3_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in3_prev_prev_0_1 = sfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in3_oks_1 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox & sfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in3_floats_2 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_1 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in3 = {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :854:13]
assign _sfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _fpiu_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _dfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _hfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign _sfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _fpiu_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _dfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _hfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire [1:0] _sfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _dfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _hfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire _sfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _sfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _fpiu_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _dfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _hfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _sfma_io_in_bits_req_fmaCmd_T_3 = _sfma_io_in_bits_req_fmaCmd_T_1 & _sfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _sfma_io_in_bits_req_fmaCmd_T_4 = {_sfma_io_in_bits_req_fmaCmd_T[1], _sfma_io_in_bits_req_fmaCmd_T[0] | _sfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign sfma_io_in_bits_req_fmaCmd = _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _fpiu_io_in_valid_T = ex_ctrl_toint | ex_ctrl_div; // @[FPU.scala:800:20, :877:51]
wire _fpiu_io_in_valid_T_1 = _fpiu_io_in_valid_T | ex_ctrl_sqrt; // @[FPU.scala:800:20, :877:{51,66}]
wire _fpiu_io_in_valid_T_2 = ex_ctrl_fastpipe & ex_ctrl_wflags; // @[FPU.scala:800:20, :877:103]
wire _fpiu_io_in_valid_T_3 = _fpiu_io_in_valid_T_1 | _fpiu_io_in_valid_T_2; // @[FPU.scala:877:{66,82,103}]
wire _fpiu_io_in_valid_T_4 = req_valid & _fpiu_io_in_valid_T_3; // @[FPU.scala:780:32, :877:{33,82}]
wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [64:0] _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10]
wire [64:0] _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10]
wire [64:0] _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10]
wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in1_prev_prev_0_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in1_floats_1 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in1_oks_1 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox & fpiu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _GEN_2 = ex_ctrl_typeTagIn == 2'h1; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T ? fpiu_io_in_bits_req_in1_oks_1 : fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}]
wire _GEN_3 = ex_ctrl_typeTagIn == 2'h2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 | _fpiu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in1_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_5 = _fpiu_io_in_bits_req_in1_T_4 | _fpiu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in1_T_7 = _fpiu_io_in_bits_req_in1_T_6 ? fpiu_io_in_bits_req_in1_floats_1 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in1_T_9 = _fpiu_io_in_bits_req_in1_T_8 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in1_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in1_T_11 = _fpiu_io_in_bits_req_in1_T_10 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in1_T_12 = _fpiu_io_in_bits_req_in1_T_5 ? _fpiu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10, :848:19]
wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in2_prev_prev_0_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in2_floats_1 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in2_oks_1 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox & fpiu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T ? fpiu_io_in_bits_req_in2_oks_1 : fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 | _fpiu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_5 = _fpiu_io_in_bits_req_in2_T_4 | _fpiu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in2_T_7 = _fpiu_io_in_bits_req_in2_T_6 ? fpiu_io_in_bits_req_in2_floats_1 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in2_T_9 = _fpiu_io_in_bits_req_in2_T_8 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in2_T_11 = _fpiu_io_in_bits_req_in2_T_10 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in2_T_12 = _fpiu_io_in_bits_req_in2_T_5 ? _fpiu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10, :848:19]
wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in3_prev_prev_0_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in3_floats_1 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in3_oks_1 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox & fpiu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T ? fpiu_io_in_bits_req_in3_oks_1 : fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 | _fpiu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_5 = _fpiu_io_in_bits_req_in3_T_4 | _fpiu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in3_T_7 = _fpiu_io_in_bits_req_in3_T_6 ? fpiu_io_in_bits_req_in3_floats_1 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in3_T_9 = _fpiu_io_in_bits_req_in3_T_8 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in3_T_11 = _fpiu_io_in_bits_req_in3_T_10 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in3_T_12 = _fpiu_io_in_bits_req_in3_T_5 ? _fpiu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in3 = _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10, :848:19]
assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _fpiu_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _fpiu_io_in_bits_req_fmaCmd_T_3 = _fpiu_io_in_bits_req_fmaCmd_T_1 & _fpiu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _fpiu_io_in_bits_req_fmaCmd_T_4 = {_fpiu_io_in_bits_req_fmaCmd_T[1], _fpiu_io_in_bits_req_fmaCmd_T[0] | _fpiu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign fpiu_io_in_bits_req_fmaCmd = _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _ifpu_io_in_valid_T = req_valid & ex_ctrl_fromint; // @[FPU.scala:780:32, :800:20, :887:33]
wire [64:0] _ifpu_io_in_bits_in1_T = {1'h0, io_fromint_data_0}; // @[FPU.scala:735:7, :889:29]
wire _fpmu_io_in_valid_T = req_valid & ex_ctrl_fastpipe; // @[FPU.scala:780:32, :800:20, :892:33]
wire divSqrt_wen; // @[FPU.scala:896:32]
wire divSqrt_inFlight; // @[FPU.scala:897:37]
reg [4:0] divSqrt_waddr; // @[FPU.scala:898:26]
reg divSqrt_cp; // @[FPU.scala:899:23]
wire [1:0] divSqrt_typeTag; // @[FPU.scala:900:29]
wire [64:0] divSqrt_wdata; // @[FPU.scala:901:27]
wire [4:0] divSqrt_flags; // @[FPU.scala:902:27]
wire _GEN_4 = ex_ctrl_typeTagOut == 2'h2; // @[FPU.scala:800:20, :914:78]
wire _dfma_io_in_valid_T_1; // @[FPU.scala:914:78]
assign _dfma_io_in_valid_T_1 = _GEN_4; // @[FPU.scala:914:78]
wire _write_port_busy_T_5; // @[FPU.scala:916:78]
assign _write_port_busy_T_5 = _GEN_4; // @[FPU.scala:914:78, :916:78]
wire _write_port_busy_T_23; // @[FPU.scala:916:78]
assign _write_port_busy_T_23 = _GEN_4; // @[FPU.scala:914:78, :916:78]
wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[FPU.scala:914:{41,56,78}]
wire [1:0] _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [64:0] _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26]
wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in1_prev_prev_0_1 = dfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in1_floats_1 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in1_oks_1 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox & dfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26, :848:19]
wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in2_prev_prev_0_1 = dfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in2_floats_1 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in2_oks_1 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox & dfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26, :848:19]
wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in3_prev_prev_0_1 = dfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in3_floats_1 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in3_oks_1 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox & dfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in3 = _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26, :848:19]
assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _dfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _dfma_io_in_bits_req_fmaCmd_T_3 = _dfma_io_in_bits_req_fmaCmd_T_1 & _dfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _dfma_io_in_bits_req_fmaCmd_T_4 = {_dfma_io_in_bits_req_fmaCmd_T[1], _dfma_io_in_bits_req_fmaCmd_T[0] | _dfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign dfma_io_in_bits_req_fmaCmd = _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _GEN_5 = ex_ctrl_typeTagOut == 2'h0; // @[FPU.scala:800:20, :920:78]
wire _hfma_io_in_valid_T_1; // @[FPU.scala:920:78]
assign _hfma_io_in_valid_T_1 = _GEN_5; // @[FPU.scala:920:78]
wire _write_port_busy_T_8; // @[FPU.scala:922:78]
assign _write_port_busy_T_8 = _GEN_5; // @[FPU.scala:920:78, :922:78]
wire _write_port_busy_T_26; // @[FPU.scala:922:78]
assign _write_port_busy_T_26 = _GEN_5; // @[FPU.scala:920:78, :922:78]
wire _hfma_io_in_valid_T_2 = _hfma_io_in_valid_T & _hfma_io_in_valid_T_1; // @[FPU.scala:920:{41,56,78}]
wire [1:0] _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [1:0] hfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_in1_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in1_prev_unswizzled = {hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in1_floats_0 = {hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in1_prev_prev_0_1 = hfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in1_prev_prev_sign = hfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in1_prev_prev_fractIn = hfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expIn = hfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = {hfma_io_in_bits_req_in1_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in1_prev_prev_fractOut = _hfma_io_in_bits_req_in1_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = hfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in1_prev_prev_expOut_T | _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in1_prev_prev_expOut = _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in1_prev_prev_hi = {hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in1_floats_1 = {hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in1_prev_isbox = &_hfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in1_oks_1 = hfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in1_oks_0 = hfma_io_in_bits_req_in1_prev_isbox & hfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in1_fractOut_T = {hfma_io_in_bits_req_in1_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in1_fractOut = _hfma_io_in_bits_req_in1_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in1_expOut_expCode = hfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in1_expOut_commonCase = _hfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in1_expOut_T = hfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in1_expOut_T_1 = hfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in1_expOut_T_2 = _hfma_io_in_bits_req_in1_expOut_T | _hfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in1_expOut_T_3 = hfma_io_in_bits_req_in1_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_4 = {hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_5 = hfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in1_expOut = _hfma_io_in_bits_req_in1_expOut_T_2 ? _hfma_io_in_bits_req_in1_expOut_T_4 : _hfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in1_hi = {hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in1_floats_2 = {hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in1_T = hfma_io_in_bits_req_in1_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in1_T_1 = hfma_io_in_bits_req_in1_floats_0 | _hfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in1 = {48'h0, _hfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13]
wire [1:0] hfma_io_in_bits_req_in2_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in2_prev_unswizzled = {hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in2_floats_0 = {hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in2_prev_prev_0_1 = hfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in2_prev_prev_sign = hfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in2_prev_prev_fractIn = hfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expIn = hfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = {hfma_io_in_bits_req_in2_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in2_prev_prev_fractOut = _hfma_io_in_bits_req_in2_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = hfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in2_prev_prev_expOut_T | _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in2_prev_prev_expOut = _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in2_prev_prev_hi = {hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in2_floats_1 = {hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in2_prev_isbox = &_hfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in2_oks_1 = hfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in2_oks_0 = hfma_io_in_bits_req_in2_prev_isbox & hfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in2_fractOut_T = {hfma_io_in_bits_req_in2_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in2_fractOut = _hfma_io_in_bits_req_in2_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in2_expOut_expCode = hfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in2_expOut_commonCase = _hfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in2_expOut_T = hfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in2_expOut_T_1 = hfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in2_expOut_T_2 = _hfma_io_in_bits_req_in2_expOut_T | _hfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in2_expOut_T_3 = hfma_io_in_bits_req_in2_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_4 = {hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_5 = hfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in2_expOut = _hfma_io_in_bits_req_in2_expOut_T_2 ? _hfma_io_in_bits_req_in2_expOut_T_4 : _hfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in2_hi = {hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in2_floats_2 = {hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in2_T = hfma_io_in_bits_req_in2_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in2_T_1 = hfma_io_in_bits_req_in2_floats_0 | _hfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in2 = {48'h0, _hfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :853:13]
wire [1:0] hfma_io_in_bits_req_in3_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in3_prev_unswizzled = {hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in3_floats_0 = {hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in3_prev_prev_0_1 = hfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in3_prev_prev_sign = hfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in3_prev_prev_fractIn = hfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expIn = hfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = {hfma_io_in_bits_req_in3_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in3_prev_prev_fractOut = _hfma_io_in_bits_req_in3_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = hfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in3_prev_prev_expOut_T | _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in3_prev_prev_expOut = _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in3_prev_prev_hi = {hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in3_floats_1 = {hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in3_prev_isbox = &_hfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in3_oks_1 = hfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in3_oks_0 = hfma_io_in_bits_req_in3_prev_isbox & hfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in3_fractOut_T = {hfma_io_in_bits_req_in3_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in3_fractOut = _hfma_io_in_bits_req_in3_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in3_expOut_expCode = hfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in3_expOut_commonCase = _hfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in3_expOut_T = hfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in3_expOut_T_1 = hfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in3_expOut_T_2 = _hfma_io_in_bits_req_in3_expOut_T | _hfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in3_expOut_T_3 = hfma_io_in_bits_req_in3_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_4 = {hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_5 = hfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in3_expOut = _hfma_io_in_bits_req_in3_expOut_T_2 ? _hfma_io_in_bits_req_in3_expOut_T_4 : _hfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in3_hi = {hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in3_floats_2 = {hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in3_T = hfma_io_in_bits_req_in3_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in3_T_1 = hfma_io_in_bits_req_in3_floats_0 | _hfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in3 = {48'h0, _hfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :854:13]
assign hfma_io_in_bits_req_typ = _hfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign hfma_io_in_bits_req_fmt = _hfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _hfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _hfma_io_in_bits_req_fmaCmd_T_3 = _hfma_io_in_bits_req_fmaCmd_T_1 & _hfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _hfma_io_in_bits_req_fmaCmd_T_4 = {_hfma_io_in_bits_req_fmaCmd_T[1], _hfma_io_in_bits_req_fmaCmd_T[0] | _hfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign hfma_io_in_bits_req_fmaCmd = _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _GEN_6 = mem_ctrl_typeTagOut == 2'h1; // @[FPU.scala:801:27, :911:72]
wire _memLatencyMask_T_2; // @[FPU.scala:911:72]
assign _memLatencyMask_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_0_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_0_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_1_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_1_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_2_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_2_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _divSqrt_io_inValid_T_2; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T_2 = _GEN_6; // @[FPU.scala:911:72, :1028:52]
wire _memLatencyMask_T_3 = mem_ctrl_fma & _memLatencyMask_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _memLatencyMask_T_4 = {_memLatencyMask_T_3, 1'h0}; // @[FPU.scala:911:56, :926:23]
wire _GEN_7 = mem_ctrl_typeTagOut == 2'h2; // @[FPU.scala:801:27, :916:78]
wire _memLatencyMask_T_5; // @[FPU.scala:916:78]
assign _memLatencyMask_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_0_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_0_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_1_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_1_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_2_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_2_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _io_sboard_set_T_2; // @[FPU.scala:916:78]
assign _io_sboard_set_T_2 = _GEN_7; // @[FPU.scala:916:78]
wire _divSqrt_io_inValid_T_4; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T_4 = _GEN_7; // @[FPU.scala:916:78, :1028:52]
wire _memLatencyMask_T_6 = mem_ctrl_fma & _memLatencyMask_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [2:0] _memLatencyMask_T_7 = {_memLatencyMask_T_6, 2'h0}; // @[FPU.scala:916:62, :926:23]
wire _GEN_8 = mem_ctrl_typeTagOut == 2'h0; // @[FPU.scala:801:27, :922:78]
wire _memLatencyMask_T_8; // @[FPU.scala:922:78]
assign _memLatencyMask_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_0_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_0_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_1_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_1_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_2_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_2_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _divSqrt_io_inValid_T; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T = _GEN_8; // @[FPU.scala:922:78, :1028:52]
wire _memLatencyMask_T_9 = mem_ctrl_fma & _memLatencyMask_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [1:0] _memLatencyMask_T_10 = {_memLatencyMask_T_9, 1'h0}; // @[FPU.scala:922:62, :926:23]
wire _memLatencyMask_T_11 = _memLatencyMask_T | _memLatencyMask_T_1; // @[FPU.scala:926:{23,72}]
wire [1:0] _memLatencyMask_T_12 = {1'h0, _memLatencyMask_T_11} | _memLatencyMask_T_4; // @[FPU.scala:926:{23,72}]
wire [2:0] _memLatencyMask_T_13 = {1'h0, _memLatencyMask_T_12} | _memLatencyMask_T_7; // @[FPU.scala:926:{23,72}]
wire [2:0] memLatencyMask = {_memLatencyMask_T_13[2], _memLatencyMask_T_13[1:0] | _memLatencyMask_T_10}; // @[FPU.scala:926:{23,72}]
reg [2:0] wen; // @[FPU.scala:939:20]
reg [4:0] wbInfo_0_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_0_typeTag; // @[FPU.scala:940:19]
reg wbInfo_0_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_0_pipeid; // @[FPU.scala:940:19]
reg [4:0] wbInfo_1_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_1_typeTag; // @[FPU.scala:940:19]
reg wbInfo_1_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_1_pipeid; // @[FPU.scala:940:19]
reg [4:0] wbInfo_2_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_2_typeTag; // @[FPU.scala:940:19]
reg wbInfo_2_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_2_pipeid; // @[FPU.scala:940:19]
wire _mem_wen_T = mem_ctrl_fma | mem_ctrl_fastpipe; // @[FPU.scala:801:27, :941:48]
wire _mem_wen_T_1 = _mem_wen_T | mem_ctrl_fromint; // @[FPU.scala:801:27, :941:{48,69}]
wire mem_wen = mem_reg_valid & _mem_wen_T_1; // @[FPU.scala:784:30, :941:{31,69}]
wire [1:0] _write_port_busy_T = {ex_ctrl_fastpipe, 1'h0}; // @[FPU.scala:800:20, :926:23]
wire [1:0] _write_port_busy_T_1 = {ex_ctrl_fromint, 1'h0}; // @[FPU.scala:800:20, :926:23]
wire _write_port_busy_T_3 = ex_ctrl_fma & _write_port_busy_T_2; // @[FPU.scala:800:20, :911:{56,72}]
wire [2:0] _write_port_busy_T_4 = {_write_port_busy_T_3, 2'h0}; // @[FPU.scala:911:56, :926:23]
wire _write_port_busy_T_6 = ex_ctrl_fma & _write_port_busy_T_5; // @[FPU.scala:800:20, :916:{62,78}]
wire [3:0] _write_port_busy_T_7 = {_write_port_busy_T_6, 3'h0}; // @[FPU.scala:916:62, :926:23]
wire _write_port_busy_T_9 = ex_ctrl_fma & _write_port_busy_T_8; // @[FPU.scala:800:20, :922:{62,78}]
wire [2:0] _write_port_busy_T_10 = {_write_port_busy_T_9, 2'h0}; // @[FPU.scala:922:62, :926:23]
wire [1:0] _write_port_busy_T_11 = _write_port_busy_T | _write_port_busy_T_1; // @[FPU.scala:926:{23,72}]
wire [2:0] _write_port_busy_T_12 = {1'h0, _write_port_busy_T_11} | _write_port_busy_T_4; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_13 = {1'h0, _write_port_busy_T_12} | _write_port_busy_T_7; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_14 = {_write_port_busy_T_13[3], _write_port_busy_T_13[2:0] | _write_port_busy_T_10}; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_15 = {1'h0, _write_port_busy_T_14[2:0] & memLatencyMask}; // @[FPU.scala:926:72, :942:62]
wire _write_port_busy_T_16 = |_write_port_busy_T_15; // @[FPU.scala:942:{62,89}]
wire _write_port_busy_T_17 = mem_wen & _write_port_busy_T_16; // @[FPU.scala:941:31, :942:{43,89}]
wire [2:0] _write_port_busy_T_18 = {ex_ctrl_fastpipe, 2'h0}; // @[FPU.scala:800:20, :926:23]
wire [2:0] _write_port_busy_T_19 = {ex_ctrl_fromint, 2'h0}; // @[FPU.scala:800:20, :926:23]
wire _write_port_busy_T_21 = ex_ctrl_fma & _write_port_busy_T_20; // @[FPU.scala:800:20, :911:{56,72}]
wire [3:0] _write_port_busy_T_22 = {_write_port_busy_T_21, 3'h0}; // @[FPU.scala:911:56, :926:23]
wire _write_port_busy_T_24 = ex_ctrl_fma & _write_port_busy_T_23; // @[FPU.scala:800:20, :916:{62,78}]
wire [4:0] _write_port_busy_T_25 = {_write_port_busy_T_24, 4'h0}; // @[FPU.scala:916:62, :926:23]
wire _write_port_busy_T_27 = ex_ctrl_fma & _write_port_busy_T_26; // @[FPU.scala:800:20, :922:{62,78}]
wire [3:0] _write_port_busy_T_28 = {_write_port_busy_T_27, 3'h0}; // @[FPU.scala:922:62, :926:23]
wire [2:0] _write_port_busy_T_29 = _write_port_busy_T_18 | _write_port_busy_T_19; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_30 = {1'h0, _write_port_busy_T_29} | _write_port_busy_T_22; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_31 = {1'h0, _write_port_busy_T_30} | _write_port_busy_T_25; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_32 = {_write_port_busy_T_31[4], _write_port_busy_T_31[3:0] | _write_port_busy_T_28}; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_33 = {2'h0, _write_port_busy_T_32[2:0] & wen}; // @[FPU.scala:926:72, :939:20, :942:101]
wire _write_port_busy_T_34 = |_write_port_busy_T_33; // @[FPU.scala:942:{101,128}]
wire _write_port_busy_T_35 = _write_port_busy_T_17 | _write_port_busy_T_34; // @[FPU.scala:942:{43,93,128}]
reg write_port_busy; // @[FPU.scala:942:34]
wire [1:0] _wen_T = wen[2:1]; // @[FPU.scala:939:20, :948:14]
wire [1:0] _wen_T_1 = wen[2:1]; // @[FPU.scala:939:20, :948:14, :951:18]
wire [2:0] _wen_T_2 = {1'h0, _wen_T_1} | memLatencyMask; // @[FPU.scala:926:72, :951:{18,23}]
wire _wbInfo_0_pipeid_T_11 = _wbInfo_0_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_0_pipeid_T_3 = mem_ctrl_fma & _wbInfo_0_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_0_pipeid_T_4 = {_wbInfo_0_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_0_pipeid_T_6 = mem_ctrl_fma & _wbInfo_0_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_0_pipeid_T_7 = {2{_wbInfo_0_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_0_pipeid_T_9 = mem_ctrl_fma & _wbInfo_0_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_0_pipeid_T_10 = {_wbInfo_0_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_0_pipeid_T_12 = {1'h0, _wbInfo_0_pipeid_T_11} | _wbInfo_0_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_0_pipeid_T_13 = _wbInfo_0_pipeid_T_12 | _wbInfo_0_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_0_pipeid_T_14 = {1'h0, _wbInfo_0_pipeid_T_13} | _wbInfo_0_pipeid_T_10; // @[FPU.scala:928:{63,100}]
wire [4:0] _wbInfo_0_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _wbInfo_1_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _wbInfo_2_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _divSqrt_waddr_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37, :1017:36]
wire _wbInfo_1_pipeid_T_11 = _wbInfo_1_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_1_pipeid_T_3 = mem_ctrl_fma & _wbInfo_1_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_1_pipeid_T_4 = {_wbInfo_1_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_1_pipeid_T_6 = mem_ctrl_fma & _wbInfo_1_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_1_pipeid_T_7 = {2{_wbInfo_1_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_1_pipeid_T_9 = mem_ctrl_fma & _wbInfo_1_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_1_pipeid_T_10 = {_wbInfo_1_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_1_pipeid_T_12 = {1'h0, _wbInfo_1_pipeid_T_11} | _wbInfo_1_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_1_pipeid_T_13 = _wbInfo_1_pipeid_T_12 | _wbInfo_1_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_1_pipeid_T_14 = {1'h0, _wbInfo_1_pipeid_T_13} | _wbInfo_1_pipeid_T_10; // @[FPU.scala:928:{63,100}]
wire _wbInfo_2_pipeid_T_11 = _wbInfo_2_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_2_pipeid_T_3 = mem_ctrl_fma & _wbInfo_2_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_2_pipeid_T_4 = {_wbInfo_2_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_2_pipeid_T_6 = mem_ctrl_fma & _wbInfo_2_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_2_pipeid_T_7 = {2{_wbInfo_2_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_2_pipeid_T_9 = mem_ctrl_fma & _wbInfo_2_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_2_pipeid_T_10 = {_wbInfo_2_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_2_pipeid_T_12 = {1'h0, _wbInfo_2_pipeid_T_11} | _wbInfo_2_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_2_pipeid_T_13 = _wbInfo_2_pipeid_T_12 | _wbInfo_2_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_2_pipeid_T_14 = {1'h0, _wbInfo_2_pipeid_T_13} | _wbInfo_2_pipeid_T_10; // @[FPU.scala:928:{63,100}]
assign waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd; // @[FPU.scala:896:32, :898:26, :940:19, :963:18]
assign io_sboard_clra_0 = waddr; // @[FPU.scala:735:7, :963:18]
assign frfWriteBundle_1_wrdst = waddr; // @[FPU.scala:805:44, :963:18]
wire wb_cp = divSqrt_wen ? divSqrt_cp : wbInfo_0_cp; // @[FPU.scala:896:32, :899:23, :940:19, :964:18]
wire [1:0] wtypeTag = divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag; // @[FPU.scala:896:32, :900:29, :940:19, :965:21]
wire _GEN_9 = wbInfo_0_pipeid == 3'h1; // @[package.scala:39:86]
wire _wdata_T_39; // @[package.scala:39:86]
assign _wdata_T_39 = _GEN_9; // @[package.scala:39:86]
wire _wexc_T; // @[package.scala:39:86]
assign _wexc_T = _GEN_9; // @[package.scala:39:86]
wire [64:0] _wdata_T_40 = _wdata_T_39 ? _ifpu_io_out_bits_data : _fpmu_io_out_bits_data; // @[package.scala:39:{76,86}]
wire _GEN_10 = wbInfo_0_pipeid == 3'h2; // @[package.scala:39:86]
wire _wdata_T_41; // @[package.scala:39:86]
assign _wdata_T_41 = _GEN_10; // @[package.scala:39:86]
wire _wexc_T_2; // @[package.scala:39:86]
assign _wexc_T_2 = _GEN_10; // @[package.scala:39:86]
wire [64:0] _wdata_T_42 = _wdata_T_41 ? _sfma_io_out_bits_data : _wdata_T_40; // @[package.scala:39:{76,86}]
wire _GEN_11 = wbInfo_0_pipeid == 3'h3; // @[package.scala:39:86]
wire _wdata_T_43; // @[package.scala:39:86]
assign _wdata_T_43 = _GEN_11; // @[package.scala:39:86]
wire _wexc_T_4; // @[package.scala:39:86]
assign _wexc_T_4 = _GEN_11; // @[package.scala:39:86]
wire _io_sboard_clr_T_2; // @[FPU.scala:1007:99]
assign _io_sboard_clr_T_2 = _GEN_11; // @[package.scala:39:86]
wire [64:0] _wdata_T_44 = _wdata_T_43 ? _dfma_io_out_bits_data : _wdata_T_42; // @[package.scala:39:{76,86}]
wire _GEN_12 = wbInfo_0_pipeid == 3'h4; // @[package.scala:39:86]
wire _wdata_T_45; // @[package.scala:39:86]
assign _wdata_T_45 = _GEN_12; // @[package.scala:39:86]
wire _wexc_T_6; // @[package.scala:39:86]
assign _wexc_T_6 = _GEN_12; // @[package.scala:39:86]
wire [64:0] _wdata_T_46 = _wdata_T_45 ? _hfma_io_out_bits_data : _wdata_T_44; // @[package.scala:39:{76,86}]
wire _GEN_13 = wbInfo_0_pipeid == 3'h5; // @[package.scala:39:86]
wire _wdata_T_47; // @[package.scala:39:86]
assign _wdata_T_47 = _GEN_13; // @[package.scala:39:86]
wire _wexc_T_8; // @[package.scala:39:86]
assign _wexc_T_8 = _GEN_13; // @[package.scala:39:86]
wire [64:0] _wdata_T_48 = _wdata_T_47 ? _hfma_io_out_bits_data : _wdata_T_46; // @[package.scala:39:{76,86}]
wire _GEN_14 = wbInfo_0_pipeid == 3'h6; // @[package.scala:39:86]
wire _wdata_T_49; // @[package.scala:39:86]
assign _wdata_T_49 = _GEN_14; // @[package.scala:39:86]
wire _wexc_T_10; // @[package.scala:39:86]
assign _wexc_T_10 = _GEN_14; // @[package.scala:39:86]
wire [64:0] _wdata_T_50 = _wdata_T_49 ? _hfma_io_out_bits_data : _wdata_T_48; // @[package.scala:39:{76,86}]
wire _wdata_T_51 = &wbInfo_0_pipeid; // @[package.scala:39:86]
wire [64:0] _wdata_T_52 = _wdata_T_51 ? _hfma_io_out_bits_data : _wdata_T_50; // @[package.scala:39:{76,86}]
wire [64:0] _wdata_T_53 = divSqrt_wen ? divSqrt_wdata : _wdata_T_52; // @[package.scala:39:76]
wire _wdata_opts_bigger_swizzledNaN_T_1 = _wdata_T_53[15]; // @[FPU.scala:340:8, :966:22]
wire _wdata_opts_bigger_swizzledNaN_T_2 = _wdata_T_53[16]; // @[FPU.scala:342:8, :966:22]
wire [14:0] _wdata_opts_bigger_swizzledNaN_T_3 = _wdata_T_53[14:0]; // @[FPU.scala:343:8, :966:22]
wire [7:0] wdata_opts_bigger_swizzledNaN_lo_hi = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8]
wire [22:0] wdata_opts_bigger_swizzledNaN_lo = {wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_lo = {4'hF, _wdata_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8]
wire [9:0] wdata_opts_bigger_swizzledNaN_hi = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_opts_bigger_swizzledNaN = {wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_opts_bigger = wdata_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8]
wire [64:0] wdata_opts_0 = {32'hFFFFFFFF, wdata_opts_bigger}; // @[FPU.scala:344:8, :398:14]
wire _wdata_opts_bigger_swizzledNaN_T_5 = _wdata_T_53[31]; // @[FPU.scala:340:8, :966:22]
wire _wdata_opts_bigger_swizzledNaN_T_6 = _wdata_T_53[32]; // @[FPU.scala:342:8, :966:22]
wire [30:0] _wdata_opts_bigger_swizzledNaN_T_7 = _wdata_T_53[30:0]; // @[FPU.scala:343:8, :966:22]
wire [20:0] wdata_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _wdata_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8]
wire [51:0] wdata_opts_bigger_swizzledNaN_lo_1 = {wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [7:0] wdata_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8]
wire [12:0] wdata_opts_bigger_swizzledNaN_hi_1 = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_opts_bigger_swizzledNaN_1 = {wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_opts_bigger_1 = wdata_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8]
wire [64:0] wdata_opts_1 = wdata_opts_bigger_1; // @[FPU.scala:344:8, :398:14]
wire _wdata_T_54 = wtypeTag == 2'h1; // @[package.scala:39:86]
wire [64:0] _wdata_T_55 = _wdata_T_54 ? wdata_opts_1 : wdata_opts_0; // @[package.scala:39:{76,86}]
wire _wdata_T_56 = wtypeTag == 2'h2; // @[package.scala:39:86]
wire [64:0] _wdata_T_57 = _wdata_T_56 ? _wdata_T_53 : _wdata_T_55; // @[package.scala:39:{76,86}]
wire _wdata_T_58 = &wtypeTag; // @[package.scala:39:86]
wire [64:0] wdata_1 = _wdata_T_58 ? _wdata_T_53 : _wdata_T_57; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_1 = _wexc_T ? _ifpu_io_out_bits_exc : _fpmu_io_out_bits_exc; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_3 = _wexc_T_2 ? _sfma_io_out_bits_exc : _wexc_T_1; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_5 = _wexc_T_4 ? _dfma_io_out_bits_exc : _wexc_T_3; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_7 = _wexc_T_6 ? _hfma_io_out_bits_exc : _wexc_T_5; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_9 = _wexc_T_8 ? _hfma_io_out_bits_exc : _wexc_T_7; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_11 = _wexc_T_10 ? _hfma_io_out_bits_exc : _wexc_T_9; // @[package.scala:39:{76,86}]
wire _wexc_T_12 = &wbInfo_0_pipeid; // @[package.scala:39:86]
wire [4:0] wexc = _wexc_T_12 ? _hfma_io_out_bits_exc : _wexc_T_11; // @[package.scala:39:{76,86}]
wire _io_fcsr_flags_valid_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :995:62]
wire _io_fcsr_flags_bits_T_3 = wen[0]; // @[FPU.scala:939:20, :968:30, :999:12]
wire _io_sboard_clr_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :1007:56]
assign frfWriteBundle_1_wrenf = ~wbInfo_0_cp & wen[0] | divSqrt_wen; // @[FPU.scala:805:44, :896:32, :939:20, :940:19, :968:{10,24,30,35}]
wire _unswizzled_T_3 = wdata_1[31]; // @[package.scala:39:76]
wire _frfWriteBundle_1_wrdata_prevRecoded_T = wdata_1[31]; // @[package.scala:39:76]
wire _unswizzled_T_4 = wdata_1[52]; // @[package.scala:39:76]
wire _frfWriteBundle_1_wrdata_prevRecoded_T_1 = wdata_1[52]; // @[package.scala:39:76]
wire [30:0] _unswizzled_T_5 = wdata_1[30:0]; // @[package.scala:39:76]
wire [30:0] _frfWriteBundle_1_wrdata_prevRecoded_T_2 = wdata_1[30:0]; // @[package.scala:39:76]
wire [1:0] unswizzled_hi_1 = {_unswizzled_T_3, _unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [32:0] unswizzled_1 = {unswizzled_hi_1, _unswizzled_T_5}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_T_4 = wdata_1[64:60]; // @[package.scala:39:76]
wire _prevOK_T_5 = &_prevOK_T_4; // @[FPU.scala:332:{49,84}]
wire _prevOK_T_6 = ~_prevOK_T_5; // @[FPU.scala:332:84, :384:20]
wire _prevOK_unswizzled_T_3 = unswizzled_1[15]; // @[FPU.scala:380:27, :381:10]
wire _prevOK_unswizzled_T_4 = unswizzled_1[23]; // @[FPU.scala:380:27, :382:10]
wire [14:0] _prevOK_unswizzled_T_5 = unswizzled_1[14:0]; // @[FPU.scala:380:27, :383:10]
wire [1:0] prevOK_unswizzled_hi_1 = {_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [16:0] prevOK_unswizzled_1 = {prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_prevOK_T_3 = unswizzled_1[32:28]; // @[FPU.scala:332:49, :380:27]
wire _prevOK_prevOK_T_4 = &_prevOK_prevOK_T_3; // @[FPU.scala:332:{49,84}]
wire _prevOK_prevOK_T_5 = ~_prevOK_prevOK_T_4; // @[FPU.scala:332:84, :384:20]
wire [2:0] _prevOK_curOK_T_7 = unswizzled_1[31:29]; // @[FPU.scala:249:25, :380:27]
wire _prevOK_curOK_T_8 = &_prevOK_curOK_T_7; // @[FPU.scala:249:{25,56}]
wire _prevOK_curOK_T_9 = ~_prevOK_curOK_T_8; // @[FPU.scala:249:56, :385:19]
wire _prevOK_curOK_T_10 = unswizzled_1[28]; // @[FPU.scala:380:27, :385:35]
wire [6:0] _prevOK_curOK_T_11 = unswizzled_1[22:16]; // @[FPU.scala:380:27, :385:60]
wire _prevOK_curOK_T_12 = &_prevOK_curOK_T_11; // @[FPU.scala:385:{60,96}]
wire _prevOK_curOK_T_13 = _prevOK_curOK_T_10 == _prevOK_curOK_T_12; // @[FPU.scala:385:{35,55,96}]
wire prevOK_curOK_1 = _prevOK_curOK_T_9 | _prevOK_curOK_T_13; // @[FPU.scala:385:{19,31,55}]
wire _prevOK_T_7 = prevOK_curOK_1; // @[FPU.scala:385:31, :386:14]
wire prevOK_1 = _prevOK_T_6 | _prevOK_T_7; // @[FPU.scala:384:{20,33}, :386:14]
wire [2:0] _curOK_T_7 = wdata_1[63:61]; // @[package.scala:39:76]
wire [2:0] _frfWriteBundle_1_wrdata_T_1 = wdata_1[63:61]; // @[package.scala:39:76]
wire _curOK_T_8 = &_curOK_T_7; // @[FPU.scala:249:{25,56}]
wire _curOK_T_9 = ~_curOK_T_8; // @[FPU.scala:249:56, :385:19]
wire _curOK_T_10 = wdata_1[60]; // @[package.scala:39:76]
wire [19:0] _curOK_T_11 = wdata_1[51:32]; // @[package.scala:39:76]
wire _curOK_T_12 = &_curOK_T_11; // @[FPU.scala:385:{60,96}]
wire _curOK_T_13 = _curOK_T_10 == _curOK_T_12; // @[FPU.scala:385:{35,55,96}]
wire curOK_1 = _curOK_T_9 | _curOK_T_13; // @[FPU.scala:385:{19,31,55}] |
Generate the Verilog code corresponding to the following Chisel files.
File dispatch.scala:
//******************************************************************************
// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// BOOM Instruction Dispatcher
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
class DispatchIO(implicit p: Parameters) extends BoomBundle
{
// incoming microops from rename2
val ren_uops = Vec(coreWidth, Flipped(DecoupledIO(new MicroOp)))
// outgoing microops to issue queues
// N issues each accept up to dispatchWidth uops
// dispatchWidth may vary between issue queues
val dis_uops = MixedVec(issueParams.map(ip=>Vec(ip.dispatchWidth, DecoupledIO(new MicroOp))))
}
abstract class Dispatcher(implicit p: Parameters) extends BoomModule
{
val io = IO(new DispatchIO)
}
/**
* This Dispatcher assumes worst case, all dispatched uops go to 1 issue queue
* This is equivalent to BOOMv2 behavior
*/
class BasicDispatcher(implicit p: Parameters) extends Dispatcher
{
issueParams.map(ip=>require(ip.dispatchWidth == coreWidth))
val ren_readys = io.dis_uops.map(d=>VecInit(d.map(_.ready)).asUInt).reduce(_&_)
for (w <- 0 until coreWidth) {
io.ren_uops(w).ready := ren_readys(w)
}
for {i <- 0 until issueParams.size
w <- 0 until coreWidth} {
val issueParam = issueParams(i)
val dis = io.dis_uops(i)
dis(w).valid := io.ren_uops(w).valid && ((io.ren_uops(w).bits.iq_type & issueParam.iqType.U) =/= 0.U)
dis(w).bits := io.ren_uops(w).bits
}
}
/**
* Tries to dispatch as many uops as it can to issue queues,
* which may accept fewer than coreWidth per cycle.
* When dispatchWidth == coreWidth, its behavior differs
* from the BasicDispatcher in that it will only stall dispatch when
* an issue queue required by a uop is full.
*/
class CompactingDispatcher(implicit p: Parameters) extends Dispatcher
{
issueParams.map(ip => require(ip.dispatchWidth >= ip.issueWidth))
val ren_readys = Wire(Vec(issueParams.size, Vec(coreWidth, Bool())))
for (((ip, dis), rdy) <- issueParams zip io.dis_uops zip ren_readys) {
val ren = Wire(Vec(coreWidth, Decoupled(new MicroOp)))
ren <> io.ren_uops
val uses_iq = ren map (u => (u.bits.iq_type & ip.iqType.U).orR)
// Only request an issue slot if the uop needs to enter that queue.
(ren zip io.ren_uops zip uses_iq) foreach {case ((u,v),q) =>
u.valid := v.valid && q}
val compactor = Module(new Compactor(coreWidth, ip.dispatchWidth, new MicroOp))
compactor.io.in <> ren
dis <> compactor.io.out
// The queue is considered ready if the uop doesn't use it.
rdy := ren zip uses_iq map {case (u,q) => u.ready || !q}
}
(ren_readys.reduce((r,i) =>
VecInit(r zip i map {case (r,i) =>
r && i})) zip io.ren_uops) foreach {case (r,u) =>
u.ready := r}
}
| module BasicDispatcher_1( // @[dispatch.scala:43:7]
input clock, // @[dispatch.scala:43:7]
input reset, // @[dispatch.scala:43:7]
output io_ren_uops_0_ready, // @[dispatch.scala:36:14]
input io_ren_uops_0_valid, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_uopc, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_0_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_0_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_0_bits_debug_pc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_iq_type, // @[dispatch.scala:36:14]
input [9:0] io_ren_uops_0_bits_fu_code, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_0_bits_ctrl_br_type, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ctrl_is_load, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ctrl_is_std, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_iw_state, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_br, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_jalr, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_jal, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_sfb, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_0_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_0_bits_br_tag, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_taken, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_0_bits_imm_packed, // @[dispatch.scala:36:14]
input [11:0] io_ren_uops_0_bits_csr_addr, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs3, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs3_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_0_bits_exc_cause, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_bypassable, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs3, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ldst_val, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_val, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_single, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
output io_ren_uops_1_ready, // @[dispatch.scala:36:14]
input io_ren_uops_1_valid, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_uopc, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_1_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_1_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_1_bits_debug_pc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_iq_type, // @[dispatch.scala:36:14]
input [9:0] io_ren_uops_1_bits_fu_code, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_1_bits_ctrl_br_type, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ctrl_is_load, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ctrl_is_std, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_iw_state, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_br, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_jalr, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_jal, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_sfb, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_1_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_1_bits_br_tag, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_taken, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_1_bits_imm_packed, // @[dispatch.scala:36:14]
input [11:0] io_ren_uops_1_bits_csr_addr, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs3, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs3_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_1_bits_exc_cause, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_bypassable, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs3, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ldst_val, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_val, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_single, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
output io_ren_uops_2_ready, // @[dispatch.scala:36:14]
input io_ren_uops_2_valid, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_uopc, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_2_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_2_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_2_bits_debug_pc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_iq_type, // @[dispatch.scala:36:14]
input [9:0] io_ren_uops_2_bits_fu_code, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_2_bits_ctrl_br_type, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ctrl_is_load, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ctrl_is_std, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_iw_state, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_br, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_jalr, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_jal, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_sfb, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_2_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_2_bits_br_tag, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_taken, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_2_bits_imm_packed, // @[dispatch.scala:36:14]
input [11:0] io_ren_uops_2_bits_csr_addr, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs3, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs3_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_2_bits_exc_cause, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_bypassable, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs3, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ldst_val, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_val, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_single, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_0_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_2_0_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_0_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_0_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_2_0_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_0_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_1_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_2_1_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_1_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_1_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_2_1_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_1_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_2_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_2_2_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_2_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_2_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_2_2_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_2_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_0_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_1_0_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_0_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_0_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_1_0_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_0_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_1_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_1_1_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_1_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_1_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_1_1_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_1_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_2_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_1_2_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_2_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_2_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_1_2_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_2_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_0_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_0_0_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_0_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_0_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_0_0_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_0_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_1_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_0_1_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_1_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_1_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_0_1_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_1_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_valid, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_uopc, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_2_bits_debug_pc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_iq_type, // @[dispatch.scala:36:14]
output [9:0] io_dis_uops_0_2_bits_fu_code, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_2_bits_ctrl_br_type, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_ctrl_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_ctrl_op2_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_ctrl_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ctrl_op_fcn, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ctrl_fcn_dw, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_ctrl_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ctrl_is_load, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ctrl_is_sta, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ctrl_is_std, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_iw_state, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_p1_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_p2_poisoned, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_br, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_jalr, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_jal, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_sfb, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_2_bits_br_tag, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_taken, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [11:0] io_dis_uops_0_2_bits_csr_addr, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_2_bits_exc_cause, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_bypassable, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs3, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ldst_val, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_val, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_single, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_debug_tsrc // @[dispatch.scala:36:14]
);
wire io_ren_uops_0_valid_0 = io_ren_uops_0_valid; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_uopc_0 = io_ren_uops_0_bits_uopc; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_0_bits_inst_0 = io_ren_uops_0_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_iq_type_0 = io_ren_uops_0_bits_iq_type; // @[dispatch.scala:43:7]
wire [9:0] io_ren_uops_0_bits_fu_code_0 = io_ren_uops_0_bits_fu_code; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_0_bits_ctrl_br_type_0 = io_ren_uops_0_bits_ctrl_br_type; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_ctrl_op1_sel_0 = io_ren_uops_0_bits_ctrl_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_ctrl_op2_sel_0 = io_ren_uops_0_bits_ctrl_op2_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_ctrl_imm_sel_0 = io_ren_uops_0_bits_ctrl_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ctrl_op_fcn_0 = io_ren_uops_0_bits_ctrl_op_fcn; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ctrl_fcn_dw_0 = io_ren_uops_0_bits_ctrl_fcn_dw; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_ctrl_csr_cmd_0 = io_ren_uops_0_bits_ctrl_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ctrl_is_load_0 = io_ren_uops_0_bits_ctrl_is_load; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ctrl_is_sta_0 = io_ren_uops_0_bits_ctrl_is_sta; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ctrl_is_std_0 = io_ren_uops_0_bits_ctrl_is_std; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_iw_state_0 = io_ren_uops_0_bits_iw_state; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_p1_poisoned_0 = io_ren_uops_0_bits_iw_p1_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_p2_poisoned_0 = io_ren_uops_0_bits_iw_p2_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_br_0 = io_ren_uops_0_bits_is_br; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_jalr_0 = io_ren_uops_0_bits_is_jalr; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_jal_0 = io_ren_uops_0_bits_is_jal; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_taken_0 = io_ren_uops_0_bits_taken; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed; // @[dispatch.scala:43:7]
wire [11:0] io_ren_uops_0_bits_csr_addr_0 = io_ren_uops_0_bits_csr_addr; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_pdst_0 = io_ren_uops_0_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs1_0 = io_ren_uops_0_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs2_0 = io_ren_uops_0_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs3_0 = io_ren_uops_0_bits_prs3; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_exception_0 = io_ren_uops_0_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_bypassable_0 = io_ren_uops_0_bits_bypassable; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_ldst_0 = io_ren_uops_0_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ldst_val_0 = io_ren_uops_0_bits_ldst_val; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_single_0 = io_ren_uops_0_bits_fp_single; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_valid_0 = io_ren_uops_1_valid; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_uopc_0 = io_ren_uops_1_bits_uopc; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_1_bits_inst_0 = io_ren_uops_1_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_iq_type_0 = io_ren_uops_1_bits_iq_type; // @[dispatch.scala:43:7]
wire [9:0] io_ren_uops_1_bits_fu_code_0 = io_ren_uops_1_bits_fu_code; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_1_bits_ctrl_br_type_0 = io_ren_uops_1_bits_ctrl_br_type; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_ctrl_op1_sel_0 = io_ren_uops_1_bits_ctrl_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_ctrl_op2_sel_0 = io_ren_uops_1_bits_ctrl_op2_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_ctrl_imm_sel_0 = io_ren_uops_1_bits_ctrl_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ctrl_op_fcn_0 = io_ren_uops_1_bits_ctrl_op_fcn; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ctrl_fcn_dw_0 = io_ren_uops_1_bits_ctrl_fcn_dw; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_ctrl_csr_cmd_0 = io_ren_uops_1_bits_ctrl_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ctrl_is_load_0 = io_ren_uops_1_bits_ctrl_is_load; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ctrl_is_sta_0 = io_ren_uops_1_bits_ctrl_is_sta; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ctrl_is_std_0 = io_ren_uops_1_bits_ctrl_is_std; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_iw_state_0 = io_ren_uops_1_bits_iw_state; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_p1_poisoned_0 = io_ren_uops_1_bits_iw_p1_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_p2_poisoned_0 = io_ren_uops_1_bits_iw_p2_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_br_0 = io_ren_uops_1_bits_is_br; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_jalr_0 = io_ren_uops_1_bits_is_jalr; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_jal_0 = io_ren_uops_1_bits_is_jal; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_taken_0 = io_ren_uops_1_bits_taken; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed; // @[dispatch.scala:43:7]
wire [11:0] io_ren_uops_1_bits_csr_addr_0 = io_ren_uops_1_bits_csr_addr; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_pdst_0 = io_ren_uops_1_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs1_0 = io_ren_uops_1_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs2_0 = io_ren_uops_1_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs3_0 = io_ren_uops_1_bits_prs3; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_exception_0 = io_ren_uops_1_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_bypassable_0 = io_ren_uops_1_bits_bypassable; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_ldst_0 = io_ren_uops_1_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ldst_val_0 = io_ren_uops_1_bits_ldst_val; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_single_0 = io_ren_uops_1_bits_fp_single; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_valid_0 = io_ren_uops_2_valid; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_uopc_0 = io_ren_uops_2_bits_uopc; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_2_bits_inst_0 = io_ren_uops_2_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_iq_type_0 = io_ren_uops_2_bits_iq_type; // @[dispatch.scala:43:7]
wire [9:0] io_ren_uops_2_bits_fu_code_0 = io_ren_uops_2_bits_fu_code; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_2_bits_ctrl_br_type_0 = io_ren_uops_2_bits_ctrl_br_type; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_ctrl_op1_sel_0 = io_ren_uops_2_bits_ctrl_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_ctrl_op2_sel_0 = io_ren_uops_2_bits_ctrl_op2_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_ctrl_imm_sel_0 = io_ren_uops_2_bits_ctrl_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ctrl_op_fcn_0 = io_ren_uops_2_bits_ctrl_op_fcn; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ctrl_fcn_dw_0 = io_ren_uops_2_bits_ctrl_fcn_dw; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_ctrl_csr_cmd_0 = io_ren_uops_2_bits_ctrl_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ctrl_is_load_0 = io_ren_uops_2_bits_ctrl_is_load; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ctrl_is_sta_0 = io_ren_uops_2_bits_ctrl_is_sta; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ctrl_is_std_0 = io_ren_uops_2_bits_ctrl_is_std; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_iw_state_0 = io_ren_uops_2_bits_iw_state; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_p1_poisoned_0 = io_ren_uops_2_bits_iw_p1_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_p2_poisoned_0 = io_ren_uops_2_bits_iw_p2_poisoned; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_br_0 = io_ren_uops_2_bits_is_br; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_jalr_0 = io_ren_uops_2_bits_is_jalr; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_jal_0 = io_ren_uops_2_bits_is_jal; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_taken_0 = io_ren_uops_2_bits_taken; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed; // @[dispatch.scala:43:7]
wire [11:0] io_ren_uops_2_bits_csr_addr_0 = io_ren_uops_2_bits_csr_addr; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_pdst_0 = io_ren_uops_2_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs1_0 = io_ren_uops_2_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs2_0 = io_ren_uops_2_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs3_0 = io_ren_uops_2_bits_prs3; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_exception_0 = io_ren_uops_2_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_bypassable_0 = io_ren_uops_2_bits_bypassable; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_ldst_0 = io_ren_uops_2_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ldst_val_0 = io_ren_uops_2_bits_ldst_val; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_single_0 = io_ren_uops_2_bits_fp_single; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_ready_0 = io_dis_uops_2_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_ready_0 = io_dis_uops_2_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_ready_0 = io_dis_uops_2_2_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_ready_0 = io_dis_uops_1_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_ready_0 = io_dis_uops_1_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_ready_0 = io_dis_uops_1_2_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_ready_0 = io_dis_uops_0_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_ready_0 = io_dis_uops_0_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_ready_0 = io_dis_uops_0_2_ready; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ppred_busy = 1'h0; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_ren_uops_1_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_ren_uops_2_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_2_0_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_2_1_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_2_2_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_1_0_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_1_1_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_1_2_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_0_0_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_0_1_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire [4:0] io_dis_uops_0_2_bits_ppred = 5'h0; // @[dispatch.scala:36:14, :43:7]
wire _io_ren_uops_0_ready_T; // @[dispatch.scala:50:39]
wire [6:0] io_dis_uops_2_0_bits_uopc_0 = io_ren_uops_0_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_uopc_0 = io_ren_uops_0_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_uopc_0 = io_ren_uops_0_bits_uopc_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_iq_type_0 = io_ren_uops_0_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_iq_type_0 = io_ren_uops_0_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_iq_type_0 = io_ren_uops_0_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_2_0_bits_fu_code_0 = io_ren_uops_0_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_1_0_bits_fu_code_0 = io_ren_uops_0_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_0_0_bits_fu_code_0 = io_ren_uops_0_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_0_bits_ctrl_br_type_0 = io_ren_uops_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_0_bits_ctrl_br_type_0 = io_ren_uops_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_0_bits_ctrl_br_type_0 = io_ren_uops_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_ctrl_op1_sel_0 = io_ren_uops_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_ctrl_op1_sel_0 = io_ren_uops_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_ctrl_op1_sel_0 = io_ren_uops_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_ctrl_op2_sel_0 = io_ren_uops_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_ctrl_op2_sel_0 = io_ren_uops_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_ctrl_op2_sel_0 = io_ren_uops_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_ctrl_imm_sel_0 = io_ren_uops_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_ctrl_imm_sel_0 = io_ren_uops_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_ctrl_imm_sel_0 = io_ren_uops_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ctrl_op_fcn_0 = io_ren_uops_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ctrl_op_fcn_0 = io_ren_uops_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ctrl_op_fcn_0 = io_ren_uops_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ctrl_fcn_dw_0 = io_ren_uops_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ctrl_fcn_dw_0 = io_ren_uops_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ctrl_fcn_dw_0 = io_ren_uops_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_ctrl_csr_cmd_0 = io_ren_uops_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_ctrl_csr_cmd_0 = io_ren_uops_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_ctrl_csr_cmd_0 = io_ren_uops_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ctrl_is_load_0 = io_ren_uops_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ctrl_is_load_0 = io_ren_uops_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ctrl_is_load_0 = io_ren_uops_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ctrl_is_sta_0 = io_ren_uops_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ctrl_is_sta_0 = io_ren_uops_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ctrl_is_sta_0 = io_ren_uops_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ctrl_is_std_0 = io_ren_uops_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ctrl_is_std_0 = io_ren_uops_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ctrl_is_std_0 = io_ren_uops_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_iw_state_0 = io_ren_uops_0_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_iw_state_0 = io_ren_uops_0_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_iw_state_0 = io_ren_uops_0_bits_iw_state_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_p1_poisoned_0 = io_ren_uops_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_p1_poisoned_0 = io_ren_uops_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_p1_poisoned_0 = io_ren_uops_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_p2_poisoned_0 = io_ren_uops_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_p2_poisoned_0 = io_ren_uops_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_p2_poisoned_0 = io_ren_uops_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_br_0 = io_ren_uops_0_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_br_0 = io_ren_uops_0_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_br_0 = io_ren_uops_0_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_jalr_0 = io_ren_uops_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_jalr_0 = io_ren_uops_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_jalr_0 = io_ren_uops_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_jal_0 = io_ren_uops_0_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_jal_0 = io_ren_uops_0_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_jal_0 = io_ren_uops_0_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_2_0_bits_csr_addr_0 = io_ren_uops_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_1_0_bits_csr_addr_0 = io_ren_uops_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_0_0_bits_csr_addr_0 = io_ren_uops_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_bypassable_0 = io_ren_uops_0_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_bypassable_0 = io_ren_uops_0_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_bypassable_0 = io_ren_uops_0_bits_bypassable_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ldst_val_0 = io_ren_uops_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ldst_val_0 = io_ren_uops_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ldst_val_0 = io_ren_uops_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_single_0 = io_ren_uops_0_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_single_0 = io_ren_uops_0_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_single_0 = io_ren_uops_0_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _io_ren_uops_1_ready_T; // @[dispatch.scala:50:39]
wire [6:0] io_dis_uops_2_1_bits_uopc_0 = io_ren_uops_1_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_uopc_0 = io_ren_uops_1_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_uopc_0 = io_ren_uops_1_bits_uopc_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_iq_type_0 = io_ren_uops_1_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_iq_type_0 = io_ren_uops_1_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_iq_type_0 = io_ren_uops_1_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_2_1_bits_fu_code_0 = io_ren_uops_1_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_1_1_bits_fu_code_0 = io_ren_uops_1_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_0_1_bits_fu_code_0 = io_ren_uops_1_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_1_bits_ctrl_br_type_0 = io_ren_uops_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_1_bits_ctrl_br_type_0 = io_ren_uops_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_1_bits_ctrl_br_type_0 = io_ren_uops_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_ctrl_op1_sel_0 = io_ren_uops_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_ctrl_op1_sel_0 = io_ren_uops_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_ctrl_op1_sel_0 = io_ren_uops_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_ctrl_op2_sel_0 = io_ren_uops_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_ctrl_op2_sel_0 = io_ren_uops_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_ctrl_op2_sel_0 = io_ren_uops_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_ctrl_imm_sel_0 = io_ren_uops_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_ctrl_imm_sel_0 = io_ren_uops_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_ctrl_imm_sel_0 = io_ren_uops_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ctrl_op_fcn_0 = io_ren_uops_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ctrl_op_fcn_0 = io_ren_uops_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ctrl_op_fcn_0 = io_ren_uops_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ctrl_fcn_dw_0 = io_ren_uops_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ctrl_fcn_dw_0 = io_ren_uops_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ctrl_fcn_dw_0 = io_ren_uops_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_ctrl_csr_cmd_0 = io_ren_uops_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_ctrl_csr_cmd_0 = io_ren_uops_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_ctrl_csr_cmd_0 = io_ren_uops_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ctrl_is_load_0 = io_ren_uops_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ctrl_is_load_0 = io_ren_uops_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ctrl_is_load_0 = io_ren_uops_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ctrl_is_sta_0 = io_ren_uops_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ctrl_is_sta_0 = io_ren_uops_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ctrl_is_sta_0 = io_ren_uops_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ctrl_is_std_0 = io_ren_uops_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ctrl_is_std_0 = io_ren_uops_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ctrl_is_std_0 = io_ren_uops_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_iw_state_0 = io_ren_uops_1_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_iw_state_0 = io_ren_uops_1_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_iw_state_0 = io_ren_uops_1_bits_iw_state_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_p1_poisoned_0 = io_ren_uops_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_p1_poisoned_0 = io_ren_uops_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_p1_poisoned_0 = io_ren_uops_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_p2_poisoned_0 = io_ren_uops_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_p2_poisoned_0 = io_ren_uops_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_p2_poisoned_0 = io_ren_uops_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_br_0 = io_ren_uops_1_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_br_0 = io_ren_uops_1_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_br_0 = io_ren_uops_1_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_jalr_0 = io_ren_uops_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_jalr_0 = io_ren_uops_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_jalr_0 = io_ren_uops_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_jal_0 = io_ren_uops_1_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_jal_0 = io_ren_uops_1_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_jal_0 = io_ren_uops_1_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_2_1_bits_csr_addr_0 = io_ren_uops_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_1_1_bits_csr_addr_0 = io_ren_uops_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_0_1_bits_csr_addr_0 = io_ren_uops_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_bypassable_0 = io_ren_uops_1_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_bypassable_0 = io_ren_uops_1_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_bypassable_0 = io_ren_uops_1_bits_bypassable_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ldst_val_0 = io_ren_uops_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ldst_val_0 = io_ren_uops_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ldst_val_0 = io_ren_uops_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_single_0 = io_ren_uops_1_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_single_0 = io_ren_uops_1_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_single_0 = io_ren_uops_1_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _io_ren_uops_2_ready_T; // @[dispatch.scala:50:39]
wire [6:0] io_dis_uops_2_2_bits_uopc_0 = io_ren_uops_2_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_uopc_0 = io_ren_uops_2_bits_uopc_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_uopc_0 = io_ren_uops_2_bits_uopc_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_iq_type_0 = io_ren_uops_2_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_iq_type_0 = io_ren_uops_2_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_iq_type_0 = io_ren_uops_2_bits_iq_type_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_2_2_bits_fu_code_0 = io_ren_uops_2_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_1_2_bits_fu_code_0 = io_ren_uops_2_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [9:0] io_dis_uops_0_2_bits_fu_code_0 = io_ren_uops_2_bits_fu_code_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_2_bits_ctrl_br_type_0 = io_ren_uops_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_2_bits_ctrl_br_type_0 = io_ren_uops_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_2_bits_ctrl_br_type_0 = io_ren_uops_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_ctrl_op1_sel_0 = io_ren_uops_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_ctrl_op1_sel_0 = io_ren_uops_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_ctrl_op1_sel_0 = io_ren_uops_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_ctrl_op2_sel_0 = io_ren_uops_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_ctrl_op2_sel_0 = io_ren_uops_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_ctrl_op2_sel_0 = io_ren_uops_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_ctrl_imm_sel_0 = io_ren_uops_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_ctrl_imm_sel_0 = io_ren_uops_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_ctrl_imm_sel_0 = io_ren_uops_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ctrl_op_fcn_0 = io_ren_uops_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ctrl_op_fcn_0 = io_ren_uops_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ctrl_op_fcn_0 = io_ren_uops_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ctrl_fcn_dw_0 = io_ren_uops_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ctrl_fcn_dw_0 = io_ren_uops_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ctrl_fcn_dw_0 = io_ren_uops_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_ctrl_csr_cmd_0 = io_ren_uops_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_ctrl_csr_cmd_0 = io_ren_uops_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_ctrl_csr_cmd_0 = io_ren_uops_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ctrl_is_load_0 = io_ren_uops_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ctrl_is_load_0 = io_ren_uops_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ctrl_is_load_0 = io_ren_uops_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ctrl_is_sta_0 = io_ren_uops_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ctrl_is_sta_0 = io_ren_uops_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ctrl_is_sta_0 = io_ren_uops_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ctrl_is_std_0 = io_ren_uops_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ctrl_is_std_0 = io_ren_uops_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ctrl_is_std_0 = io_ren_uops_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_iw_state_0 = io_ren_uops_2_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_iw_state_0 = io_ren_uops_2_bits_iw_state_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_iw_state_0 = io_ren_uops_2_bits_iw_state_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_p1_poisoned_0 = io_ren_uops_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_p1_poisoned_0 = io_ren_uops_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_p1_poisoned_0 = io_ren_uops_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_p2_poisoned_0 = io_ren_uops_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_p2_poisoned_0 = io_ren_uops_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_p2_poisoned_0 = io_ren_uops_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_br_0 = io_ren_uops_2_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_br_0 = io_ren_uops_2_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_br_0 = io_ren_uops_2_bits_is_br_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_jalr_0 = io_ren_uops_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_jalr_0 = io_ren_uops_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_jalr_0 = io_ren_uops_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_jal_0 = io_ren_uops_2_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_jal_0 = io_ren_uops_2_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_jal_0 = io_ren_uops_2_bits_is_jal_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_2_2_bits_csr_addr_0 = io_ren_uops_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_1_2_bits_csr_addr_0 = io_ren_uops_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [11:0] io_dis_uops_0_2_bits_csr_addr_0 = io_ren_uops_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_bypassable_0 = io_ren_uops_2_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_bypassable_0 = io_ren_uops_2_bits_bypassable_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_bypassable_0 = io_ren_uops_2_bits_bypassable_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ldst_val_0 = io_ren_uops_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ldst_val_0 = io_ren_uops_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ldst_val_0 = io_ren_uops_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_single_0 = io_ren_uops_2_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_single_0 = io_ren_uops_2_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_single_0 = io_ren_uops_2_bits_fp_single_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _ren_readys_WIRE_2_0 = io_dis_uops_2_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_0_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2_1 = io_dis_uops_2_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_1_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2_2 = io_dis_uops_2_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_2_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_0 = io_dis_uops_1_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_0_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_1 = io_dis_uops_1_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_1_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_2 = io_dis_uops_1_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_2_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_0 = io_dis_uops_0_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_0_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1 = io_dis_uops_0_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_1_valid_T_2; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2 = io_dis_uops_0_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_2_valid_T_2; // @[dispatch.scala:58:42]
wire io_ren_uops_0_ready_0; // @[dispatch.scala:43:7]
wire io_ren_uops_1_ready_0; // @[dispatch.scala:43:7]
wire io_ren_uops_2_ready_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_valid_0; // @[dispatch.scala:43:7]
wire [1:0] ren_readys_hi = {_ren_readys_WIRE_2, _ren_readys_WIRE_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T = {ren_readys_hi, _ren_readys_WIRE_0}; // @[dispatch.scala:47:{46,63}]
wire [1:0] ren_readys_hi_1 = {_ren_readys_WIRE_1_2, _ren_readys_WIRE_1_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_1 = {ren_readys_hi_1, _ren_readys_WIRE_1_0}; // @[dispatch.scala:47:{46,63}]
wire [1:0] ren_readys_hi_2 = {_ren_readys_WIRE_2_2, _ren_readys_WIRE_2_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_2 = {ren_readys_hi_2, _ren_readys_WIRE_2_0}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_3 = _ren_readys_T & _ren_readys_T_1; // @[dispatch.scala:47:{63,79}]
wire [2:0] ren_readys = _ren_readys_T_3 & _ren_readys_T_2; // @[dispatch.scala:47:{63,79}]
assign _io_ren_uops_0_ready_T = ren_readys[0]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_0_ready_0 = _io_ren_uops_0_ready_T; // @[dispatch.scala:43:7, :50:39]
assign _io_ren_uops_1_ready_T = ren_readys[1]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_1_ready_0 = _io_ren_uops_1_ready_T; // @[dispatch.scala:43:7, :50:39]
assign _io_ren_uops_2_ready_T = ren_readys[2]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_2_ready_0 = _io_ren_uops_2_ready_T; // @[dispatch.scala:43:7, :50:39]
wire [2:0] _io_dis_uops_0_0_valid_T = {1'h0, io_ren_uops_0_bits_iq_type_0[1], 1'h0}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_0_0_valid_T_1 = |_io_dis_uops_0_0_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_0_0_valid_T_2 = io_ren_uops_0_valid_0 & _io_dis_uops_0_0_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_0_0_valid_0 = _io_dis_uops_0_0_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_0_1_valid_T = {1'h0, io_ren_uops_1_bits_iq_type_0[1], 1'h0}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_0_1_valid_T_1 = |_io_dis_uops_0_1_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_0_1_valid_T_2 = io_ren_uops_1_valid_0 & _io_dis_uops_0_1_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_0_1_valid_0 = _io_dis_uops_0_1_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_0_2_valid_T = {1'h0, io_ren_uops_2_bits_iq_type_0[1], 1'h0}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_0_2_valid_T_1 = |_io_dis_uops_0_2_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_0_2_valid_T_2 = io_ren_uops_2_valid_0 & _io_dis_uops_0_2_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_0_2_valid_0 = _io_dis_uops_0_2_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_1_0_valid_T = {2'h0, io_ren_uops_0_bits_iq_type_0[0]}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_1_0_valid_T_1 = |_io_dis_uops_1_0_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_1_0_valid_T_2 = io_ren_uops_0_valid_0 & _io_dis_uops_1_0_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_1_0_valid_0 = _io_dis_uops_1_0_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_1_1_valid_T = {2'h0, io_ren_uops_1_bits_iq_type_0[0]}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_1_1_valid_T_1 = |_io_dis_uops_1_1_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_1_1_valid_T_2 = io_ren_uops_1_valid_0 & _io_dis_uops_1_1_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_1_1_valid_0 = _io_dis_uops_1_1_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_1_2_valid_T = {2'h0, io_ren_uops_2_bits_iq_type_0[0]}; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_1_2_valid_T_1 = |_io_dis_uops_1_2_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_1_2_valid_T_2 = io_ren_uops_2_valid_0 & _io_dis_uops_1_2_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_1_2_valid_0 = _io_dis_uops_1_2_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_2_0_valid_T = io_ren_uops_0_bits_iq_type_0 & 3'h4; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_2_0_valid_T_1 = |_io_dis_uops_2_0_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_2_0_valid_T_2 = io_ren_uops_0_valid_0 & _io_dis_uops_2_0_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_2_0_valid_0 = _io_dis_uops_2_0_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_2_1_valid_T = io_ren_uops_1_bits_iq_type_0 & 3'h4; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_2_1_valid_T_1 = |_io_dis_uops_2_1_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_2_1_valid_T_2 = io_ren_uops_1_valid_0 & _io_dis_uops_2_1_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_2_1_valid_0 = _io_dis_uops_2_1_valid_T_2; // @[dispatch.scala:43:7, :58:42]
wire [2:0] _io_dis_uops_2_2_valid_T = io_ren_uops_2_bits_iq_type_0 & 3'h4; // @[dispatch.scala:43:7, :58:75]
wire _io_dis_uops_2_2_valid_T_1 = |_io_dis_uops_2_2_valid_T; // @[dispatch.scala:58:{75,98}]
assign _io_dis_uops_2_2_valid_T_2 = io_ren_uops_2_valid_0 & _io_dis_uops_2_2_valid_T_1; // @[dispatch.scala:43:7, :58:{42,98}]
assign io_dis_uops_2_2_valid_0 = _io_dis_uops_2_2_valid_T_2; // @[dispatch.scala:43:7, :58:42]
assign io_ren_uops_0_ready = io_ren_uops_0_ready_0; // @[dispatch.scala:43:7]
assign io_ren_uops_1_ready = io_ren_uops_1_ready_0; // @[dispatch.scala:43:7]
assign io_ren_uops_2_ready = io_ren_uops_2_ready_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_valid = io_dis_uops_2_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_uopc = io_dis_uops_2_0_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_inst = io_dis_uops_2_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_inst = io_dis_uops_2_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_rvc = io_dis_uops_2_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_pc = io_dis_uops_2_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iq_type = io_dis_uops_2_0_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code = io_dis_uops_2_0_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_br_type = io_dis_uops_2_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_op1_sel = io_dis_uops_2_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_op2_sel = io_dis_uops_2_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_imm_sel = io_dis_uops_2_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_op_fcn = io_dis_uops_2_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_fcn_dw = io_dis_uops_2_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_csr_cmd = io_dis_uops_2_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_is_load = io_dis_uops_2_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_is_sta = io_dis_uops_2_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ctrl_is_std = io_dis_uops_2_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_state = io_dis_uops_2_0_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p1_poisoned = io_dis_uops_2_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p2_poisoned = io_dis_uops_2_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_br = io_dis_uops_2_0_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_jalr = io_dis_uops_2_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_jal = io_dis_uops_2_0_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_sfb = io_dis_uops_2_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_br_mask = io_dis_uops_2_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_br_tag = io_dis_uops_2_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ftq_idx = io_dis_uops_2_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_edge_inst = io_dis_uops_2_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_pc_lob = io_dis_uops_2_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_taken = io_dis_uops_2_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_imm_packed = io_dis_uops_2_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_csr_addr = io_dis_uops_2_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_rob_idx = io_dis_uops_2_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldq_idx = io_dis_uops_2_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_stq_idx = io_dis_uops_2_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_rxq_idx = io_dis_uops_2_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_pdst = io_dis_uops_2_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs1 = io_dis_uops_2_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs2 = io_dis_uops_2_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs3 = io_dis_uops_2_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs1_busy = io_dis_uops_2_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs2_busy = io_dis_uops_2_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs3_busy = io_dis_uops_2_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_stale_pdst = io_dis_uops_2_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_exception = io_dis_uops_2_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_exc_cause = io_dis_uops_2_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_bypassable = io_dis_uops_2_0_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_cmd = io_dis_uops_2_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_size = io_dis_uops_2_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_signed = io_dis_uops_2_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_fence = io_dis_uops_2_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_fencei = io_dis_uops_2_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_amo = io_dis_uops_2_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_uses_ldq = io_dis_uops_2_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_uses_stq = io_dis_uops_2_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_sys_pc2epc = io_dis_uops_2_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_unique = io_dis_uops_2_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_flush_on_commit = io_dis_uops_2_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldst_is_rs1 = io_dis_uops_2_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldst = io_dis_uops_2_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs1 = io_dis_uops_2_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs2 = io_dis_uops_2_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs3 = io_dis_uops_2_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldst_val = io_dis_uops_2_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_dst_rtype = io_dis_uops_2_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs1_rtype = io_dis_uops_2_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs2_rtype = io_dis_uops_2_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_frs3_en = io_dis_uops_2_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_val = io_dis_uops_2_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_single = io_dis_uops_2_0_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_pf_if = io_dis_uops_2_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_ae_if = io_dis_uops_2_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_ma_if = io_dis_uops_2_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_bp_debug_if = io_dis_uops_2_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_bp_xcpt_if = io_dis_uops_2_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_fsrc = io_dis_uops_2_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_tsrc = io_dis_uops_2_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_valid = io_dis_uops_2_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_uopc = io_dis_uops_2_1_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_inst = io_dis_uops_2_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_inst = io_dis_uops_2_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_rvc = io_dis_uops_2_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_pc = io_dis_uops_2_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iq_type = io_dis_uops_2_1_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code = io_dis_uops_2_1_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_br_type = io_dis_uops_2_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_op1_sel = io_dis_uops_2_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_op2_sel = io_dis_uops_2_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_imm_sel = io_dis_uops_2_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_op_fcn = io_dis_uops_2_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_fcn_dw = io_dis_uops_2_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_csr_cmd = io_dis_uops_2_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_is_load = io_dis_uops_2_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_is_sta = io_dis_uops_2_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ctrl_is_std = io_dis_uops_2_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_state = io_dis_uops_2_1_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p1_poisoned = io_dis_uops_2_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p2_poisoned = io_dis_uops_2_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_br = io_dis_uops_2_1_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_jalr = io_dis_uops_2_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_jal = io_dis_uops_2_1_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_sfb = io_dis_uops_2_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_br_mask = io_dis_uops_2_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_br_tag = io_dis_uops_2_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ftq_idx = io_dis_uops_2_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_edge_inst = io_dis_uops_2_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_pc_lob = io_dis_uops_2_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_taken = io_dis_uops_2_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_imm_packed = io_dis_uops_2_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_csr_addr = io_dis_uops_2_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_rob_idx = io_dis_uops_2_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldq_idx = io_dis_uops_2_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_stq_idx = io_dis_uops_2_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_rxq_idx = io_dis_uops_2_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_pdst = io_dis_uops_2_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs1 = io_dis_uops_2_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs2 = io_dis_uops_2_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs3 = io_dis_uops_2_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs1_busy = io_dis_uops_2_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs2_busy = io_dis_uops_2_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs3_busy = io_dis_uops_2_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_stale_pdst = io_dis_uops_2_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_exception = io_dis_uops_2_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_exc_cause = io_dis_uops_2_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_bypassable = io_dis_uops_2_1_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_cmd = io_dis_uops_2_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_size = io_dis_uops_2_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_signed = io_dis_uops_2_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_fence = io_dis_uops_2_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_fencei = io_dis_uops_2_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_amo = io_dis_uops_2_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_uses_ldq = io_dis_uops_2_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_uses_stq = io_dis_uops_2_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_sys_pc2epc = io_dis_uops_2_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_unique = io_dis_uops_2_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_flush_on_commit = io_dis_uops_2_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldst_is_rs1 = io_dis_uops_2_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldst = io_dis_uops_2_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs1 = io_dis_uops_2_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs2 = io_dis_uops_2_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs3 = io_dis_uops_2_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldst_val = io_dis_uops_2_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_dst_rtype = io_dis_uops_2_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs1_rtype = io_dis_uops_2_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs2_rtype = io_dis_uops_2_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_frs3_en = io_dis_uops_2_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_val = io_dis_uops_2_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_single = io_dis_uops_2_1_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_pf_if = io_dis_uops_2_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_ae_if = io_dis_uops_2_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_ma_if = io_dis_uops_2_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_bp_debug_if = io_dis_uops_2_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_bp_xcpt_if = io_dis_uops_2_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_fsrc = io_dis_uops_2_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_tsrc = io_dis_uops_2_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_valid = io_dis_uops_2_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_uopc = io_dis_uops_2_2_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_inst = io_dis_uops_2_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_inst = io_dis_uops_2_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_rvc = io_dis_uops_2_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_pc = io_dis_uops_2_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iq_type = io_dis_uops_2_2_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code = io_dis_uops_2_2_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_br_type = io_dis_uops_2_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_op1_sel = io_dis_uops_2_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_op2_sel = io_dis_uops_2_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_imm_sel = io_dis_uops_2_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_op_fcn = io_dis_uops_2_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_fcn_dw = io_dis_uops_2_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_csr_cmd = io_dis_uops_2_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_is_load = io_dis_uops_2_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_is_sta = io_dis_uops_2_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ctrl_is_std = io_dis_uops_2_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_state = io_dis_uops_2_2_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p1_poisoned = io_dis_uops_2_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p2_poisoned = io_dis_uops_2_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_br = io_dis_uops_2_2_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_jalr = io_dis_uops_2_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_jal = io_dis_uops_2_2_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_sfb = io_dis_uops_2_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_br_mask = io_dis_uops_2_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_br_tag = io_dis_uops_2_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ftq_idx = io_dis_uops_2_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_edge_inst = io_dis_uops_2_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_pc_lob = io_dis_uops_2_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_taken = io_dis_uops_2_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_imm_packed = io_dis_uops_2_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_csr_addr = io_dis_uops_2_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_rob_idx = io_dis_uops_2_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldq_idx = io_dis_uops_2_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_stq_idx = io_dis_uops_2_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_rxq_idx = io_dis_uops_2_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_pdst = io_dis_uops_2_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs1 = io_dis_uops_2_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs2 = io_dis_uops_2_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs3 = io_dis_uops_2_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs1_busy = io_dis_uops_2_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs2_busy = io_dis_uops_2_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs3_busy = io_dis_uops_2_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_stale_pdst = io_dis_uops_2_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_exception = io_dis_uops_2_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_exc_cause = io_dis_uops_2_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_bypassable = io_dis_uops_2_2_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_cmd = io_dis_uops_2_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_size = io_dis_uops_2_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_signed = io_dis_uops_2_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_fence = io_dis_uops_2_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_fencei = io_dis_uops_2_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_amo = io_dis_uops_2_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_uses_ldq = io_dis_uops_2_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_uses_stq = io_dis_uops_2_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_sys_pc2epc = io_dis_uops_2_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_unique = io_dis_uops_2_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_flush_on_commit = io_dis_uops_2_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldst_is_rs1 = io_dis_uops_2_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldst = io_dis_uops_2_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs1 = io_dis_uops_2_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs2 = io_dis_uops_2_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs3 = io_dis_uops_2_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldst_val = io_dis_uops_2_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_dst_rtype = io_dis_uops_2_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs1_rtype = io_dis_uops_2_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs2_rtype = io_dis_uops_2_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_frs3_en = io_dis_uops_2_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_val = io_dis_uops_2_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_single = io_dis_uops_2_2_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_pf_if = io_dis_uops_2_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_ae_if = io_dis_uops_2_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_ma_if = io_dis_uops_2_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_bp_debug_if = io_dis_uops_2_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_bp_xcpt_if = io_dis_uops_2_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_fsrc = io_dis_uops_2_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_tsrc = io_dis_uops_2_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_valid = io_dis_uops_1_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_uopc = io_dis_uops_1_0_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_inst = io_dis_uops_1_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_inst = io_dis_uops_1_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_rvc = io_dis_uops_1_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_pc = io_dis_uops_1_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iq_type = io_dis_uops_1_0_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code = io_dis_uops_1_0_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_br_type = io_dis_uops_1_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_op1_sel = io_dis_uops_1_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_op2_sel = io_dis_uops_1_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_imm_sel = io_dis_uops_1_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_op_fcn = io_dis_uops_1_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_fcn_dw = io_dis_uops_1_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_csr_cmd = io_dis_uops_1_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_is_load = io_dis_uops_1_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_is_sta = io_dis_uops_1_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ctrl_is_std = io_dis_uops_1_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_state = io_dis_uops_1_0_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p1_poisoned = io_dis_uops_1_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p2_poisoned = io_dis_uops_1_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_br = io_dis_uops_1_0_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_jalr = io_dis_uops_1_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_jal = io_dis_uops_1_0_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_sfb = io_dis_uops_1_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_br_mask = io_dis_uops_1_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_br_tag = io_dis_uops_1_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ftq_idx = io_dis_uops_1_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_edge_inst = io_dis_uops_1_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_pc_lob = io_dis_uops_1_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_taken = io_dis_uops_1_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_imm_packed = io_dis_uops_1_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_csr_addr = io_dis_uops_1_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_rob_idx = io_dis_uops_1_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldq_idx = io_dis_uops_1_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_stq_idx = io_dis_uops_1_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_rxq_idx = io_dis_uops_1_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_pdst = io_dis_uops_1_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs1 = io_dis_uops_1_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs2 = io_dis_uops_1_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs3 = io_dis_uops_1_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs1_busy = io_dis_uops_1_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs2_busy = io_dis_uops_1_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs3_busy = io_dis_uops_1_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_stale_pdst = io_dis_uops_1_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_exception = io_dis_uops_1_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_exc_cause = io_dis_uops_1_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_bypassable = io_dis_uops_1_0_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_cmd = io_dis_uops_1_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_size = io_dis_uops_1_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_signed = io_dis_uops_1_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_fence = io_dis_uops_1_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_fencei = io_dis_uops_1_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_amo = io_dis_uops_1_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_uses_ldq = io_dis_uops_1_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_uses_stq = io_dis_uops_1_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_sys_pc2epc = io_dis_uops_1_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_unique = io_dis_uops_1_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_flush_on_commit = io_dis_uops_1_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldst_is_rs1 = io_dis_uops_1_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldst = io_dis_uops_1_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs1 = io_dis_uops_1_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs2 = io_dis_uops_1_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs3 = io_dis_uops_1_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldst_val = io_dis_uops_1_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_dst_rtype = io_dis_uops_1_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs1_rtype = io_dis_uops_1_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs2_rtype = io_dis_uops_1_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_frs3_en = io_dis_uops_1_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_val = io_dis_uops_1_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_single = io_dis_uops_1_0_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_pf_if = io_dis_uops_1_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_ae_if = io_dis_uops_1_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_ma_if = io_dis_uops_1_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_bp_debug_if = io_dis_uops_1_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_bp_xcpt_if = io_dis_uops_1_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_fsrc = io_dis_uops_1_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_tsrc = io_dis_uops_1_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_valid = io_dis_uops_1_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_uopc = io_dis_uops_1_1_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_inst = io_dis_uops_1_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_inst = io_dis_uops_1_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_rvc = io_dis_uops_1_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_pc = io_dis_uops_1_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iq_type = io_dis_uops_1_1_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code = io_dis_uops_1_1_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_br_type = io_dis_uops_1_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_op1_sel = io_dis_uops_1_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_op2_sel = io_dis_uops_1_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_imm_sel = io_dis_uops_1_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_op_fcn = io_dis_uops_1_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_fcn_dw = io_dis_uops_1_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_csr_cmd = io_dis_uops_1_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_is_load = io_dis_uops_1_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_is_sta = io_dis_uops_1_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ctrl_is_std = io_dis_uops_1_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_state = io_dis_uops_1_1_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p1_poisoned = io_dis_uops_1_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p2_poisoned = io_dis_uops_1_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_br = io_dis_uops_1_1_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_jalr = io_dis_uops_1_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_jal = io_dis_uops_1_1_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_sfb = io_dis_uops_1_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_br_mask = io_dis_uops_1_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_br_tag = io_dis_uops_1_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ftq_idx = io_dis_uops_1_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_edge_inst = io_dis_uops_1_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_pc_lob = io_dis_uops_1_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_taken = io_dis_uops_1_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_imm_packed = io_dis_uops_1_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_csr_addr = io_dis_uops_1_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_rob_idx = io_dis_uops_1_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldq_idx = io_dis_uops_1_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_stq_idx = io_dis_uops_1_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_rxq_idx = io_dis_uops_1_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_pdst = io_dis_uops_1_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs1 = io_dis_uops_1_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs2 = io_dis_uops_1_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs3 = io_dis_uops_1_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs1_busy = io_dis_uops_1_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs2_busy = io_dis_uops_1_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs3_busy = io_dis_uops_1_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_stale_pdst = io_dis_uops_1_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_exception = io_dis_uops_1_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_exc_cause = io_dis_uops_1_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_bypassable = io_dis_uops_1_1_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_cmd = io_dis_uops_1_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_size = io_dis_uops_1_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_signed = io_dis_uops_1_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_fence = io_dis_uops_1_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_fencei = io_dis_uops_1_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_amo = io_dis_uops_1_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_uses_ldq = io_dis_uops_1_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_uses_stq = io_dis_uops_1_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_sys_pc2epc = io_dis_uops_1_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_unique = io_dis_uops_1_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_flush_on_commit = io_dis_uops_1_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldst_is_rs1 = io_dis_uops_1_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldst = io_dis_uops_1_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs1 = io_dis_uops_1_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs2 = io_dis_uops_1_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs3 = io_dis_uops_1_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldst_val = io_dis_uops_1_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_dst_rtype = io_dis_uops_1_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs1_rtype = io_dis_uops_1_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs2_rtype = io_dis_uops_1_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_frs3_en = io_dis_uops_1_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_val = io_dis_uops_1_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_single = io_dis_uops_1_1_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_pf_if = io_dis_uops_1_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_ae_if = io_dis_uops_1_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_ma_if = io_dis_uops_1_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_bp_debug_if = io_dis_uops_1_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_bp_xcpt_if = io_dis_uops_1_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_fsrc = io_dis_uops_1_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_tsrc = io_dis_uops_1_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_valid = io_dis_uops_1_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_uopc = io_dis_uops_1_2_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_inst = io_dis_uops_1_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_inst = io_dis_uops_1_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_rvc = io_dis_uops_1_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_pc = io_dis_uops_1_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iq_type = io_dis_uops_1_2_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code = io_dis_uops_1_2_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_br_type = io_dis_uops_1_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_op1_sel = io_dis_uops_1_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_op2_sel = io_dis_uops_1_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_imm_sel = io_dis_uops_1_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_op_fcn = io_dis_uops_1_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_fcn_dw = io_dis_uops_1_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_csr_cmd = io_dis_uops_1_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_is_load = io_dis_uops_1_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_is_sta = io_dis_uops_1_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ctrl_is_std = io_dis_uops_1_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_state = io_dis_uops_1_2_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p1_poisoned = io_dis_uops_1_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p2_poisoned = io_dis_uops_1_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_br = io_dis_uops_1_2_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_jalr = io_dis_uops_1_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_jal = io_dis_uops_1_2_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_sfb = io_dis_uops_1_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_br_mask = io_dis_uops_1_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_br_tag = io_dis_uops_1_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ftq_idx = io_dis_uops_1_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_edge_inst = io_dis_uops_1_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_pc_lob = io_dis_uops_1_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_taken = io_dis_uops_1_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_imm_packed = io_dis_uops_1_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_csr_addr = io_dis_uops_1_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_rob_idx = io_dis_uops_1_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldq_idx = io_dis_uops_1_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_stq_idx = io_dis_uops_1_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_rxq_idx = io_dis_uops_1_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_pdst = io_dis_uops_1_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs1 = io_dis_uops_1_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs2 = io_dis_uops_1_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs3 = io_dis_uops_1_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs1_busy = io_dis_uops_1_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs2_busy = io_dis_uops_1_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs3_busy = io_dis_uops_1_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_stale_pdst = io_dis_uops_1_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_exception = io_dis_uops_1_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_exc_cause = io_dis_uops_1_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_bypassable = io_dis_uops_1_2_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_cmd = io_dis_uops_1_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_size = io_dis_uops_1_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_signed = io_dis_uops_1_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_fence = io_dis_uops_1_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_fencei = io_dis_uops_1_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_amo = io_dis_uops_1_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_uses_ldq = io_dis_uops_1_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_uses_stq = io_dis_uops_1_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_sys_pc2epc = io_dis_uops_1_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_unique = io_dis_uops_1_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_flush_on_commit = io_dis_uops_1_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldst_is_rs1 = io_dis_uops_1_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldst = io_dis_uops_1_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs1 = io_dis_uops_1_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs2 = io_dis_uops_1_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs3 = io_dis_uops_1_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldst_val = io_dis_uops_1_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_dst_rtype = io_dis_uops_1_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs1_rtype = io_dis_uops_1_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs2_rtype = io_dis_uops_1_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_frs3_en = io_dis_uops_1_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_val = io_dis_uops_1_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_single = io_dis_uops_1_2_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_pf_if = io_dis_uops_1_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_ae_if = io_dis_uops_1_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_ma_if = io_dis_uops_1_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_bp_debug_if = io_dis_uops_1_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_bp_xcpt_if = io_dis_uops_1_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_fsrc = io_dis_uops_1_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_tsrc = io_dis_uops_1_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_valid = io_dis_uops_0_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_uopc = io_dis_uops_0_0_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_inst = io_dis_uops_0_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_inst = io_dis_uops_0_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_rvc = io_dis_uops_0_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_pc = io_dis_uops_0_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iq_type = io_dis_uops_0_0_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code = io_dis_uops_0_0_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_br_type = io_dis_uops_0_0_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_op1_sel = io_dis_uops_0_0_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_op2_sel = io_dis_uops_0_0_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_imm_sel = io_dis_uops_0_0_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_op_fcn = io_dis_uops_0_0_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_fcn_dw = io_dis_uops_0_0_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_csr_cmd = io_dis_uops_0_0_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_is_load = io_dis_uops_0_0_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_is_sta = io_dis_uops_0_0_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ctrl_is_std = io_dis_uops_0_0_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_state = io_dis_uops_0_0_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p1_poisoned = io_dis_uops_0_0_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p2_poisoned = io_dis_uops_0_0_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_br = io_dis_uops_0_0_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_jalr = io_dis_uops_0_0_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_jal = io_dis_uops_0_0_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_sfb = io_dis_uops_0_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_br_mask = io_dis_uops_0_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_br_tag = io_dis_uops_0_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ftq_idx = io_dis_uops_0_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_edge_inst = io_dis_uops_0_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_pc_lob = io_dis_uops_0_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_taken = io_dis_uops_0_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_imm_packed = io_dis_uops_0_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_csr_addr = io_dis_uops_0_0_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_rob_idx = io_dis_uops_0_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldq_idx = io_dis_uops_0_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_stq_idx = io_dis_uops_0_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_rxq_idx = io_dis_uops_0_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_pdst = io_dis_uops_0_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs1 = io_dis_uops_0_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs2 = io_dis_uops_0_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs3 = io_dis_uops_0_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs1_busy = io_dis_uops_0_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs2_busy = io_dis_uops_0_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs3_busy = io_dis_uops_0_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_stale_pdst = io_dis_uops_0_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_exception = io_dis_uops_0_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_exc_cause = io_dis_uops_0_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_bypassable = io_dis_uops_0_0_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_cmd = io_dis_uops_0_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_size = io_dis_uops_0_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_signed = io_dis_uops_0_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_fence = io_dis_uops_0_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_fencei = io_dis_uops_0_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_amo = io_dis_uops_0_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_uses_ldq = io_dis_uops_0_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_uses_stq = io_dis_uops_0_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_sys_pc2epc = io_dis_uops_0_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_unique = io_dis_uops_0_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_flush_on_commit = io_dis_uops_0_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldst_is_rs1 = io_dis_uops_0_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldst = io_dis_uops_0_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs1 = io_dis_uops_0_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs2 = io_dis_uops_0_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs3 = io_dis_uops_0_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldst_val = io_dis_uops_0_0_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_dst_rtype = io_dis_uops_0_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs1_rtype = io_dis_uops_0_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs2_rtype = io_dis_uops_0_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_frs3_en = io_dis_uops_0_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_val = io_dis_uops_0_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_single = io_dis_uops_0_0_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_pf_if = io_dis_uops_0_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_ae_if = io_dis_uops_0_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_ma_if = io_dis_uops_0_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_bp_debug_if = io_dis_uops_0_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_bp_xcpt_if = io_dis_uops_0_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_fsrc = io_dis_uops_0_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_tsrc = io_dis_uops_0_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_valid = io_dis_uops_0_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_uopc = io_dis_uops_0_1_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_inst = io_dis_uops_0_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_inst = io_dis_uops_0_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_rvc = io_dis_uops_0_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_pc = io_dis_uops_0_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iq_type = io_dis_uops_0_1_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code = io_dis_uops_0_1_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_br_type = io_dis_uops_0_1_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_op1_sel = io_dis_uops_0_1_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_op2_sel = io_dis_uops_0_1_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_imm_sel = io_dis_uops_0_1_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_op_fcn = io_dis_uops_0_1_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_fcn_dw = io_dis_uops_0_1_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_csr_cmd = io_dis_uops_0_1_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_is_load = io_dis_uops_0_1_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_is_sta = io_dis_uops_0_1_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ctrl_is_std = io_dis_uops_0_1_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_state = io_dis_uops_0_1_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p1_poisoned = io_dis_uops_0_1_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p2_poisoned = io_dis_uops_0_1_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_br = io_dis_uops_0_1_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_jalr = io_dis_uops_0_1_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_jal = io_dis_uops_0_1_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_sfb = io_dis_uops_0_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_br_mask = io_dis_uops_0_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_br_tag = io_dis_uops_0_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ftq_idx = io_dis_uops_0_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_edge_inst = io_dis_uops_0_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_pc_lob = io_dis_uops_0_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_taken = io_dis_uops_0_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_imm_packed = io_dis_uops_0_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_csr_addr = io_dis_uops_0_1_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_rob_idx = io_dis_uops_0_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldq_idx = io_dis_uops_0_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_stq_idx = io_dis_uops_0_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_rxq_idx = io_dis_uops_0_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_pdst = io_dis_uops_0_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs1 = io_dis_uops_0_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs2 = io_dis_uops_0_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs3 = io_dis_uops_0_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs1_busy = io_dis_uops_0_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs2_busy = io_dis_uops_0_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs3_busy = io_dis_uops_0_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_stale_pdst = io_dis_uops_0_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_exception = io_dis_uops_0_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_exc_cause = io_dis_uops_0_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_bypassable = io_dis_uops_0_1_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_cmd = io_dis_uops_0_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_size = io_dis_uops_0_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_signed = io_dis_uops_0_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_fence = io_dis_uops_0_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_fencei = io_dis_uops_0_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_amo = io_dis_uops_0_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_uses_ldq = io_dis_uops_0_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_uses_stq = io_dis_uops_0_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_sys_pc2epc = io_dis_uops_0_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_unique = io_dis_uops_0_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_flush_on_commit = io_dis_uops_0_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldst_is_rs1 = io_dis_uops_0_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldst = io_dis_uops_0_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs1 = io_dis_uops_0_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs2 = io_dis_uops_0_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs3 = io_dis_uops_0_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldst_val = io_dis_uops_0_1_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_dst_rtype = io_dis_uops_0_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs1_rtype = io_dis_uops_0_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs2_rtype = io_dis_uops_0_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_frs3_en = io_dis_uops_0_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_val = io_dis_uops_0_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_single = io_dis_uops_0_1_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_pf_if = io_dis_uops_0_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_ae_if = io_dis_uops_0_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_ma_if = io_dis_uops_0_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_bp_debug_if = io_dis_uops_0_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_bp_xcpt_if = io_dis_uops_0_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_fsrc = io_dis_uops_0_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_tsrc = io_dis_uops_0_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_valid = io_dis_uops_0_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_uopc = io_dis_uops_0_2_bits_uopc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_inst = io_dis_uops_0_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_inst = io_dis_uops_0_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_rvc = io_dis_uops_0_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_pc = io_dis_uops_0_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iq_type = io_dis_uops_0_2_bits_iq_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code = io_dis_uops_0_2_bits_fu_code_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_br_type = io_dis_uops_0_2_bits_ctrl_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_op1_sel = io_dis_uops_0_2_bits_ctrl_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_op2_sel = io_dis_uops_0_2_bits_ctrl_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_imm_sel = io_dis_uops_0_2_bits_ctrl_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_op_fcn = io_dis_uops_0_2_bits_ctrl_op_fcn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_fcn_dw = io_dis_uops_0_2_bits_ctrl_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_csr_cmd = io_dis_uops_0_2_bits_ctrl_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_is_load = io_dis_uops_0_2_bits_ctrl_is_load_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_is_sta = io_dis_uops_0_2_bits_ctrl_is_sta_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ctrl_is_std = io_dis_uops_0_2_bits_ctrl_is_std_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_state = io_dis_uops_0_2_bits_iw_state_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p1_poisoned = io_dis_uops_0_2_bits_iw_p1_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p2_poisoned = io_dis_uops_0_2_bits_iw_p2_poisoned_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_br = io_dis_uops_0_2_bits_is_br_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_jalr = io_dis_uops_0_2_bits_is_jalr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_jal = io_dis_uops_0_2_bits_is_jal_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_sfb = io_dis_uops_0_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_br_mask = io_dis_uops_0_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_br_tag = io_dis_uops_0_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ftq_idx = io_dis_uops_0_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_edge_inst = io_dis_uops_0_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_pc_lob = io_dis_uops_0_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_taken = io_dis_uops_0_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_imm_packed = io_dis_uops_0_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_csr_addr = io_dis_uops_0_2_bits_csr_addr_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_rob_idx = io_dis_uops_0_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldq_idx = io_dis_uops_0_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_stq_idx = io_dis_uops_0_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_rxq_idx = io_dis_uops_0_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_pdst = io_dis_uops_0_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs1 = io_dis_uops_0_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs2 = io_dis_uops_0_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs3 = io_dis_uops_0_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs1_busy = io_dis_uops_0_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs2_busy = io_dis_uops_0_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs3_busy = io_dis_uops_0_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_stale_pdst = io_dis_uops_0_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_exception = io_dis_uops_0_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_exc_cause = io_dis_uops_0_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_bypassable = io_dis_uops_0_2_bits_bypassable_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_cmd = io_dis_uops_0_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_size = io_dis_uops_0_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_signed = io_dis_uops_0_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_fence = io_dis_uops_0_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_fencei = io_dis_uops_0_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_amo = io_dis_uops_0_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_uses_ldq = io_dis_uops_0_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_uses_stq = io_dis_uops_0_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_sys_pc2epc = io_dis_uops_0_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_unique = io_dis_uops_0_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_flush_on_commit = io_dis_uops_0_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldst_is_rs1 = io_dis_uops_0_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldst = io_dis_uops_0_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs1 = io_dis_uops_0_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs2 = io_dis_uops_0_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs3 = io_dis_uops_0_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldst_val = io_dis_uops_0_2_bits_ldst_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_dst_rtype = io_dis_uops_0_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs1_rtype = io_dis_uops_0_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs2_rtype = io_dis_uops_0_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_frs3_en = io_dis_uops_0_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_val = io_dis_uops_0_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_single = io_dis_uops_0_2_bits_fp_single_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_pf_if = io_dis_uops_0_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_ae_if = io_dis_uops_0_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_ma_if = io_dis_uops_0_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_bp_debug_if = io_dis_uops_0_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_bp_xcpt_if = io_dis_uops_0_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_fsrc = io_dis_uops_0_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_tsrc = io_dis_uops_0_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_135( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_108( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_105( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_329( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_269( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_501 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_157( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_178 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_83( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2049:0] _c_sizes_set_T_1 = 2050'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [639:0] c_opcodes_set = 640'h0; // @[Monitor.scala:740:34]
wire [639:0] c_sizes_set = 640'h0; // @[Monitor.scala:741:34]
wire [159:0] c_set = 160'h0; // @[Monitor.scala:738:34]
wire [159:0] c_set_wo_ready = 160'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [159:0] inflight; // @[Monitor.scala:614:27]
reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [639:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [159:0] a_set; // @[Monitor.scala:626:34]
wire [159:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [639:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [639:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [159:0] d_clr; // @[Monitor.scala:664:34]
wire [159:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [639:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [639:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [159:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [159:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [159:0] inflight_1; // @[Monitor.scala:726:35]
wire [159:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [639:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [159:0] d_clr_1; // @[Monitor.scala:774:34]
wire [159:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [639:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [639:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [159:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_185( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_263( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1753 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1753; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1753; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1821 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1821; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1821; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1821; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1686 = _T_1753 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1686 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1686 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1686 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1686 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1686 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1732 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1732 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1701 = _T_1821 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1701 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1701 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1701 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1797 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1797 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1779 = _T_1821 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1779 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1779 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1779 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File DivSqrtRecF64_mulAddZ31.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.{Cat, Fill}
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for standard 64-bit floating-point in
| recoded form, using a separate integer multiplier-adder. Multiple clock
| cycles are needed for each division or square-root operation. See
| "docs/DivSqrtRecF64_mulAddZ31.txt" for more details.
*----------------------------------------------------------------------------*/
class DivSqrtRecF64ToRaw_mulAddZ31 extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
//*** OPTIONALLY PROPAGATE:
// val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(11, 55))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum_A = RegInit(0.U(3.W))
val cycleNum_B = RegInit(0.U(4.W))
val cycleNum_C = RegInit(0.U(3.W))
val cycleNum_E = RegInit(0.U(3.W))
val valid_PA = RegInit(false.B)
val sqrtOp_PA = Reg(Bool())
val majorExc_PA = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PA = Reg(Bool())
val isInf_PA = Reg(Bool())
val isZero_PA = Reg(Bool())
val sign_PA = Reg(Bool())
val sExp_PA = Reg(SInt(13.W))
val fractB_PA = Reg(UInt(52.W))
val fractA_PA = Reg(UInt(52.W))
val roundingMode_PA = Reg(UInt(3.W))
val valid_PB = RegInit(false.B)
val sqrtOp_PB = Reg(Bool())
val majorExc_PB = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PB = Reg(Bool())
val isInf_PB = Reg(Bool())
val isZero_PB = Reg(Bool())
val sign_PB = Reg(Bool())
val sExp_PB = Reg(SInt(13.W))
val bit0FractA_PB = Reg(UInt(1.W))
val fractB_PB = Reg(UInt(52.W))
val roundingMode_PB = Reg(UInt(3.W))
val valid_PC = RegInit(false.B)
val sqrtOp_PC = Reg(Bool())
val majorExc_PC = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_PC = Reg(Bool())
val isInf_PC = Reg(Bool())
val isZero_PC = Reg(Bool())
val sign_PC = Reg(Bool())
val sExp_PC = Reg(SInt(13.W))
val bit0FractA_PC = Reg(UInt(1.W))
val fractB_PC = Reg(UInt(52.W))
val roundingMode_PC = Reg(UInt(3.W))
val fractR0_A = Reg(UInt(9.W))
//*** COMBINE 'hiSqrR0_A_sqrt' AND 'partNegSigma0_A'?
val hiSqrR0_A_sqrt = Reg(UInt(10.W))
val partNegSigma0_A = Reg(UInt(21.W))
val nextMulAdd9A_A = Reg(UInt(9.W))
val nextMulAdd9B_A = Reg(UInt(9.W))
val ER1_B_sqrt = Reg(UInt(17.W))
val ESqrR1_B_sqrt = Reg(UInt(32.W))
val sigX1_B = Reg(UInt(58.W))
val sqrSigma1_C = Reg(UInt(33.W))
val sigXN_C = Reg(UInt(58.W))
val u_C_sqrt = Reg(UInt(31.W))
val E_E_div = Reg(Bool())
val sigT_E = Reg(UInt(54.W))
val isNegRemT_E = Reg(Bool())
val isZeroRemT_E = Reg(Bool())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val ready_PA = Wire(Bool())
val ready_PB = Wire(Bool())
val ready_PC = Wire(Bool())
val leaving_PA = Wire(Bool())
val leaving_PB = Wire(Bool())
val leaving_PC = Wire(Bool())
val zSigma1_B4 = Wire(UInt())
val sigXNU_B3_CX = Wire(UInt())
val zComplSigT_C1_sqrt = Wire(UInt())
val zComplSigT_C1 = Wire(UInt())
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cyc_S_div = io.inReady_div && io.inValid && ! io.sqrtOp
val cyc_S_sqrt = io.inReady_sqrt && io.inValid && io.sqrtOp
val cyc_S = cyc_S_div || cyc_S_sqrt
val rawA_S = rawFloatFromRecFN(11, 53, io.a)
val rawB_S = rawFloatFromRecFN(11, 53, io.b)
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawB_S.isNaN && ! rawB_S.isZero && rawB_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawB_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawB_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawB_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = (! io.sqrtOp && rawA_S.sign) ^ rawB_S.sign
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseB_S && ! rawB_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +& (rawB_S.sExp(11) ## ~rawB_S.sExp(10, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
(Mux(((7<<9).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(12, 9)
) ##
sExpQuot_S_div(8, 0)
).asSInt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA_normalCase_div = cyc_S_div && normalCase_S_div
val entering_PA_normalCase_sqrt = cyc_S_sqrt && normalCase_S_sqrt
val entering_PA_normalCase =
entering_PA_normalCase_div || entering_PA_normalCase_sqrt
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering_PA_normalCase || (cycleNum_A =/= 0.U)) {
cycleNum_A :=
Mux(entering_PA_normalCase_div, 3.U, 0.U) |
Mux(entering_PA_normalCase_sqrt, 6.U, 0.U) |
Mux(! entering_PA_normalCase, cycleNum_A - 1.U, 0.U)
}
val cyc_A7_sqrt = entering_PA_normalCase_sqrt
val cyc_A6_sqrt = (cycleNum_A === 6.U)
val cyc_A5_sqrt = (cycleNum_A === 5.U)
val cyc_A4_sqrt = (cycleNum_A === 4.U)
val cyc_A4_div = entering_PA_normalCase_div
val cyc_A4 = cyc_A4_sqrt || cyc_A4_div
val cyc_A3 = (cycleNum_A === 3.U)
val cyc_A2 = (cycleNum_A === 2.U)
val cyc_A1 = (cycleNum_A === 1.U)
val cyc_A3_div = cyc_A3 && ! sqrtOp_PA
val cyc_A2_div = cyc_A2 && ! sqrtOp_PA
val cyc_A1_div = cyc_A1 && ! sqrtOp_PA
val cyc_A3_sqrt = cyc_A3 && sqrtOp_PA
val cyc_A2_sqrt = cyc_A2 && sqrtOp_PA
val cyc_A1_sqrt = cyc_A1 && sqrtOp_PA
when (cyc_A1 || (cycleNum_B =/= 0.U)) {
cycleNum_B :=
Mux(cyc_A1,
Mux(sqrtOp_PA, 10.U, 6.U),
cycleNum_B - 1.U
)
}
val cyc_B10_sqrt = (cycleNum_B === 10.U)
val cyc_B9_sqrt = (cycleNum_B === 9.U)
val cyc_B8_sqrt = (cycleNum_B === 8.U)
val cyc_B7_sqrt = (cycleNum_B === 7.U)
val cyc_B6 = (cycleNum_B === 6.U)
val cyc_B5 = (cycleNum_B === 5.U)
val cyc_B4 = (cycleNum_B === 4.U)
val cyc_B3 = (cycleNum_B === 3.U)
val cyc_B2 = (cycleNum_B === 2.U)
val cyc_B1 = (cycleNum_B === 1.U)
val cyc_B6_div = cyc_B6 && valid_PA && ! sqrtOp_PA
val cyc_B5_div = cyc_B5 && valid_PA && ! sqrtOp_PA
val cyc_B4_div = cyc_B4 && valid_PA && ! sqrtOp_PA
val cyc_B3_div = cyc_B3 && ! sqrtOp_PB
val cyc_B2_div = cyc_B2 && ! sqrtOp_PB
val cyc_B1_div = cyc_B1 && ! sqrtOp_PB
val cyc_B6_sqrt = cyc_B6 && valid_PB && sqrtOp_PB
val cyc_B5_sqrt = cyc_B5 && valid_PB && sqrtOp_PB
val cyc_B4_sqrt = cyc_B4 && valid_PB && sqrtOp_PB
val cyc_B3_sqrt = cyc_B3 && sqrtOp_PB
val cyc_B2_sqrt = cyc_B2 && sqrtOp_PB
val cyc_B1_sqrt = cyc_B1 && sqrtOp_PB
when (cyc_B1 || (cycleNum_C =/= 0.U)) {
cycleNum_C :=
Mux(cyc_B1, Mux(sqrtOp_PB, 6.U, 5.U), cycleNum_C - 1.U)
}
val cyc_C6_sqrt = (cycleNum_C === 6.U)
val cyc_C5 = (cycleNum_C === 5.U)
val cyc_C4 = (cycleNum_C === 4.U)
val cyc_C3 = (cycleNum_C === 3.U)
val cyc_C2 = (cycleNum_C === 2.U)
val cyc_C1 = (cycleNum_C === 1.U)
val cyc_C5_div = cyc_C5 && ! sqrtOp_PB
val cyc_C4_div = cyc_C4 && ! sqrtOp_PB
val cyc_C3_div = cyc_C3 && ! sqrtOp_PB
val cyc_C2_div = cyc_C2 && ! sqrtOp_PC
val cyc_C1_div = cyc_C1 && ! sqrtOp_PC
val cyc_C5_sqrt = cyc_C5 && sqrtOp_PB
val cyc_C4_sqrt = cyc_C4 && sqrtOp_PB
val cyc_C3_sqrt = cyc_C3 && sqrtOp_PB
val cyc_C2_sqrt = cyc_C2 && sqrtOp_PC
val cyc_C1_sqrt = cyc_C1 && sqrtOp_PC
when (cyc_C1 || (cycleNum_E =/= 0.U)) {
cycleNum_E := Mux(cyc_C1, 4.U, cycleNum_E - 1.U)
}
val cyc_E4 = (cycleNum_E === 4.U)
val cyc_E3 = (cycleNum_E === 3.U)
val cyc_E2 = (cycleNum_E === 2.U)
val cyc_E1 = (cycleNum_E === 1.U)
val cyc_E4_div = cyc_E4 && ! sqrtOp_PC
val cyc_E3_div = cyc_E3 && ! sqrtOp_PC
val cyc_E2_div = cyc_E2 && ! sqrtOp_PC
val cyc_E1_div = cyc_E1 && ! sqrtOp_PC
val cyc_E4_sqrt = cyc_E4 && sqrtOp_PC
val cyc_E3_sqrt = cyc_E3 && sqrtOp_PC
val cyc_E2_sqrt = cyc_E2 && sqrtOp_PC
val cyc_E1_sqrt = cyc_E1 && sqrtOp_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PA =
entering_PA_normalCase || (cyc_S && (valid_PA || ! ready_PB))
when (entering_PA || leaving_PA) {
valid_PA := entering_PA
}
when (entering_PA) {
sqrtOp_PA := io.sqrtOp
majorExc_PA := majorExc_S
isNaN_PA := isNaN_S
isInf_PA := isInf_S
isZero_PA := isZero_S
sign_PA := sign_S
}
when (entering_PA_normalCase) {
sExp_PA := Mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div)
fractB_PA := rawB_S.sig(51, 0)
roundingMode_PA := io.roundingMode
}
when (entering_PA_normalCase_div) {
fractA_PA := rawA_S.sig(51, 0)
}
val normalCase_PA = ! isNaN_PA && ! isInf_PA && ! isZero_PA
val sigA_PA = 1.U(1.W) ## fractA_PA
val sigB_PA = 1.U(1.W) ## fractB_PA
val valid_normalCase_leaving_PA = cyc_B4_div || cyc_B7_sqrt
val valid_leaving_PA =
Mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)
leaving_PA := valid_PA && valid_leaving_PA
ready_PA := ! valid_PA || valid_leaving_PA
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PB_S =
cyc_S && ! normalCase_S && ! valid_PA &&
(leaving_PB || (! valid_PB && ! ready_PC))
val entering_PB_normalCase =
valid_PA && normalCase_PA && valid_normalCase_leaving_PA
val entering_PB = entering_PB_S || leaving_PA
when (entering_PB || leaving_PB) {
valid_PB := entering_PB
}
when (entering_PB) {
sqrtOp_PB := Mux(valid_PA, sqrtOp_PA, io.sqrtOp )
majorExc_PB := Mux(valid_PA, majorExc_PA, majorExc_S)
isNaN_PB := Mux(valid_PA, isNaN_PA, isNaN_S )
isInf_PB := Mux(valid_PA, isInf_PA, isInf_S )
isZero_PB := Mux(valid_PA, isZero_PA, isZero_S )
sign_PB := Mux(valid_PA, sign_PA, sign_S )
}
when (entering_PB_normalCase) {
sExp_PB := sExp_PA
bit0FractA_PB := fractA_PA(0)
fractB_PB := fractB_PA
roundingMode_PB := Mux(valid_PA, roundingMode_PA, io.roundingMode)
}
val normalCase_PB = ! isNaN_PB && ! isInf_PB && ! isZero_PB
val valid_normalCase_leaving_PB = cyc_C3
val valid_leaving_PB =
Mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)
leaving_PB := valid_PB && valid_leaving_PB
ready_PB := ! valid_PB || valid_leaving_PB
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val entering_PC_S =
cyc_S && ! normalCase_S && ! valid_PA && ! valid_PB && ready_PC
val entering_PC_normalCase =
valid_PB && normalCase_PB && valid_normalCase_leaving_PB
val entering_PC = entering_PC_S || leaving_PB
when (entering_PC || leaving_PC) {
valid_PC := entering_PC
}
when (entering_PC) {
sqrtOp_PC := Mux(valid_PB, sqrtOp_PB, io.sqrtOp )
majorExc_PC := Mux(valid_PB, majorExc_PB, majorExc_S)
isNaN_PC := Mux(valid_PB, isNaN_PB, isNaN_S )
isInf_PC := Mux(valid_PB, isInf_PB, isInf_S )
isZero_PC := Mux(valid_PB, isZero_PB, isZero_S )
sign_PC := Mux(valid_PB, sign_PB, sign_S )
}
when (entering_PC_normalCase) {
sExp_PC := sExp_PB
bit0FractA_PC := bit0FractA_PB
fractB_PC := fractB_PB
roundingMode_PC := Mux(valid_PB, roundingMode_PB, io.roundingMode)
}
val normalCase_PC = ! isNaN_PC && ! isInf_PC && ! isZero_PC
val sigB_PC = 1.U(1.W) ## fractB_PC
val valid_leaving_PC = ! normalCase_PC || cyc_E1
leaving_PC := valid_PC && valid_leaving_PC
ready_PC := ! valid_PC || valid_leaving_PC
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
//*** NEED TO COMPUTE AS MUCH AS POSSIBLE IN PREVIOUS CYCLE?:
io.inReady_div :=
//*** REPLACE ALL OF '! cyc_B*_sqrt' BY '! (valid_PB && sqrtOp_PB)'?:
ready_PA && ! cyc_B7_sqrt && ! cyc_B6_sqrt && ! cyc_B5_sqrt &&
! cyc_B4_sqrt && ! cyc_B3 && ! cyc_B2 && ! cyc_B1_sqrt &&
! cyc_C5 && ! cyc_C4
io.inReady_sqrt :=
ready_PA && ! cyc_B6_sqrt && ! cyc_B5_sqrt && ! cyc_B4_sqrt &&
! cyc_B2_div && ! cyc_B1_sqrt
/*------------------------------------------------------------------------
| Macrostage A, built around a 9x9-bit multiplier-adder.
*------------------------------------------------------------------------*/
val zFractB_A4_div = Mux(cyc_A4_div, rawB_S.sig(51, 0), 0.U)
val zLinPiece_0_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 0.U)
val zLinPiece_1_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 1.U)
val zLinPiece_2_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 2.U)
val zLinPiece_3_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 3.U)
val zLinPiece_4_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 4.U)
val zLinPiece_5_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 5.U)
val zLinPiece_6_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 6.U)
val zLinPiece_7_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 7.U)
val zK1_A4_div =
Mux(zLinPiece_0_A4_div, "h1C7".U, 0.U) |
Mux(zLinPiece_1_A4_div, "h16C".U, 0.U) |
Mux(zLinPiece_2_A4_div, "h12A".U, 0.U) |
Mux(zLinPiece_3_A4_div, "h0F8".U, 0.U) |
Mux(zLinPiece_4_A4_div, "h0D2".U, 0.U) |
Mux(zLinPiece_5_A4_div, "h0B4".U, 0.U) |
Mux(zLinPiece_6_A4_div, "h09C".U, 0.U) |
Mux(zLinPiece_7_A4_div, "h089".U, 0.U)
val zComplFractK0_A4_div =
Mux(zLinPiece_0_A4_div, ~"hFE3".U(12.W), 0.U) |
Mux(zLinPiece_1_A4_div, ~"hC5D".U(12.W), 0.U) |
Mux(zLinPiece_2_A4_div, ~"h98A".U(12.W), 0.U) |
Mux(zLinPiece_3_A4_div, ~"h739".U(12.W), 0.U) |
Mux(zLinPiece_4_A4_div, ~"h54B".U(12.W), 0.U) |
Mux(zLinPiece_5_A4_div, ~"h3A9".U(12.W), 0.U) |
Mux(zLinPiece_6_A4_div, ~"h242".U(12.W), 0.U) |
Mux(zLinPiece_7_A4_div, ~"h10B".U(12.W), 0.U)
val zFractB_A7_sqrt = Mux(cyc_A7_sqrt, rawB_S.sig(51, 0), 0.U)
val zQuadPiece_0_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_1_A7_sqrt =
cyc_A7_sqrt && ! rawB_S.sExp(0) && rawB_S.sig(51)
val zQuadPiece_2_A7_sqrt =
cyc_A7_sqrt && rawB_S.sExp(0) && ! rawB_S.sig(51)
val zQuadPiece_3_A7_sqrt = cyc_A7_sqrt && rawB_S.sExp(0) && rawB_S.sig(51)
val zK2_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, "h1C8".U, 0.U) |
Mux(zQuadPiece_1_A7_sqrt, "h0C1".U, 0.U) |
Mux(zQuadPiece_2_A7_sqrt, "h143".U, 0.U) |
Mux(zQuadPiece_3_A7_sqrt, "h089".U, 0.U)
val zComplK1_A7_sqrt =
Mux(zQuadPiece_0_A7_sqrt, ~"h3D0".U(10.W), 0.U) |
Mux(zQuadPiece_1_A7_sqrt, ~"h220".U(10.W), 0.U) |
Mux(zQuadPiece_2_A7_sqrt, ~"h2B2".U(10.W), 0.U) |
Mux(zQuadPiece_3_A7_sqrt, ~"h181".U(10.W), 0.U)
val zQuadPiece_0_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_1_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && sigB_PA(51)
val zQuadPiece_2_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && ! sigB_PA(51)
val zQuadPiece_3_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && sigB_PA(51)
val zComplFractK0_A6_sqrt =
Mux(zQuadPiece_0_A6_sqrt, ~"h1FE5".U(13.W), 0.U) |
Mux(zQuadPiece_1_A6_sqrt, ~"h1435".U(13.W), 0.U) |
Mux(zQuadPiece_2_A6_sqrt, ~"h0D2C".U(13.W), 0.U) |
Mux(zQuadPiece_3_A6_sqrt, ~"h04E8".U(13.W), 0.U)
val mulAdd9A_A =
zFractB_A4_div(48, 40) | zK2_A7_sqrt |
Mux(! cyc_S, nextMulAdd9A_A, 0.U)
val mulAdd9B_A =
zK1_A4_div | zFractB_A7_sqrt(50, 42) |
Mux(! cyc_S, nextMulAdd9B_A, 0.U)
val mulAdd9C_A =
//*** ADJUST CONSTANTS SO 'Fill'S AREN'T NEEDED:
zComplK1_A7_sqrt ## Fill(10, cyc_A7_sqrt) |
Cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt, Fill(6, cyc_A6_sqrt)) |
Cat(cyc_A4_div, zComplFractK0_A4_div, Fill(8, cyc_A4_div )) |
Mux(cyc_A5_sqrt, (1<<18).U +& (fractR0_A<<10), 0.U) |
Mux(cyc_A4_sqrt && ! hiSqrR0_A_sqrt(9), (1<<10).U, 0.U) |
Mux((cyc_A4_sqrt && hiSqrR0_A_sqrt(9)) || cyc_A3_div,
sigB_PA(46, 26) + (1<<10).U,
0.U
) |
Mux(cyc_A3_sqrt || cyc_A2, partNegSigma0_A, 0.U) |
Mux(cyc_A1_sqrt, fractR0_A<<16, 0.U) |
Mux(cyc_A1_div, fractR0_A<<15, 0.U)
val loMulAdd9Out_A = mulAdd9A_A * mulAdd9B_A +& mulAdd9C_A(17, 0)
val mulAdd9Out_A =
Cat(Mux(loMulAdd9Out_A(18),
mulAdd9C_A(24, 18) + 1.U,
mulAdd9C_A(24, 18)
),
loMulAdd9Out_A(17, 0)
)
val zFractR0_A6_sqrt =
Mux(cyc_A6_sqrt && mulAdd9Out_A(19), ~(mulAdd9Out_A>>10), 0.U)
/*------------------------------------------------------------------------
| ('sqrR0_A5_sqrt' is usually >= 1, but not always.)
*------------------------------------------------------------------------*/
val sqrR0_A5_sqrt = Mux(sExp_PA(0), mulAdd9Out_A<<1, mulAdd9Out_A)
val zFractR0_A4_div =
Mux(cyc_A4_div && mulAdd9Out_A(20), ~(mulAdd9Out_A>>11), 0.U)
val zSigma0_A2 =
Mux(cyc_A2 && mulAdd9Out_A(11), ~(mulAdd9Out_A>>2), 0.U)
val r1_A1 = (1<<15).U | Mux(sqrtOp_PA, mulAdd9Out_A>>10, mulAdd9Out_A>>9)
val ER1_A1_sqrt = Mux(sExp_PA(0), r1_A1<<1, r1_A1)
when (cyc_A6_sqrt || cyc_A4_div) {
fractR0_A := zFractR0_A6_sqrt | zFractR0_A4_div
}
when (cyc_A5_sqrt) {
hiSqrR0_A_sqrt := sqrR0_A5_sqrt>>10
}
when (cyc_A4_sqrt || cyc_A3) {
partNegSigma0_A := Mux(cyc_A4_sqrt, mulAdd9Out_A, mulAdd9Out_A>>9)
}
when (
cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A3 || cyc_A2
) {
nextMulAdd9A_A :=
Mux(cyc_A7_sqrt, ~mulAdd9Out_A>>11, 0.U) |
zFractR0_A6_sqrt |
Mux(cyc_A4_sqrt, sigB_PA(43, 35), 0.U) |
zFractB_A4_div(43, 35) |
Mux(cyc_A5_sqrt || cyc_A3, sigB_PA(52, 44), 0.U) |
zSigma0_A2
}
when (cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A2) {
nextMulAdd9B_A :=
zFractB_A7_sqrt(50, 42) |
zFractR0_A6_sqrt |
Mux(cyc_A5_sqrt, sqrR0_A5_sqrt(9, 1), 0.U) |
zFractR0_A4_div |
Mux(cyc_A4_sqrt, hiSqrR0_A_sqrt(8, 0), 0.U) |
Mux(cyc_A2, Cat(1.U(1.W), fractR0_A(8, 1)), 0.U)
}
when (cyc_A1_sqrt) {
ER1_B_sqrt := ER1_A1_sqrt
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.latchMulAddA_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_div || cyc_B4 || cyc_B3 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddA_0 :=
Mux(cyc_A1_sqrt, ER1_A1_sqrt<<36, 0.U) | // 52:36
Mux(cyc_B7_sqrt || cyc_A1_div, sigB_PA, 0.U) | // 52:0
Mux(cyc_B6_div, sigA_PA, 0.U) | // 52:0
zSigma1_B4(45, 12) | // 33:0
//*** ONLY 30 BITS NEEDED IN CYCLE C6:
Mux(cyc_B3 || cyc_C6_sqrt, sigXNU_B3_CX(57, 12), 0.U) | // 45:0
Mux(cyc_C4_div, sigXN_C(57, 25)<<13, 0.U) | // 45:13
Mux(cyc_C4_sqrt, u_C_sqrt<<15, 0.U) | // 45:15
Mux(cyc_C1_div, sigB_PC, 0.U) | // 52:0
zComplSigT_C1_sqrt // 53:0
io.latchMulAddB_0 :=
cyc_A1 || cyc_B7_sqrt || cyc_B6_sqrt || cyc_B4 ||
cyc_C6_sqrt || cyc_C4 || cyc_C1
io.mulAddB_0 :=
Mux(cyc_A1, r1_A1<<36, 0.U) | // 51:36
Mux(cyc_B7_sqrt, ESqrR1_B_sqrt<<19, 0.U) | // 50:19
Mux(cyc_B6_sqrt, ER1_B_sqrt<<36, 0.U) | // 52:36
zSigma1_B4 | // 45:0
Mux(cyc_C6_sqrt, sqrSigma1_C(30, 1), 0.U) | // 29:0
Mux(cyc_C4, sqrSigma1_C, 0.U) | // 32:0
zComplSigT_C1 // 53:0
io.usingMulAdd :=
Cat(cyc_A4 || cyc_A3_div || cyc_A1_div ||
cyc_B10_sqrt || cyc_B9_sqrt || cyc_B7_sqrt || cyc_B6 ||
cyc_B5_sqrt || cyc_B3_sqrt || cyc_B2_div || cyc_B1_sqrt ||
cyc_C4,
cyc_A3 || cyc_A2_div ||
cyc_B9_sqrt || cyc_B8_sqrt || cyc_B6 || cyc_B5 ||
cyc_B4_sqrt || cyc_B2_sqrt || cyc_B1_div || cyc_C6_sqrt ||
cyc_C3,
cyc_A2 || cyc_A1_div ||
cyc_B8_sqrt || cyc_B7_sqrt || cyc_B5 || cyc_B4 ||
cyc_B3_sqrt || cyc_B1_sqrt || cyc_C5 ||
cyc_C2,
io.latchMulAddA_0 || cyc_B6 || cyc_B2_sqrt
)
io.mulAddC_2 :=
Mux(cyc_B1, sigX1_B<<47, 0.U) |
Mux(cyc_C6_sqrt, sigX1_B<<46, 0.U) |
Mux(cyc_C4_sqrt || cyc_C2, sigXN_C<<47, 0.U) |
Mux(cyc_E3_div && ! E_E_div, bit0FractA_PC<<53, 0.U) |
Mux(cyc_E3_sqrt,
(Mux(sExp_PC(0),
sigB_PC(0)<<1,
(sigB_PC(1) ^ sigB_PC(0)) ## sigB_PC(0)
) ^ ((~ sigT_E(0))<<1)
)<<54,
0.U
)
val ESqrR1_B8_sqrt = io.mulAddResult_3(103, 72)
zSigma1_B4 := Mux(cyc_B4, ~io.mulAddResult_3(90, 45), 0.U)
val sqrSigma1_B1 = io.mulAddResult_3(79, 47)
sigXNU_B3_CX := io.mulAddResult_3(104, 47) // x1, x2, u (sqrt), xT'
val E_C1_div = ! io.mulAddResult_3(104)
zComplSigT_C1 :=
Mux((cyc_C1_div && ! E_C1_div) || cyc_C1_sqrt,
~io.mulAddResult_3(104, 51),
0.U
) |
Mux(cyc_C1_div && E_C1_div, ~io.mulAddResult_3(102, 50), 0.U)
zComplSigT_C1_sqrt :=
Mux(cyc_C1_sqrt, ~io.mulAddResult_3(104, 51), 0.U)
/*------------------------------------------------------------------------
| (For square root, 'sigT_C1' will usually be >= 1, but not always.)
*------------------------------------------------------------------------*/
val sigT_C1 = ~zComplSigT_C1
val remT_E2 = io.mulAddResult_3(55, 0)
when (cyc_B8_sqrt) {
ESqrR1_B_sqrt := ESqrR1_B8_sqrt
}
when (cyc_B3) {
sigX1_B := sigXNU_B3_CX
}
when (cyc_B1) {
sqrSigma1_C := sqrSigma1_B1
}
when (cyc_C6_sqrt || cyc_C5_div || cyc_C3_sqrt) {
sigXN_C := sigXNU_B3_CX
}
when (cyc_C5_sqrt) {
u_C_sqrt := sigXNU_B3_CX(56, 26)
}
when (cyc_C1) {
E_E_div := E_C1_div
sigT_E := sigT_C1
}
when (cyc_E2) {
isNegRemT_E := Mux(sqrtOp_PC, remT_E2(55), remT_E2(53))
isZeroRemT_E :=
(remT_E2(53, 0) === 0.U) &&
(! sqrtOp_PC || (remT_E2(55, 54) === 0.U))
}
/*------------------------------------------------------------------------
| T is the lower-bound "trial" result value, with 54 bits of precision.
| It is known that the true unrounded result is within the range of
| (T, T + (2 ulps of 54 bits)). X is defined as the best estimate,
| = T + (1 ulp), which is exactly in the middle of the possible range.
*------------------------------------------------------------------------*/
val trueLtX_E1 =
Mux(sqrtOp_PC, ! isNegRemT_E && ! isZeroRemT_E, isNegRemT_E)
val trueEqX_E1 = isZeroRemT_E
/*------------------------------------------------------------------------
| The inputs to these two values are stable for several clock cycles in
| advance, so the circuitry can be minimized at the expense of speed.
*** ANY WAY TO TELL THIS TO THE TOOLS?
*------------------------------------------------------------------------*/
val sExpP1_PC = sExp_PC + 1.S
val sigTP1_E = sigT_E +& 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := leaving_PC && ! sqrtOp_PC
io.rawOutValid_sqrt := leaving_PC && sqrtOp_PC
io.roundingModeOut := roundingMode_PC
io.invalidExc := majorExc_PC && isNaN_PC
io.infiniteExc := majorExc_PC && ! isNaN_PC
io.rawOut.isNaN := isNaN_PC
io.rawOut.isInf := isInf_PC
io.rawOut.isZero := isZero_PC
io.rawOut.sign := sign_PC
io.rawOut.sExp :=
Mux(! sqrtOp_PC && E_E_div, sExp_PC, 0.S) |
Mux(! sqrtOp_PC && ! E_E_div, sExpP1_PC, 0.S) |
Mux( sqrtOp_PC, (sExp_PC>>1) +& 1024.S, 0.S)
io.rawOut.sig := Mux(trueLtX_E1, sigT_E, sigTP1_E) ## ! trueEqX_E1
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class DivSqrtRecF64_mulAddZ31(options: Int) extends Module
{
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady_div = Output(Bool())
val inReady_sqrt = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(Bits(65.W))
val b = Input(Bits(65.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val usingMulAdd = Output(Bits(4.W))
val latchMulAddA_0 = Output(Bool())
val mulAddA_0 = Output(UInt(54.W))
val latchMulAddB_0 = Output(Bool())
val mulAddB_0 = Output(UInt(54.W))
val mulAddC_2 = Output(UInt(105.W))
val mulAddResult_3 = Input(UInt(105.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(Bits(65.W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecF64ToRaw = Module(new DivSqrtRecF64ToRaw_mulAddZ31)
io.inReady_div := divSqrtRecF64ToRaw.io.inReady_div
io.inReady_sqrt := divSqrtRecF64ToRaw.io.inReady_sqrt
divSqrtRecF64ToRaw.io.inValid := io.inValid
divSqrtRecF64ToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecF64ToRaw.io.a := io.a
divSqrtRecF64ToRaw.io.b := io.b
divSqrtRecF64ToRaw.io.roundingMode := io.roundingMode
io.usingMulAdd := divSqrtRecF64ToRaw.io.usingMulAdd
io.latchMulAddA_0 := divSqrtRecF64ToRaw.io.latchMulAddA_0
io.mulAddA_0 := divSqrtRecF64ToRaw.io.mulAddA_0
io.latchMulAddB_0 := divSqrtRecF64ToRaw.io.latchMulAddB_0
io.mulAddB_0 := divSqrtRecF64ToRaw.io.mulAddB_0
io.mulAddC_2 := divSqrtRecF64ToRaw.io.mulAddC_2
divSqrtRecF64ToRaw.io.mulAddResult_3 := io.mulAddResult_3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecF64ToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecF64ToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(11, 53, flRoundOpt_sigMSBitAlwaysZero))
roundRawFNToRecFN.io.invalidExc := divSqrtRecF64ToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecF64ToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecF64ToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecF64ToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module DivSqrtRecF64_mulAddZ31_1( // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
input clock, // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
input reset, // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_outValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output io_outValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [64:0] io_out, // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
output [4:0] io_exceptionFlags // @[DivSqrtRecF64_mulAddZ31.scala:721:16]
);
wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_invalidExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_infiniteExc; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isNaN; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isInf; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_isZero; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire _divSqrtRecF64ToRaw_io_rawOut_sign; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig; // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_detectTininess = 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7, :721:16, :775:15]
wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [64:0] io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
DivSqrtRecF64ToRaw_mulAddZ31_1 divSqrtRecF64ToRaw ( // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.clock (clock),
.reset (reset),
.io_inReady_div (io_inReady_div_0),
.io_inReady_sqrt (io_inReady_sqrt_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_a (io_a_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_b (io_b_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_usingMulAdd (io_usingMulAdd_0),
.io_latchMulAddA_0 (io_latchMulAddA_0_0),
.io_mulAddA_0 (io_mulAddA_0_0),
.io_latchMulAddB_0 (io_latchMulAddB_0_0),
.io_mulAddB_0 (io_mulAddB_0_0),
.io_mulAddC_2 (io_mulAddC_2_0),
.io_mulAddResult_3 (io_mulAddResult_3_0), // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
.io_rawOutValid_div (io_outValid_div_0),
.io_rawOutValid_sqrt (io_outValid_sqrt_0),
.io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig)
); // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
RoundRawFNToRecFN_e11_s53_3 roundRawFNToRecFN ( // @[DivSqrtRecF64_mulAddZ31.scala:775:15]
.io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut), // @[DivSqrtRecF64_mulAddZ31.scala:751:36]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[DivSqrtRecF64_mulAddZ31.scala:775:15]
assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_out = io_out_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecF64_mulAddZ31.scala:719:7]
endmodule |
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